/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c
C | 559 lines | 426 code | 97 blank | 36 comment | 94 complexity | e0dd3d84df2973edf1391d1dfc85cb49 MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
1/**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#include "vmwgfx_drv.h"
29#include "drmP.h"
30#include "ttm/ttm_placement.h"
31
32bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
33{
34 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
35 uint32_t fifo_min, hwversion;
36
37 if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
38 return false;
39
40 fifo_min = ioread32(fifo_mem + SVGA_FIFO_MIN);
41 if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
42 return false;
43
44 hwversion = ioread32(fifo_mem + SVGA_FIFO_3D_HWVERSION);
45 if (hwversion == 0)
46 return false;
47
48 if (hwversion < SVGA3D_HWVERSION_WS65_B1)
49 return false;
50
51 return true;
52}
53
54bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
55{
56 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
57 uint32_t caps;
58
59 if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
60 return false;
61
62 caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
63 if (caps & SVGA_FIFO_CAP_PITCHLOCK)
64 return true;
65
66 return false;
67}
68
69int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
70{
71 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
72 uint32_t max;
73 uint32_t min;
74 uint32_t dummy;
75 int ret;
76
77 fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
78 fifo->static_buffer = vmalloc(fifo->static_buffer_size);
79 if (unlikely(fifo->static_buffer == NULL))
80 return -ENOMEM;
81
82 fifo->last_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
83 fifo->last_data_size = 0;
84 fifo->last_buffer_add = false;
85 fifo->last_buffer = vmalloc(fifo->last_buffer_size);
86 if (unlikely(fifo->last_buffer == NULL)) {
87 ret = -ENOMEM;
88 goto out_err;
89 }
90
91 fifo->dynamic_buffer = NULL;
92 fifo->reserved_size = 0;
93 fifo->using_bounce_buffer = false;
94
95 mutex_init(&fifo->fifo_mutex);
96 init_rwsem(&fifo->rwsem);
97
98 /*
99 * Allow mapping the first page read-only to user-space.
100 */
101
102 DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
103 DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
104 DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
105
106 mutex_lock(&dev_priv->hw_mutex);
107 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
108 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
109 vmw_write(dev_priv, SVGA_REG_ENABLE, 1);
110
111 min = 4;
112 if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
113 min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
114 min <<= 2;
115
116 if (min < PAGE_SIZE)
117 min = PAGE_SIZE;
118
119 iowrite32(min, fifo_mem + SVGA_FIFO_MIN);
120 iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
121 wmb();
122 iowrite32(min, fifo_mem + SVGA_FIFO_NEXT_CMD);
123 iowrite32(min, fifo_mem + SVGA_FIFO_STOP);
124 iowrite32(0, fifo_mem + SVGA_FIFO_BUSY);
125 mb();
126
127 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
128 mutex_unlock(&dev_priv->hw_mutex);
129
130 max = ioread32(fifo_mem + SVGA_FIFO_MAX);
131 min = ioread32(fifo_mem + SVGA_FIFO_MIN);
132 fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
133
134 DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
135 (unsigned int) max,
136 (unsigned int) min,
137 (unsigned int) fifo->capabilities);
138
139 atomic_set(&dev_priv->fence_seq, dev_priv->last_read_sequence);
140 iowrite32(dev_priv->last_read_sequence, fifo_mem + SVGA_FIFO_FENCE);
141 vmw_fence_queue_init(&fifo->fence_queue);
142 return vmw_fifo_send_fence(dev_priv, &dummy);
143out_err:
144 vfree(fifo->static_buffer);
145 fifo->static_buffer = NULL;
146 return ret;
147}
148
149void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
150{
151 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
152
153 mutex_lock(&dev_priv->hw_mutex);
154
155 if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) {
156 iowrite32(1, fifo_mem + SVGA_FIFO_BUSY);
157 vmw_write(dev_priv, SVGA_REG_SYNC, reason);
158 }
159
160 mutex_unlock(&dev_priv->hw_mutex);
161}
162
163void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
164{
165 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
166
167 mutex_lock(&dev_priv->hw_mutex);
168
169 while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
170 vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
171
172 dev_priv->last_read_sequence = ioread32(fifo_mem + SVGA_FIFO_FENCE);
173
174 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
175 dev_priv->config_done_state);
176 vmw_write(dev_priv, SVGA_REG_ENABLE,
177 dev_priv->enable_state);
178
179 mutex_unlock(&dev_priv->hw_mutex);
180 vmw_fence_queue_takedown(&fifo->fence_queue);
181
182 if (likely(fifo->last_buffer != NULL)) {
183 vfree(fifo->last_buffer);
184 fifo->last_buffer = NULL;
185 }
186
187 if (likely(fifo->static_buffer != NULL)) {
188 vfree(fifo->static_buffer);
189 fifo->static_buffer = NULL;
190 }
191
192 if (likely(fifo->dynamic_buffer != NULL)) {
193 vfree(fifo->dynamic_buffer);
194 fifo->dynamic_buffer = NULL;
195 }
196}
197
198static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
199{
200 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
201 uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
202 uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
203 uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
204 uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
205
206 return ((max - next_cmd) + (stop - min) <= bytes);
207}
208
209static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
210 uint32_t bytes, bool interruptible,
211 unsigned long timeout)
212{
213 int ret = 0;
214 unsigned long end_jiffies = jiffies + timeout;
215 DEFINE_WAIT(__wait);
216
217 DRM_INFO("Fifo wait noirq.\n");
218
219 for (;;) {
220 prepare_to_wait(&dev_priv->fifo_queue, &__wait,
221 (interruptible) ?
222 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
223 if (!vmw_fifo_is_full(dev_priv, bytes))
224 break;
225 if (time_after_eq(jiffies, end_jiffies)) {
226 ret = -EBUSY;
227 DRM_ERROR("SVGA device lockup.\n");
228 break;
229 }
230 schedule_timeout(1);
231 if (interruptible && signal_pending(current)) {
232 ret = -ERESTARTSYS;
233 break;
234 }
235 }
236 finish_wait(&dev_priv->fifo_queue, &__wait);
237 wake_up_all(&dev_priv->fifo_queue);
238 DRM_INFO("Fifo noirq exit.\n");
239 return ret;
240}
241
242static int vmw_fifo_wait(struct vmw_private *dev_priv,
243 uint32_t bytes, bool interruptible,
244 unsigned long timeout)
245{
246 long ret = 1L;
247 unsigned long irq_flags;
248
249 if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
250 return 0;
251
252 vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
253 if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
254 return vmw_fifo_wait_noirq(dev_priv, bytes,
255 interruptible, timeout);
256
257 mutex_lock(&dev_priv->hw_mutex);
258 if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) {
259 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
260 outl(SVGA_IRQFLAG_FIFO_PROGRESS,
261 dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
262 vmw_write(dev_priv, SVGA_REG_IRQMASK,
263 vmw_read(dev_priv, SVGA_REG_IRQMASK) |
264 SVGA_IRQFLAG_FIFO_PROGRESS);
265 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
266 }
267 mutex_unlock(&dev_priv->hw_mutex);
268
269 if (interruptible)
270 ret = wait_event_interruptible_timeout
271 (dev_priv->fifo_queue,
272 !vmw_fifo_is_full(dev_priv, bytes), timeout);
273 else
274 ret = wait_event_timeout
275 (dev_priv->fifo_queue,
276 !vmw_fifo_is_full(dev_priv, bytes), timeout);
277
278 if (unlikely(ret == 0))
279 ret = -EBUSY;
280 else if (likely(ret > 0))
281 ret = 0;
282
283 mutex_lock(&dev_priv->hw_mutex);
284 if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) {
285 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
286 vmw_write(dev_priv, SVGA_REG_IRQMASK,
287 vmw_read(dev_priv, SVGA_REG_IRQMASK) &
288 ~SVGA_IRQFLAG_FIFO_PROGRESS);
289 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
290 }
291 mutex_unlock(&dev_priv->hw_mutex);
292
293 return ret;
294}
295
296void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes)
297{
298 struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
299 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
300 uint32_t max;
301 uint32_t min;
302 uint32_t next_cmd;
303 uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
304 int ret;
305
306 mutex_lock(&fifo_state->fifo_mutex);
307 max = ioread32(fifo_mem + SVGA_FIFO_MAX);
308 min = ioread32(fifo_mem + SVGA_FIFO_MIN);
309 next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
310
311 if (unlikely(bytes >= (max - min)))
312 goto out_err;
313
314 BUG_ON(fifo_state->reserved_size != 0);
315 BUG_ON(fifo_state->dynamic_buffer != NULL);
316
317 fifo_state->reserved_size = bytes;
318
319 while (1) {
320 uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
321 bool need_bounce = false;
322 bool reserve_in_place = false;
323
324 if (next_cmd >= stop) {
325 if (likely((next_cmd + bytes < max ||
326 (next_cmd + bytes == max && stop > min))))
327 reserve_in_place = true;
328
329 else if (vmw_fifo_is_full(dev_priv, bytes)) {
330 ret = vmw_fifo_wait(dev_priv, bytes,
331 false, 3 * HZ);
332 if (unlikely(ret != 0))
333 goto out_err;
334 } else
335 need_bounce = true;
336
337 } else {
338
339 if (likely((next_cmd + bytes < stop)))
340 reserve_in_place = true;
341 else {
342 ret = vmw_fifo_wait(dev_priv, bytes,
343 false, 3 * HZ);
344 if (unlikely(ret != 0))
345 goto out_err;
346 }
347 }
348
349 if (reserve_in_place) {
350 if (reserveable || bytes <= sizeof(uint32_t)) {
351 fifo_state->using_bounce_buffer = false;
352
353 if (reserveable)
354 iowrite32(bytes, fifo_mem +
355 SVGA_FIFO_RESERVED);
356 return fifo_mem + (next_cmd >> 2);
357 } else {
358 need_bounce = true;
359 }
360 }
361
362 if (need_bounce) {
363 fifo_state->using_bounce_buffer = true;
364 if (bytes < fifo_state->static_buffer_size)
365 return fifo_state->static_buffer;
366 else {
367 fifo_state->dynamic_buffer = vmalloc(bytes);
368 return fifo_state->dynamic_buffer;
369 }
370 }
371 }
372out_err:
373 fifo_state->reserved_size = 0;
374 mutex_unlock(&fifo_state->fifo_mutex);
375 return NULL;
376}
377
378static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
379 __le32 __iomem *fifo_mem,
380 uint32_t next_cmd,
381 uint32_t max, uint32_t min, uint32_t bytes)
382{
383 uint32_t chunk_size = max - next_cmd;
384 uint32_t rest;
385 uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
386 fifo_state->dynamic_buffer : fifo_state->static_buffer;
387
388 if (bytes < chunk_size)
389 chunk_size = bytes;
390
391 iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED);
392 mb();
393 memcpy_toio(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
394 rest = bytes - chunk_size;
395 if (rest)
396 memcpy_toio(fifo_mem + (min >> 2), buffer + (chunk_size >> 2),
397 rest);
398}
399
400static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
401 __le32 __iomem *fifo_mem,
402 uint32_t next_cmd,
403 uint32_t max, uint32_t min, uint32_t bytes)
404{
405 uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
406 fifo_state->dynamic_buffer : fifo_state->static_buffer;
407
408 while (bytes > 0) {
409 iowrite32(*buffer++, fifo_mem + (next_cmd >> 2));
410 next_cmd += sizeof(uint32_t);
411 if (unlikely(next_cmd == max))
412 next_cmd = min;
413 mb();
414 iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
415 mb();
416 bytes -= sizeof(uint32_t);
417 }
418}
419
420void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
421{
422 struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
423 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
424 uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
425 uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
426 uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
427 bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
428
429 BUG_ON((bytes & 3) != 0);
430 BUG_ON(bytes > fifo_state->reserved_size);
431
432 fifo_state->reserved_size = 0;
433
434 if (fifo_state->using_bounce_buffer) {
435 if (reserveable)
436 vmw_fifo_res_copy(fifo_state, fifo_mem,
437 next_cmd, max, min, bytes);
438 else
439 vmw_fifo_slow_copy(fifo_state, fifo_mem,
440 next_cmd, max, min, bytes);
441
442 if (fifo_state->dynamic_buffer) {
443 vfree(fifo_state->dynamic_buffer);
444 fifo_state->dynamic_buffer = NULL;
445 }
446
447 }
448
449 down_write(&fifo_state->rwsem);
450 if (fifo_state->using_bounce_buffer || reserveable) {
451 next_cmd += bytes;
452 if (next_cmd >= max)
453 next_cmd -= max - min;
454 mb();
455 iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
456 }
457
458 if (reserveable)
459 iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);
460 mb();
461 up_write(&fifo_state->rwsem);
462 vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
463 mutex_unlock(&fifo_state->fifo_mutex);
464}
465
466int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *sequence)
467{
468 struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
469 struct svga_fifo_cmd_fence *cmd_fence;
470 void *fm;
471 int ret = 0;
472 uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence);
473
474 fm = vmw_fifo_reserve(dev_priv, bytes);
475 if (unlikely(fm == NULL)) {
476 *sequence = atomic_read(&dev_priv->fence_seq);
477 ret = -ENOMEM;
478 (void)vmw_fallback_wait(dev_priv, false, true, *sequence,
479 false, 3*HZ);
480 goto out_err;
481 }
482
483 do {
484 *sequence = atomic_add_return(1, &dev_priv->fence_seq);
485 } while (*sequence == 0);
486
487 if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
488
489 /*
490 * Don't request hardware to send a fence. The
491 * waiting code in vmwgfx_irq.c will emulate this.
492 */
493
494 vmw_fifo_commit(dev_priv, 0);
495 return 0;
496 }
497
498 *(__le32 *) fm = cpu_to_le32(SVGA_CMD_FENCE);
499 cmd_fence = (struct svga_fifo_cmd_fence *)
500 ((unsigned long)fm + sizeof(__le32));
501
502 iowrite32(*sequence, &cmd_fence->fence);
503 fifo_state->last_buffer_add = true;
504 vmw_fifo_commit(dev_priv, bytes);
505 fifo_state->last_buffer_add = false;
506 (void) vmw_fence_push(&fifo_state->fence_queue, *sequence);
507 vmw_update_sequence(dev_priv, fifo_state);
508
509out_err:
510 return ret;
511}
512
513/**
514 * Map the first page of the FIFO read-only to user-space.
515 */
516
517static int vmw_fifo_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
518{
519 int ret;
520 unsigned long address = (unsigned long)vmf->virtual_address;
521
522 if (address != vma->vm_start)
523 return VM_FAULT_SIGBUS;
524
525 ret = vm_insert_pfn(vma, address, vma->vm_pgoff);
526 if (likely(ret == -EBUSY || ret == 0))
527 return VM_FAULT_NOPAGE;
528 else if (ret == -ENOMEM)
529 return VM_FAULT_OOM;
530
531 return VM_FAULT_SIGBUS;
532}
533
534static struct vm_operations_struct vmw_fifo_vm_ops = {
535 .fault = vmw_fifo_vm_fault,
536 .open = NULL,
537 .close = NULL
538};
539
540int vmw_fifo_mmap(struct file *filp, struct vm_area_struct *vma)
541{
542 struct drm_file *file_priv;
543 struct vmw_private *dev_priv;
544
545 file_priv = (struct drm_file *)filp->private_data;
546 dev_priv = vmw_priv(file_priv->minor->dev);
547
548 if (vma->vm_pgoff != (dev_priv->mmio_start >> PAGE_SHIFT) ||
549 (vma->vm_end - vma->vm_start) != PAGE_SIZE)
550 return -EINVAL;
551
552 vma->vm_flags &= ~(VM_WRITE | VM_MAYWRITE);
553 vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_SHARED;
554 vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
555 vma->vm_page_prot = ttm_io_prot(TTM_PL_FLAG_UNCACHED,
556 vma->vm_page_prot);
557 vma->vm_ops = &vmw_fifo_vm_ops;
558 return 0;
559}