/drivers/gpu/drm/radeon/radeon_reg.h

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  1. /*
  2. * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
  3. * VA Linux Systems Inc., Fremont, California.
  4. *
  5. * All Rights Reserved.
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining
  8. * a copy of this software and associated documentation files (the
  9. * "Software"), to deal in the Software without restriction, including
  10. * without limitation on the rights to use, copy, modify, merge,
  11. * publish, distribute, sublicense, and/or sell copies of the Software,
  12. * and to permit persons to whom the Software is furnished to do so,
  13. * subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the
  16. * next paragraph) shall be included in all copies or substantial
  17. * portions of the Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  20. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  22. * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
  23. * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  24. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  25. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26. * DEALINGS IN THE SOFTWARE.
  27. */
  28. /*
  29. * Authors:
  30. * Kevin E. Martin <martin@xfree86.org>
  31. * Rickard E. Faith <faith@valinux.com>
  32. * Alan Hourihane <alanh@fairlite.demon.co.uk>
  33. *
  34. * References:
  35. *
  36. * !!!! FIXME !!!!
  37. * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
  38. * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
  39. * 1999.
  40. *
  41. * !!!! FIXME !!!!
  42. * RAGE 128 Software Development Manual (Technical Reference Manual P/N
  43. * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
  44. *
  45. */
  46. /* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h
  47. * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT
  48. * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */
  49. #ifndef _RADEON_REG_H_
  50. #define _RADEON_REG_H_
  51. #include "r300_reg.h"
  52. #include "r500_reg.h"
  53. #include "r600_reg.h"
  54. #include "evergreen_reg.h"
  55. #define RADEON_MC_AGP_LOCATION 0x014c
  56. #define RADEON_MC_AGP_START_MASK 0x0000FFFF
  57. #define RADEON_MC_AGP_START_SHIFT 0
  58. #define RADEON_MC_AGP_TOP_MASK 0xFFFF0000
  59. #define RADEON_MC_AGP_TOP_SHIFT 16
  60. #define RADEON_MC_FB_LOCATION 0x0148
  61. #define RADEON_MC_FB_START_MASK 0x0000FFFF
  62. #define RADEON_MC_FB_START_SHIFT 0
  63. #define RADEON_MC_FB_TOP_MASK 0xFFFF0000
  64. #define RADEON_MC_FB_TOP_SHIFT 16
  65. #define RADEON_AGP_BASE_2 0x015c /* r200+ only */
  66. #define RADEON_AGP_BASE 0x0170
  67. #define ATI_DATATYPE_VQ 0
  68. #define ATI_DATATYPE_CI4 1
  69. #define ATI_DATATYPE_CI8 2
  70. #define ATI_DATATYPE_ARGB1555 3
  71. #define ATI_DATATYPE_RGB565 4
  72. #define ATI_DATATYPE_RGB888 5
  73. #define ATI_DATATYPE_ARGB8888 6
  74. #define ATI_DATATYPE_RGB332 7
  75. #define ATI_DATATYPE_Y8 8
  76. #define ATI_DATATYPE_RGB8 9
  77. #define ATI_DATATYPE_CI16 10
  78. #define ATI_DATATYPE_VYUY_422 11
  79. #define ATI_DATATYPE_YVYU_422 12
  80. #define ATI_DATATYPE_AYUV_444 14
  81. #define ATI_DATATYPE_ARGB4444 15
  82. /* Registers for 2D/Video/Overlay */
  83. #define RADEON_ADAPTER_ID 0x0f2c /* PCI */
  84. #define RADEON_AGP_BASE 0x0170
  85. #define RADEON_AGP_CNTL 0x0174
  86. # define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)
  87. # define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)
  88. # define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)
  89. # define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)
  90. # define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)
  91. # define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)
  92. # define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)
  93. # define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)
  94. #define RADEON_STATUS_PCI_CONFIG 0x06
  95. # define RADEON_CAP_LIST 0x100000
  96. #define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/
  97. # define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */
  98. # define RADEON_CAP_ID_NULL 0x00 /* End of capability list */
  99. # define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */
  100. # define RADEON_CAP_ID_EXP 0x10 /* PCI Express */
  101. #define RADEON_AGP_COMMAND 0x0f60 /* PCI */
  102. #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/
  103. # define RADEON_AGP_ENABLE (1<<8)
  104. #define RADEON_AGP_PLL_CNTL 0x000b /* PLL */
  105. #define RADEON_AGP_STATUS 0x0f5c /* PCI */
  106. # define RADEON_AGP_1X_MODE 0x01
  107. # define RADEON_AGP_2X_MODE 0x02
  108. # define RADEON_AGP_4X_MODE 0x04
  109. # define RADEON_AGP_FW_MODE 0x10
  110. # define RADEON_AGP_MODE_MASK 0x17
  111. # define RADEON_AGPv3_MODE 0x08
  112. # define RADEON_AGPv3_4X_MODE 0x01
  113. # define RADEON_AGPv3_8X_MODE 0x02
  114. #define RADEON_ATTRDR 0x03c1 /* VGA */
  115. #define RADEON_ATTRDW 0x03c0 /* VGA */
  116. #define RADEON_ATTRX 0x03c0 /* VGA */
  117. #define RADEON_AUX_SC_CNTL 0x1660
  118. # define RADEON_AUX1_SC_EN (1 << 0)
  119. # define RADEON_AUX1_SC_MODE_OR (0 << 1)
  120. # define RADEON_AUX1_SC_MODE_NAND (1 << 1)
  121. # define RADEON_AUX2_SC_EN (1 << 2)
  122. # define RADEON_AUX2_SC_MODE_OR (0 << 3)
  123. # define RADEON_AUX2_SC_MODE_NAND (1 << 3)
  124. # define RADEON_AUX3_SC_EN (1 << 4)
  125. # define RADEON_AUX3_SC_MODE_OR (0 << 5)
  126. # define RADEON_AUX3_SC_MODE_NAND (1 << 5)
  127. #define RADEON_AUX1_SC_BOTTOM 0x1670
  128. #define RADEON_AUX1_SC_LEFT 0x1664
  129. #define RADEON_AUX1_SC_RIGHT 0x1668
  130. #define RADEON_AUX1_SC_TOP 0x166c
  131. #define RADEON_AUX2_SC_BOTTOM 0x1680
  132. #define RADEON_AUX2_SC_LEFT 0x1674
  133. #define RADEON_AUX2_SC_RIGHT 0x1678
  134. #define RADEON_AUX2_SC_TOP 0x167c
  135. #define RADEON_AUX3_SC_BOTTOM 0x1690
  136. #define RADEON_AUX3_SC_LEFT 0x1684
  137. #define RADEON_AUX3_SC_RIGHT 0x1688
  138. #define RADEON_AUX3_SC_TOP 0x168c
  139. #define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8
  140. #define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc
  141. #define RADEON_BASE_CODE 0x0f0b
  142. #define RADEON_BIOS_0_SCRATCH 0x0010
  143. # define RADEON_FP_PANEL_SCALABLE (1 << 16)
  144. # define RADEON_FP_PANEL_SCALE_EN (1 << 17)
  145. # define RADEON_FP_CHIP_SCALE_EN (1 << 18)
  146. # define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26)
  147. # define RADEON_DISPLAY_ROT_MASK (3 << 28)
  148. # define RADEON_DISPLAY_ROT_00 (0 << 28)
  149. # define RADEON_DISPLAY_ROT_90 (1 << 28)
  150. # define RADEON_DISPLAY_ROT_180 (2 << 28)
  151. # define RADEON_DISPLAY_ROT_270 (3 << 28)
  152. #define RADEON_BIOS_1_SCRATCH 0x0014
  153. #define RADEON_BIOS_2_SCRATCH 0x0018
  154. #define RADEON_BIOS_3_SCRATCH 0x001c
  155. #define RADEON_BIOS_4_SCRATCH 0x0020
  156. # define RADEON_CRT1_ATTACHED_MASK (3 << 0)
  157. # define RADEON_CRT1_ATTACHED_MONO (1 << 0)
  158. # define RADEON_CRT1_ATTACHED_COLOR (2 << 0)
  159. # define RADEON_LCD1_ATTACHED (1 << 2)
  160. # define RADEON_DFP1_ATTACHED (1 << 3)
  161. # define RADEON_TV1_ATTACHED_MASK (3 << 4)
  162. # define RADEON_TV1_ATTACHED_COMP (1 << 4)
  163. # define RADEON_TV1_ATTACHED_SVIDEO (2 << 4)
  164. # define RADEON_CRT2_ATTACHED_MASK (3 << 8)
  165. # define RADEON_CRT2_ATTACHED_MONO (1 << 8)
  166. # define RADEON_CRT2_ATTACHED_COLOR (2 << 8)
  167. # define RADEON_DFP2_ATTACHED (1 << 11)
  168. #define RADEON_BIOS_5_SCRATCH 0x0024
  169. # define RADEON_LCD1_ON (1 << 0)
  170. # define RADEON_CRT1_ON (1 << 1)
  171. # define RADEON_TV1_ON (1 << 2)
  172. # define RADEON_DFP1_ON (1 << 3)
  173. # define RADEON_CRT2_ON (1 << 5)
  174. # define RADEON_CV1_ON (1 << 6)
  175. # define RADEON_DFP2_ON (1 << 7)
  176. # define RADEON_LCD1_CRTC_MASK (1 << 8)
  177. # define RADEON_LCD1_CRTC_SHIFT 8
  178. # define RADEON_CRT1_CRTC_MASK (1 << 9)
  179. # define RADEON_CRT1_CRTC_SHIFT 9
  180. # define RADEON_TV1_CRTC_MASK (1 << 10)
  181. # define RADEON_TV1_CRTC_SHIFT 10
  182. # define RADEON_DFP1_CRTC_MASK (1 << 11)
  183. # define RADEON_DFP1_CRTC_SHIFT 11
  184. # define RADEON_CRT2_CRTC_MASK (1 << 12)
  185. # define RADEON_CRT2_CRTC_SHIFT 12
  186. # define RADEON_CV1_CRTC_MASK (1 << 13)
  187. # define RADEON_CV1_CRTC_SHIFT 13
  188. # define RADEON_DFP2_CRTC_MASK (1 << 14)
  189. # define RADEON_DFP2_CRTC_SHIFT 14
  190. # define RADEON_ACC_REQ_LCD1 (1 << 16)
  191. # define RADEON_ACC_REQ_CRT1 (1 << 17)
  192. # define RADEON_ACC_REQ_TV1 (1 << 18)
  193. # define RADEON_ACC_REQ_DFP1 (1 << 19)
  194. # define RADEON_ACC_REQ_CRT2 (1 << 21)
  195. # define RADEON_ACC_REQ_TV2 (1 << 22)
  196. # define RADEON_ACC_REQ_DFP2 (1 << 23)
  197. #define RADEON_BIOS_6_SCRATCH 0x0028
  198. # define RADEON_ACC_MODE_CHANGE (1 << 2)
  199. # define RADEON_EXT_DESKTOP_MODE (1 << 3)
  200. # define RADEON_LCD_DPMS_ON (1 << 20)
  201. # define RADEON_CRT_DPMS_ON (1 << 21)
  202. # define RADEON_TV_DPMS_ON (1 << 22)
  203. # define RADEON_DFP_DPMS_ON (1 << 23)
  204. # define RADEON_DPMS_MASK (3 << 24)
  205. # define RADEON_DPMS_ON (0 << 24)
  206. # define RADEON_DPMS_STANDBY (1 << 24)
  207. # define RADEON_DPMS_SUSPEND (2 << 24)
  208. # define RADEON_DPMS_OFF (3 << 24)
  209. # define RADEON_SCREEN_BLANKING (1 << 26)
  210. # define RADEON_DRIVER_CRITICAL (1 << 27)
  211. # define RADEON_DISPLAY_SWITCHING_DIS (1 << 30)
  212. #define RADEON_BIOS_7_SCRATCH 0x002c
  213. # define RADEON_SYS_HOTKEY (1 << 10)
  214. # define RADEON_DRV_LOADED (1 << 12)
  215. #define RADEON_BIOS_ROM 0x0f30 /* PCI */
  216. #define RADEON_BIST 0x0f0f /* PCI */
  217. #define RADEON_BRUSH_DATA0 0x1480
  218. #define RADEON_BRUSH_DATA1 0x1484
  219. #define RADEON_BRUSH_DATA10 0x14a8
  220. #define RADEON_BRUSH_DATA11 0x14ac
  221. #define RADEON_BRUSH_DATA12 0x14b0
  222. #define RADEON_BRUSH_DATA13 0x14b4
  223. #define RADEON_BRUSH_DATA14 0x14b8
  224. #define RADEON_BRUSH_DATA15 0x14bc
  225. #define RADEON_BRUSH_DATA16 0x14c0
  226. #define RADEON_BRUSH_DATA17 0x14c4
  227. #define RADEON_BRUSH_DATA18 0x14c8
  228. #define RADEON_BRUSH_DATA19 0x14cc
  229. #define RADEON_BRUSH_DATA2 0x1488
  230. #define RADEON_BRUSH_DATA20 0x14d0
  231. #define RADEON_BRUSH_DATA21 0x14d4
  232. #define RADEON_BRUSH_DATA22 0x14d8
  233. #define RADEON_BRUSH_DATA23 0x14dc
  234. #define RADEON_BRUSH_DATA24 0x14e0
  235. #define RADEON_BRUSH_DATA25 0x14e4
  236. #define RADEON_BRUSH_DATA26 0x14e8
  237. #define RADEON_BRUSH_DATA27 0x14ec
  238. #define RADEON_BRUSH_DATA28 0x14f0
  239. #define RADEON_BRUSH_DATA29 0x14f4
  240. #define RADEON_BRUSH_DATA3 0x148c
  241. #define RADEON_BRUSH_DATA30 0x14f8
  242. #define RADEON_BRUSH_DATA31 0x14fc
  243. #define RADEON_BRUSH_DATA32 0x1500
  244. #define RADEON_BRUSH_DATA33 0x1504
  245. #define RADEON_BRUSH_DATA34 0x1508
  246. #define RADEON_BRUSH_DATA35 0x150c
  247. #define RADEON_BRUSH_DATA36 0x1510
  248. #define RADEON_BRUSH_DATA37 0x1514
  249. #define RADEON_BRUSH_DATA38 0x1518
  250. #define RADEON_BRUSH_DATA39 0x151c
  251. #define RADEON_BRUSH_DATA4 0x1490
  252. #define RADEON_BRUSH_DATA40 0x1520
  253. #define RADEON_BRUSH_DATA41 0x1524
  254. #define RADEON_BRUSH_DATA42 0x1528
  255. #define RADEON_BRUSH_DATA43 0x152c
  256. #define RADEON_BRUSH_DATA44 0x1530
  257. #define RADEON_BRUSH_DATA45 0x1534
  258. #define RADEON_BRUSH_DATA46 0x1538
  259. #define RADEON_BRUSH_DATA47 0x153c
  260. #define RADEON_BRUSH_DATA48 0x1540
  261. #define RADEON_BRUSH_DATA49 0x1544
  262. #define RADEON_BRUSH_DATA5 0x1494
  263. #define RADEON_BRUSH_DATA50 0x1548
  264. #define RADEON_BRUSH_DATA51 0x154c
  265. #define RADEON_BRUSH_DATA52 0x1550
  266. #define RADEON_BRUSH_DATA53 0x1554
  267. #define RADEON_BRUSH_DATA54 0x1558
  268. #define RADEON_BRUSH_DATA55 0x155c
  269. #define RADEON_BRUSH_DATA56 0x1560
  270. #define RADEON_BRUSH_DATA57 0x1564
  271. #define RADEON_BRUSH_DATA58 0x1568
  272. #define RADEON_BRUSH_DATA59 0x156c
  273. #define RADEON_BRUSH_DATA6 0x1498
  274. #define RADEON_BRUSH_DATA60 0x1570
  275. #define RADEON_BRUSH_DATA61 0x1574
  276. #define RADEON_BRUSH_DATA62 0x1578
  277. #define RADEON_BRUSH_DATA63 0x157c
  278. #define RADEON_BRUSH_DATA7 0x149c
  279. #define RADEON_BRUSH_DATA8 0x14a0
  280. #define RADEON_BRUSH_DATA9 0x14a4
  281. #define RADEON_BRUSH_SCALE 0x1470
  282. #define RADEON_BRUSH_Y_X 0x1474
  283. #define RADEON_BUS_CNTL 0x0030
  284. # define RADEON_BUS_MASTER_DIS (1 << 6)
  285. # define RADEON_BUS_BIOS_DIS_ROM (1 << 12)
  286. # define RS600_BUS_MASTER_DIS (1 << 14)
  287. # define RS600_MSI_REARM (1 << 20) /* rs600/rs690/rs740 */
  288. # define RADEON_BUS_RD_DISCARD_EN (1 << 24)
  289. # define RADEON_BUS_RD_ABORT_EN (1 << 25)
  290. # define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)
  291. # define RADEON_BUS_WRT_BURST (1 << 29)
  292. # define RADEON_BUS_READ_BURST (1 << 30)
  293. #define RADEON_BUS_CNTL1 0x0034
  294. # define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)
  295. /* rv370/rv380, rv410, r423/r430/r480, r5xx */
  296. #define RADEON_MSI_REARM_EN 0x0160
  297. # define RV370_MSI_REARM_EN (1 << 0)
  298. /* #define RADEON_PCIE_INDEX 0x0030 */
  299. /* #define RADEON_PCIE_DATA 0x0034 */
  300. #define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */
  301. # define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0
  302. # define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7
  303. # define RADEON_PCIE_LC_LINK_WIDTH_X0 0
  304. # define RADEON_PCIE_LC_LINK_WIDTH_X1 1
  305. # define RADEON_PCIE_LC_LINK_WIDTH_X2 2
  306. # define RADEON_PCIE_LC_LINK_WIDTH_X4 3
  307. # define RADEON_PCIE_LC_LINK_WIDTH_X8 4
  308. # define RADEON_PCIE_LC_LINK_WIDTH_X12 5
  309. # define RADEON_PCIE_LC_LINK_WIDTH_X16 6
  310. # define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4
  311. # define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70
  312. # define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8)
  313. # define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9)
  314. # define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10)
  315. #define RADEON_CACHE_CNTL 0x1724
  316. #define RADEON_CACHE_LINE 0x0f0c /* PCI */
  317. #define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */
  318. #define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */
  319. #define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */
  320. # define RADEON_DONT_USE_XTALIN (1 << 4)
  321. # define RADEON_SCLK_DYN_START_CNTL (1 << 15)
  322. #define RADEON_CLOCK_CNTL_DATA 0x000c
  323. #define RADEON_CLOCK_CNTL_INDEX 0x0008
  324. # define RADEON_PLL_WR_EN (1 << 7)
  325. # define RADEON_PLL_DIV_SEL (3 << 8)
  326. # define RADEON_PLL2_DIV_SEL_MASK (~(3 << 8))
  327. #define RADEON_CLK_PWRMGT_CNTL 0x0014
  328. # define RADEON_ENGIN_DYNCLK_MODE (1 << 12)
  329. # define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13)
  330. # define RADEON_ACTIVE_HILO_LAT_SHIFT 13
  331. # define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12)
  332. # define RADEON_MC_BUSY (1 << 16)
  333. # define RADEON_DLL_READY (1 << 19)
  334. # define RADEON_CG_NO1_DEBUG_0 (1 << 24)
  335. # define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24)
  336. # define RADEON_DYN_STOP_MODE_MASK (7 << 21)
  337. # define RADEON_TVPLL_PWRMGT_OFF (1 << 30)
  338. # define RADEON_TVCLK_TURNOFF (1 << 31)
  339. #define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */
  340. # define RADEON_PM_MODE_SEL (1 << 13)
  341. # define RADEON_TCL_BYPASS_DISABLE (1 << 20)
  342. #define RADEON_CLR_CMP_CLR_3D 0x1a24
  343. #define RADEON_CLR_CMP_CLR_DST 0x15c8
  344. #define RADEON_CLR_CMP_CLR_SRC 0x15c4
  345. #define RADEON_CLR_CMP_CNTL 0x15c0
  346. # define RADEON_SRC_CMP_EQ_COLOR (4 << 0)
  347. # define RADEON_SRC_CMP_NEQ_COLOR (5 << 0)
  348. # define RADEON_CLR_CMP_SRC_SOURCE (1 << 24)
  349. #define RADEON_CLR_CMP_MASK 0x15cc
  350. # define RADEON_CLR_CMP_MSK 0xffffffff
  351. #define RADEON_CLR_CMP_MASK_3D 0x1A28
  352. #define RADEON_COMMAND 0x0f04 /* PCI */
  353. #define RADEON_COMPOSITE_SHADOW_ID 0x1a0c
  354. #define RADEON_CONFIG_APER_0_BASE 0x0100
  355. #define RADEON_CONFIG_APER_1_BASE 0x0104
  356. #define RADEON_CONFIG_APER_SIZE 0x0108
  357. #define RADEON_CONFIG_BONDS 0x00e8
  358. #define RADEON_CONFIG_CNTL 0x00e0
  359. # define RADEON_CFG_ATI_REV_A11 (0 << 16)
  360. # define RADEON_CFG_ATI_REV_A12 (1 << 16)
  361. # define RADEON_CFG_ATI_REV_A13 (2 << 16)
  362. # define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16)
  363. #define RADEON_CONFIG_MEMSIZE 0x00f8
  364. #define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114
  365. #define RADEON_CONFIG_REG_1_BASE 0x010c
  366. #define RADEON_CONFIG_REG_APER_SIZE 0x0110
  367. #define RADEON_CONFIG_XSTRAP 0x00e4
  368. #define RADEON_CONSTANT_COLOR_C 0x1d34
  369. # define RADEON_CONSTANT_COLOR_MASK 0x00ffffff
  370. # define RADEON_CONSTANT_COLOR_ONE 0x00ffffff
  371. # define RADEON_CONSTANT_COLOR_ZERO 0x00000000
  372. #define RADEON_CRC_CMDFIFO_ADDR 0x0740
  373. #define RADEON_CRC_CMDFIFO_DOUT 0x0744
  374. #define RADEON_GRPH_BUFFER_CNTL 0x02f0
  375. # define RADEON_GRPH_START_REQ_MASK (0x7f)
  376. # define RADEON_GRPH_START_REQ_SHIFT 0
  377. # define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)
  378. # define RADEON_GRPH_STOP_REQ_SHIFT 8
  379. # define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)
  380. # define RADEON_GRPH_CRITICAL_POINT_SHIFT 16
  381. # define RADEON_GRPH_CRITICAL_CNTL (1<<28)
  382. # define RADEON_GRPH_BUFFER_SIZE (1<<29)
  383. # define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)
  384. # define RADEON_GRPH_STOP_CNTL (1<<31)
  385. #define RADEON_GRPH2_BUFFER_CNTL 0x03f0
  386. # define RADEON_GRPH2_START_REQ_MASK (0x7f)
  387. # define RADEON_GRPH2_START_REQ_SHIFT 0
  388. # define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)
  389. # define RADEON_GRPH2_STOP_REQ_SHIFT 8
  390. # define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)
  391. # define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16
  392. # define RADEON_GRPH2_CRITICAL_CNTL (1<<28)
  393. # define RADEON_GRPH2_BUFFER_SIZE (1<<29)
  394. # define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)
  395. # define RADEON_GRPH2_STOP_CNTL (1<<31)
  396. #define RADEON_CRTC_CRNT_FRAME 0x0214
  397. #define RADEON_CRTC_EXT_CNTL 0x0054
  398. # define RADEON_CRTC_VGA_XOVERSCAN (1 << 0)
  399. # define RADEON_VGA_ATI_LINEAR (1 << 3)
  400. # define RADEON_XCRT_CNT_EN (1 << 6)
  401. # define RADEON_CRTC_HSYNC_DIS (1 << 8)
  402. # define RADEON_CRTC_VSYNC_DIS (1 << 9)
  403. # define RADEON_CRTC_DISPLAY_DIS (1 << 10)
  404. # define RADEON_CRTC_SYNC_TRISTAT (1 << 11)
  405. # define RADEON_CRTC_CRT_ON (1 << 15)
  406. #define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055
  407. # define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0)
  408. # define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1)
  409. # define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2)
  410. #define RADEON_CRTC_GEN_CNTL 0x0050
  411. # define RADEON_CRTC_DBL_SCAN_EN (1 << 0)
  412. # define RADEON_CRTC_INTERLACE_EN (1 << 1)
  413. # define RADEON_CRTC_CSYNC_EN (1 << 4)
  414. # define RADEON_CRTC_ICON_EN (1 << 15)
  415. # define RADEON_CRTC_CUR_EN (1 << 16)
  416. # define RADEON_CRTC_CUR_MODE_MASK (7 << 20)
  417. # define RADEON_CRTC_CUR_MODE_SHIFT 20
  418. # define RADEON_CRTC_CUR_MODE_MONO 0
  419. # define RADEON_CRTC_CUR_MODE_24BPP 2
  420. # define RADEON_CRTC_EXT_DISP_EN (1 << 24)
  421. # define RADEON_CRTC_EN (1 << 25)
  422. # define RADEON_CRTC_DISP_REQ_EN_B (1 << 26)
  423. #define RADEON_CRTC2_GEN_CNTL 0x03f8
  424. # define RADEON_CRTC2_DBL_SCAN_EN (1 << 0)
  425. # define RADEON_CRTC2_INTERLACE_EN (1 << 1)
  426. # define RADEON_CRTC2_SYNC_TRISTAT (1 << 4)
  427. # define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5)
  428. # define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6)
  429. # define RADEON_CRTC2_CRT2_ON (1 << 7)
  430. # define RADEON_CRTC2_PIX_WIDTH_SHIFT 8
  431. # define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8)
  432. # define RADEON_CRTC2_ICON_EN (1 << 15)
  433. # define RADEON_CRTC2_CUR_EN (1 << 16)
  434. # define RADEON_CRTC2_CUR_MODE_MASK (7 << 20)
  435. # define RADEON_CRTC2_DISP_DIS (1 << 23)
  436. # define RADEON_CRTC2_EN (1 << 25)
  437. # define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26)
  438. # define RADEON_CRTC2_CSYNC_EN (1 << 27)
  439. # define RADEON_CRTC2_HSYNC_DIS (1 << 28)
  440. # define RADEON_CRTC2_VSYNC_DIS (1 << 29)
  441. #define RADEON_CRTC_MORE_CNTL 0x27c
  442. # define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2)
  443. # define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3)
  444. # define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
  445. # define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
  446. #define RADEON_CRTC_GUI_TRIG_VLINE 0x0218
  447. #define RADEON_CRTC_H_SYNC_STRT_WID 0x0204
  448. # define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0)
  449. # define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)
  450. # define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3
  451. # define RADEON_CRTC_H_SYNC_WID (0x3f << 16)
  452. # define RADEON_CRTC_H_SYNC_WID_SHIFT 16
  453. # define RADEON_CRTC_H_SYNC_POL (1 << 23)
  454. #define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304
  455. # define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0)
  456. # define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)
  457. # define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3
  458. # define RADEON_CRTC2_H_SYNC_WID (0x3f << 16)
  459. # define RADEON_CRTC2_H_SYNC_WID_SHIFT 16
  460. # define RADEON_CRTC2_H_SYNC_POL (1 << 23)
  461. #define RADEON_CRTC_H_TOTAL_DISP 0x0200
  462. # define RADEON_CRTC_H_TOTAL (0x03ff << 0)
  463. # define RADEON_CRTC_H_TOTAL_SHIFT 0
  464. # define RADEON_CRTC_H_DISP (0x01ff << 16)
  465. # define RADEON_CRTC_H_DISP_SHIFT 16
  466. #define RADEON_CRTC2_H_TOTAL_DISP 0x0300
  467. # define RADEON_CRTC2_H_TOTAL (0x03ff << 0)
  468. # define RADEON_CRTC2_H_TOTAL_SHIFT 0
  469. # define RADEON_CRTC2_H_DISP (0x01ff << 16)
  470. # define RADEON_CRTC2_H_DISP_SHIFT 16
  471. #define RADEON_CRTC_OFFSET_RIGHT 0x0220
  472. #define RADEON_CRTC_OFFSET 0x0224
  473. # define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30)
  474. # define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31)
  475. #define RADEON_CRTC2_OFFSET 0x0324
  476. # define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30)
  477. # define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31)
  478. #define RADEON_CRTC_OFFSET_CNTL 0x0228
  479. # define RADEON_CRTC_TILE_LINE_SHIFT 0
  480. # define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4
  481. # define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6)
  482. # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7)
  483. # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7)
  484. # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7)
  485. # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7)
  486. # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7)
  487. # define R300_CRTC_X_Y_MODE_EN (1 << 9)
  488. # define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10)
  489. # define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10)
  490. # define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10)
  491. # define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10)
  492. # define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10)
  493. # define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12)
  494. # define R300_CRTC_MICRO_TILE_EN (1 << 13)
  495. # define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14)
  496. # define R300_CRTC_MACRO_TILE_EN (1 << 15)
  497. # define RADEON_CRTC_TILE_EN_RIGHT (1 << 14)
  498. # define RADEON_CRTC_TILE_EN (1 << 15)
  499. # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
  500. # define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17)
  501. #define R300_CRTC_TILE_X0_Y0 0x0350
  502. #define R300_CRTC2_TILE_X0_Y0 0x0358
  503. #define RADEON_CRTC2_OFFSET_CNTL 0x0328
  504. # define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16)
  505. # define RADEON_CRTC2_TILE_EN (1 << 15)
  506. #define RADEON_CRTC_PITCH 0x022c
  507. # define RADEON_CRTC_PITCH__SHIFT 0
  508. # define RADEON_CRTC_PITCH__RIGHT_SHIFT 16
  509. #define RADEON_CRTC2_PITCH 0x032c
  510. #define RADEON_CRTC_STATUS 0x005c
  511. # define RADEON_CRTC_VBLANK_SAVE (1 << 1)
  512. # define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1)
  513. #define RADEON_CRTC2_STATUS 0x03fc
  514. # define RADEON_CRTC2_VBLANK_SAVE (1 << 1)
  515. # define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1)
  516. #define RADEON_CRTC_V_SYNC_STRT_WID 0x020c
  517. # define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0)
  518. # define RADEON_CRTC_V_SYNC_STRT_SHIFT 0
  519. # define RADEON_CRTC_V_SYNC_WID (0x1f << 16)
  520. # define RADEON_CRTC_V_SYNC_WID_SHIFT 16
  521. # define RADEON_CRTC_V_SYNC_POL (1 << 23)
  522. #define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c
  523. # define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0)
  524. # define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0
  525. # define RADEON_CRTC2_V_SYNC_WID (0x1f << 16)
  526. # define RADEON_CRTC2_V_SYNC_WID_SHIFT 16
  527. # define RADEON_CRTC2_V_SYNC_POL (1 << 23)
  528. #define RADEON_CRTC_V_TOTAL_DISP 0x0208
  529. # define RADEON_CRTC_V_TOTAL (0x07ff << 0)
  530. # define RADEON_CRTC_V_TOTAL_SHIFT 0
  531. # define RADEON_CRTC_V_DISP (0x07ff << 16)
  532. # define RADEON_CRTC_V_DISP_SHIFT 16
  533. #define RADEON_CRTC2_V_TOTAL_DISP 0x0308
  534. # define RADEON_CRTC2_V_TOTAL (0x07ff << 0)
  535. # define RADEON_CRTC2_V_TOTAL_SHIFT 0
  536. # define RADEON_CRTC2_V_DISP (0x07ff << 16)
  537. # define RADEON_CRTC2_V_DISP_SHIFT 16
  538. #define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210
  539. # define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16)
  540. #define RADEON_CRTC2_CRNT_FRAME 0x0314
  541. #define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318
  542. #define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310
  543. #define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */
  544. #define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */
  545. #define RADEON_CUR_CLR0 0x026c
  546. #define RADEON_CUR_CLR1 0x0270
  547. #define RADEON_CUR_HORZ_VERT_OFF 0x0268
  548. #define RADEON_CUR_HORZ_VERT_POSN 0x0264
  549. #define RADEON_CUR_OFFSET 0x0260
  550. # define RADEON_CUR_LOCK (1 << 31)
  551. #define RADEON_CUR2_CLR0 0x036c
  552. #define RADEON_CUR2_CLR1 0x0370
  553. #define RADEON_CUR2_HORZ_VERT_OFF 0x0368
  554. #define RADEON_CUR2_HORZ_VERT_POSN 0x0364
  555. #define RADEON_CUR2_OFFSET 0x0360
  556. # define RADEON_CUR2_LOCK (1 << 31)
  557. #define RADEON_DAC_CNTL 0x0058
  558. # define RADEON_DAC_RANGE_CNTL (3 << 0)
  559. # define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0)
  560. # define RADEON_DAC_RANGE_CNTL_MASK 0x03
  561. # define RADEON_DAC_BLANKING (1 << 2)
  562. # define RADEON_DAC_CMP_EN (1 << 3)
  563. # define RADEON_DAC_CMP_OUTPUT (1 << 7)
  564. # define RADEON_DAC_8BIT_EN (1 << 8)
  565. # define RADEON_DAC_TVO_EN (1 << 10)
  566. # define RADEON_DAC_VGA_ADR_EN (1 << 13)
  567. # define RADEON_DAC_PDWN (1 << 15)
  568. # define RADEON_DAC_MASK_ALL (0xff << 24)
  569. #define RADEON_DAC_CNTL2 0x007c
  570. # define RADEON_DAC2_TV_CLK_SEL (0 << 1)
  571. # define RADEON_DAC2_DAC_CLK_SEL (1 << 0)
  572. # define RADEON_DAC2_DAC2_CLK_SEL (1 << 1)
  573. # define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5)
  574. # define RADEON_DAC2_CMP_EN (1 << 7)
  575. # define RADEON_DAC2_CMP_OUT_R (1 << 8)
  576. # define RADEON_DAC2_CMP_OUT_G (1 << 9)
  577. # define RADEON_DAC2_CMP_OUT_B (1 << 10)
  578. # define RADEON_DAC2_CMP_OUTPUT (1 << 11)
  579. #define RADEON_DAC_EXT_CNTL 0x0280
  580. # define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0)
  581. # define RADEON_DAC2_FORCE_DATA_EN (1 << 1)
  582. # define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)
  583. # define RADEON_DAC_FORCE_DATA_EN (1 << 5)
  584. # define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)
  585. # define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6)
  586. # define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6)
  587. # define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6)
  588. # define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6)
  589. # define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00
  590. # define RADEON_DAC_FORCE_DATA_SHIFT 8
  591. #define RADEON_DAC_MACRO_CNTL 0x0d04
  592. # define RADEON_DAC_PDWN_R (1 << 16)
  593. # define RADEON_DAC_PDWN_G (1 << 17)
  594. # define RADEON_DAC_PDWN_B (1 << 18)
  595. #define RADEON_DISP_PWR_MAN 0x0d08
  596. # define RADEON_DISP_PWR_MAN_D3_CRTC_EN (1 << 0)
  597. # define RADEON_DISP_PWR_MAN_D3_CRTC2_EN (1 << 4)
  598. # define RADEON_DISP_PWR_MAN_DPMS_ON (0 << 8)
  599. # define RADEON_DISP_PWR_MAN_DPMS_STANDBY (1 << 8)
  600. # define RADEON_DISP_PWR_MAN_DPMS_SUSPEND (2 << 8)
  601. # define RADEON_DISP_PWR_MAN_DPMS_OFF (3 << 8)
  602. # define RADEON_DISP_D3_RST (1 << 16)
  603. # define RADEON_DISP_D3_REG_RST (1 << 17)
  604. # define RADEON_DISP_D3_GRPH_RST (1 << 18)
  605. # define RADEON_DISP_D3_SUBPIC_RST (1 << 19)
  606. # define RADEON_DISP_D3_OV0_RST (1 << 20)
  607. # define RADEON_DISP_D1D2_GRPH_RST (1 << 21)
  608. # define RADEON_DISP_D1D2_SUBPIC_RST (1 << 22)
  609. # define RADEON_DISP_D1D2_OV0_RST (1 << 23)
  610. # define RADEON_DIG_TMDS_ENABLE_RST (1 << 24)
  611. # define RADEON_TV_ENABLE_RST (1 << 25)
  612. # define RADEON_AUTO_PWRUP_EN (1 << 26)
  613. #define RADEON_TV_DAC_CNTL 0x088c
  614. # define RADEON_TV_DAC_NBLANK (1 << 0)
  615. # define RADEON_TV_DAC_NHOLD (1 << 1)
  616. # define RADEON_TV_DAC_PEDESTAL (1 << 2)
  617. # define RADEON_TV_MONITOR_DETECT_EN (1 << 4)
  618. # define RADEON_TV_DAC_CMPOUT (1 << 5)
  619. # define RADEON_TV_DAC_STD_MASK (3 << 8)
  620. # define RADEON_TV_DAC_STD_PAL (0 << 8)
  621. # define RADEON_TV_DAC_STD_NTSC (1 << 8)
  622. # define RADEON_TV_DAC_STD_PS2 (2 << 8)
  623. # define RADEON_TV_DAC_STD_RS343 (3 << 8)
  624. # define RADEON_TV_DAC_BGSLEEP (1 << 6)
  625. # define RADEON_TV_DAC_BGADJ_MASK (0xf << 16)
  626. # define RADEON_TV_DAC_BGADJ_SHIFT 16
  627. # define RADEON_TV_DAC_DACADJ_MASK (0xf << 20)
  628. # define RADEON_TV_DAC_DACADJ_SHIFT 20
  629. # define RADEON_TV_DAC_RDACPD (1 << 24)
  630. # define RADEON_TV_DAC_GDACPD (1 << 25)
  631. # define RADEON_TV_DAC_BDACPD (1 << 26)
  632. # define RADEON_TV_DAC_RDACDET (1 << 29)
  633. # define RADEON_TV_DAC_GDACDET (1 << 30)
  634. # define RADEON_TV_DAC_BDACDET (1 << 31)
  635. # define R420_TV_DAC_DACADJ_MASK (0x1f << 20)
  636. # define R420_TV_DAC_RDACPD (1 << 25)
  637. # define R420_TV_DAC_GDACPD (1 << 26)
  638. # define R420_TV_DAC_BDACPD (1 << 27)
  639. # define R420_TV_DAC_TVENABLE (1 << 28)
  640. #define RADEON_DISP_HW_DEBUG 0x0d14
  641. # define RADEON_CRT2_DISP1_SEL (1 << 5)
  642. #define RADEON_DISP_OUTPUT_CNTL 0x0d64
  643. # define RADEON_DISP_DAC_SOURCE_MASK 0x03
  644. # define RADEON_DISP_DAC2_SOURCE_MASK 0x0c
  645. # define RADEON_DISP_DAC_SOURCE_CRTC2 0x01
  646. # define RADEON_DISP_DAC_SOURCE_RMX 0x02
  647. # define RADEON_DISP_DAC_SOURCE_LTU 0x03
  648. # define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04
  649. # define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2)
  650. # define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0
  651. # define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2)
  652. # define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2)
  653. # define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2)
  654. # define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4)
  655. # define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4)
  656. # define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4)
  657. # define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4)
  658. # define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */
  659. # define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */
  660. #define RADEON_DISP_TV_OUT_CNTL 0x0d6c
  661. # define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16)
  662. # define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16)
  663. #define RADEON_DAC_CRC_SIG 0x02cc
  664. #define RADEON_DAC_DATA 0x03c9 /* VGA */
  665. #define RADEON_DAC_MASK 0x03c6 /* VGA */
  666. #define RADEON_DAC_R_INDEX 0x03c7 /* VGA */
  667. #define RADEON_DAC_W_INDEX 0x03c8 /* VGA */
  668. #define RADEON_DDA_CONFIG 0x02e0
  669. #define RADEON_DDA_ON_OFF 0x02e4
  670. #define RADEON_DEFAULT_OFFSET 0x16e0
  671. #define RADEON_DEFAULT_PITCH 0x16e4
  672. #define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8
  673. # define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
  674. # define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
  675. #define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820
  676. #define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824
  677. #define RADEON_DEVICE_ID 0x0f02 /* PCI */
  678. #define RADEON_DISP_MISC_CNTL 0x0d00
  679. # define RADEON_SOFT_RESET_GRPH_PP (1 << 0)
  680. #define RADEON_DISP_MERGE_CNTL 0x0d60
  681. # define RADEON_DISP_ALPHA_MODE_MASK 0x03
  682. # define RADEON_DISP_ALPHA_MODE_KEY 0
  683. # define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1
  684. # define RADEON_DISP_ALPHA_MODE_GLOBAL 2
  685. # define RADEON_DISP_RGB_OFFSET_EN (1 << 8)
  686. # define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16)
  687. # define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24)
  688. # define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)
  689. #define RADEON_DISP2_MERGE_CNTL 0x0d68
  690. # define RADEON_DISP2_RGB_OFFSET_EN (1 << 8)
  691. #define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80
  692. #define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84
  693. #define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88
  694. #define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c
  695. #define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90
  696. #define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98
  697. #define RADEON_DP_BRUSH_BKGD_CLR 0x1478
  698. #define RADEON_DP_BRUSH_FRGD_CLR 0x147c
  699. #define RADEON_DP_CNTL 0x16c0
  700. # define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0)
  701. # define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1)
  702. # define RADEON_DP_DST_TILE_LINEAR (0 << 3)
  703. # define RADEON_DP_DST_TILE_MACRO (1 << 3)
  704. # define RADEON_DP_DST_TILE_MICRO (2 << 3)
  705. # define RADEON_DP_DST_TILE_BOTH (3 << 3)
  706. #define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
  707. # define RADEON_DST_Y_MAJOR (1 << 2)
  708. # define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)
  709. # define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)
  710. #define RADEON_DP_DATATYPE 0x16c4
  711. # define RADEON_HOST_BIG_ENDIAN_EN (1 << 29)
  712. #define RADEON_DP_GUI_MASTER_CNTL 0x146c
  713. # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
  714. # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
  715. # define RADEON_GMC_SRC_CLIPPING (1 << 2)
  716. # define RADEON_GMC_DST_CLIPPING (1 << 3)
  717. # define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4)
  718. # define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4)
  719. # define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4)
  720. # define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4)
  721. # define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4)
  722. # define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4)
  723. # define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4)
  724. # define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4)
  725. # define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4)
  726. # define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4)
  727. # define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4)
  728. # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
  729. # define RADEON_GMC_BRUSH_NONE (15 << 4)
  730. # define RADEON_GMC_DST_8BPP_CI (2 << 8)
  731. # define RADEON_GMC_DST_15BPP (3 << 8)
  732. # define RADEON_GMC_DST_16BPP (4 << 8)
  733. # define RADEON_GMC_DST_24BPP (5 << 8)
  734. # define RADEON_GMC_DST_32BPP (6 << 8)
  735. # define RADEON_GMC_DST_8BPP_RGB (7 << 8)
  736. # define RADEON_GMC_DST_Y8 (8 << 8)
  737. # define RADEON_GMC_DST_RGB8 (9 << 8)
  738. # define RADEON_GMC_DST_VYUY (11 << 8)
  739. # define RADEON_GMC_DST_YVYU (12 << 8)
  740. # define RADEON_GMC_DST_AYUV444 (14 << 8)
  741. # define RADEON_GMC_DST_ARGB4444 (15 << 8)
  742. # define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8)
  743. # define RADEON_GMC_DST_DATATYPE_SHIFT 8
  744. # define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12)
  745. # define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)
  746. # define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)
  747. # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
  748. # define RADEON_GMC_BYTE_PIX_ORDER (1 << 14)
  749. # define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14)
  750. # define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14)
  751. # define RADEON_GMC_CONVERSION_TEMP (1 << 15)
  752. # define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15)
  753. # define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15)
  754. # define RADEON_GMC_ROP3_MASK (0xff << 16)
  755. # define RADEON_DP_SRC_SOURCE_MASK (7 << 24)
  756. # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
  757. # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
  758. # define RADEON_GMC_3D_FCN_EN (1 << 27)
  759. # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
  760. # define RADEON_GMC_AUX_CLIP_DIS (1 << 29)
  761. # define RADEON_GMC_WR_MSK_DIS (1 << 30)
  762. # define RADEON_GMC_LD_BRUSH_Y_X (1 << 31)
  763. # define RADEON_ROP3_ZERO 0x00000000
  764. # define RADEON_ROP3_DSa 0x00880000
  765. # define RADEON_ROP3_SDna 0x00440000
  766. # define RADEON_ROP3_S 0x00cc0000
  767. # define RADEON_ROP3_DSna 0x00220000
  768. # define RADEON_ROP3_D 0x00aa0000
  769. # define RADEON_ROP3_DSx 0x00660000
  770. # define RADEON_ROP3_DSo 0x00ee0000
  771. # define RADEON_ROP3_DSon 0x00110000
  772. # define RADEON_ROP3_DSxn 0x00990000
  773. # define RADEON_ROP3_Dn 0x00550000
  774. # define RADEON_ROP3_SDno 0x00dd0000
  775. # define RADEON_ROP3_Sn 0x00330000
  776. # define RADEON_ROP3_DSno 0x00bb0000
  777. # define RADEON_ROP3_DSan 0x00770000
  778. # define RADEON_ROP3_ONE 0x00ff0000
  779. # define RADEON_ROP3_DPa 0x00a00000
  780. # define RADEON_ROP3_PDna 0x00500000
  781. # define RADEON_ROP3_P 0x00f00000
  782. # define RADEON_ROP3_DPna 0x000a0000
  783. # define RADEON_ROP3_D 0x00aa0000
  784. # define RADEON_ROP3_DPx 0x005a0000
  785. # define RADEON_ROP3_DPo 0x00fa0000
  786. # define RADEON_ROP3_DPon 0x00050000
  787. # define RADEON_ROP3_PDxn 0x00a50000
  788. # define RADEON_ROP3_PDno 0x00f50000
  789. # define RADEON_ROP3_Pn 0x000f0000
  790. # define RADEON_ROP3_DPno 0x00af0000
  791. # define RADEON_ROP3_DPan 0x005f0000
  792. #define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84
  793. #define RADEON_DP_MIX 0x16c8
  794. #define RADEON_DP_SRC_BKGD_CLR 0x15dc
  795. #define RADEON_DP_SRC_FRGD_CLR 0x15d8
  796. #define RADEON_DP_WRITE_MASK 0x16cc
  797. #define RADEON_DST_BRES_DEC 0x1630
  798. #define RADEON_DST_BRES_ERR 0x1628
  799. #define RADEON_DST_BRES_INC 0x162c
  800. #define RADEON_DST_BRES_LNTH 0x1634
  801. #define RADEON_DST_BRES_LNTH_SUB 0x1638
  802. #define RADEON_DST_HEIGHT 0x1410
  803. #define RADEON_DST_HEIGHT_WIDTH 0x143c
  804. #define RADEON_DST_HEIGHT_WIDTH_8 0x158c
  805. #define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4
  806. #define RADEON_DST_HEIGHT_Y 0x15a0
  807. #define RADEON_DST_LINE_START 0x1600
  808. #define RADEON_DST_LINE_END 0x1604
  809. #define RADEON_DST_LINE_PATCOUNT 0x1608
  810. # define RADEON_BRES_CNTL_SHIFT 8
  811. #define RADEON_DST_OFFSET 0x1404
  812. #define RADEON_DST_PITCH 0x1408
  813. #define RADEON_DST_PITCH_OFFSET 0x142c
  814. #define RADEON_DST_PITCH_OFFSET_C 0x1c80
  815. # define RADEON_PITCH_SHIFT 21
  816. # define RADEON_DST_TILE_LINEAR (0 << 30)
  817. # define RADEON_DST_TILE_MACRO (1 << 30)
  818. # define RADEON_DST_TILE_MICRO (2 << 30)
  819. # define RADEON_DST_TILE_BOTH (3 << 30)
  820. #define RADEON_DST_WIDTH 0x140c
  821. #define RADEON_DST_WIDTH_HEIGHT 0x1598
  822. #define RADEON_DST_WIDTH_X 0x1588
  823. #define RADEON_DST_WIDTH_X_INCY 0x159c
  824. #define RADEON_DST_X 0x141c
  825. #define RADEON_DST_X_SUB 0x15a4
  826. #define RADEON_DST_X_Y 0x1594
  827. #define RADEON_DST_Y 0x1420
  828. #define RADEON_DST_Y_SUB 0x15a8
  829. #define RADEON_DST_Y_X 0x1438
  830. #define RADEON_FCP_CNTL 0x0910
  831. # define RADEON_FCP0_SRC_PCICLK 0
  832. # define RADEON_FCP0_SRC_PCLK 1
  833. # define RADEON_FCP0_SRC_PCLKb 2
  834. # define RADEON_FCP0_SRC_HREF 3
  835. # define RADEON_FCP0_SRC_GND 4
  836. # define RADEON_FCP0_SRC_HREFb 5
  837. #define RADEON_FLUSH_1 0x1704
  838. #define RADEON_FLUSH_2 0x1708
  839. #define RADEON_FLUSH_3 0x170c
  840. #define RADEON_FLUSH_4 0x1710
  841. #define RADEON_FLUSH_5 0x1714
  842. #define RADEON_FLUSH_6 0x1718
  843. #define RADEON_FLUSH_7 0x171c
  844. #define RADEON_FOG_3D_TABLE_START 0x1810
  845. #define RADEON_FOG_3D_TABLE_END 0x1814
  846. #define RADEON_FOG_3D_TABLE_DENSITY 0x181c
  847. #define RADEON_FOG_TABLE_INDEX 0x1a14
  848. #define RADEON_FOG_TABLE_DATA 0x1a18
  849. #define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250
  850. #define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254
  851. # define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff
  852. # define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000
  853. # define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff
  854. # define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000
  855. # define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
  856. # define RADEON_FP_H_SYNC_WID_MASK 0x003f0000
  857. # define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff
  858. # define RADEON_FP_V_SYNC_WID_MASK 0x001f0000
  859. # define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000
  860. # define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010
  861. # define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000
  862. # define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010
  863. # define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
  864. # define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010
  865. # define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000
  866. # define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010
  867. #define RADEON_FP_GEN_CNTL 0x0284
  868. # define RADEON_FP_FPON (1 << 0)
  869. # define RADEON_FP_BLANK_EN (1 << 1)
  870. # define RADEON_FP_TMDS_EN (1 << 2)
  871. # define RADEON_FP_PANEL_FORMAT (1 << 3)
  872. # define RADEON_FP_EN_TMDS (1 << 7)
  873. # define RADEON_FP_DETECT_SENSE (1 << 8)
  874. # define RADEON_FP_DETECT_INT_POL (1 << 9)
  875. # define R200_FP_SOURCE_SEL_MASK (3 << 10)
  876. # define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)
  877. # define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)
  878. # define R200_FP_SOURCE_SEL_RMX (2 << 10)
  879. # define R200_FP_SOURCE_SEL_TRANS (3 << 10)
  880. # define RADEON_FP_SEL_CRTC1 (0 << 13)
  881. # define RADEON_FP_SEL_CRTC2 (1 << 13)
  882. # define R300_HPD_SEL(x) ((x) << 13)
  883. # define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
  884. # define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
  885. # define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)
  886. # define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18)
  887. # define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
  888. # define RADEON_FP_DFP_SYNC_SEL (1 << 21)
  889. # define RADEON_FP_CRTC_LOCK_8DOT (1 << 22)
  890. # define RADEON_FP_CRT_SYNC_SEL (1 << 23)
  891. # define RADEON_FP_USE_SHADOW_EN (1 << 24)
  892. # define RADEON_FP_CRT_SYNC_ALT (1 << 26)
  893. #define RADEON_FP2_GEN_CNTL 0x0288
  894. # define RADEON_FP2_BLANK_EN (1 << 1)
  895. # define RADEON_FP2_ON (1 << 2)
  896. # define RADEON_FP2_PANEL_FORMAT (1 << 3)
  897. # define RADEON_FP2_DETECT_SENSE (1 << 8)
  898. # define RADEON_FP2_DETECT_INT_POL (1 << 9)
  899. # define R200_FP2_SOURCE_SEL_MASK (3 << 10)
  900. # define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10)
  901. # define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10)
  902. # define R200_FP2_SOURCE_SEL_RMX (2 << 10)
  903. # define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10)
  904. # define RADEON_FP2_SRC_SEL_MASK (3 << 13)
  905. # define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13)
  906. # define RADEON_FP2_FP_POL (1 << 16)
  907. # define RADEON_FP2_LP_POL (1 << 17)
  908. # define RADEON_FP2_SCK_POL (1 << 18)
  909. # define RADEON_FP2_LCD_CNTL_MASK (7 << 19)
  910. # define RADEON_FP2_PAD_FLOP_EN (1 << 22)
  911. # define RADEON_FP2_CRC_EN (1 << 23)
  912. # define RADEON_FP2_CRC_READ_EN (1 << 24)
  913. # define RADEON_FP2_DVO_EN (1 << 25)
  914. # define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26)
  915. # define R200_FP2_DVO_RATE_SEL_SDR (1 << 27)
  916. # define R300_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28)
  917. # define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29)
  918. #define RADEON_FP_H_SYNC_STRT_WID 0x02c4
  919. #define RADEON_FP_H2_SYNC_STRT_WID 0x03c4
  920. #define RADEON_FP_HORZ_STRETCH 0x028c
  921. #define RADEON_FP_HORZ2_STRETCH 0x038c
  922. # define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff
  923. # define RADEON_HORZ_STRETCH_RATIO_MAX 4096
  924. # define RADEON_HORZ_PANEL_SIZE (0x1ff << 16)
  925. # define RADEON_HORZ_PANEL_SHIFT 16
  926. # define RADEON_HORZ_STRETCH_PIXREP (0 << 25)
  927. # define RADEON_HORZ_STRETCH_BLEND (1 << 26)
  928. # define RADEON_HORZ_STRETCH_ENABLE (1 << 25)
  929. # define RADEON_HORZ_AUTO_RATIO (1 << 27)
  930. # define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28)
  931. # define RADEON_HORZ_AUTO_RATIO_INC (1 << 31)
  932. #define RADEON_FP_HORZ_VERT_ACTIVE 0x0278
  933. #define RADEON_FP_V_SYNC_STRT_WID 0x02c8
  934. #define RADEON_FP_VERT_STRETCH 0x0290
  935. #define RADEON_FP_V2_SYNC_STRT_WID 0x03c8
  936. #define RADEON_FP_VERT2_STRETCH 0x0390
  937. # define RADEON_VERT_PANEL_SIZE (0xfff << 12)
  938. # define RADEON_VERT_PANEL_SHIFT 12
  939. # define RADEON_VERT_STRETCH_RATIO_MASK 0xfff
  940. # define RADEON_VERT_STRETCH_RATIO_SHIFT 0
  941. # define RADEON_VERT_STRETCH_RATIO_MAX 4096
  942. # define RADEON_VERT_STRETCH_ENABLE (1 << 25)
  943. # define RADEON_VERT_STRETCH_LINEREP (0