/drivers/gpu/drm/radeon/radeon_reg.h
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- /*
- * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
- * VA Linux Systems Inc., Fremont, California.
- *
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation on the rights to use, copy, modify, merge,
- * publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial
- * portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
- * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
- * DEALINGS IN THE SOFTWARE.
- */
- /*
- * Authors:
- * Kevin E. Martin <martin@xfree86.org>
- * Rickard E. Faith <faith@valinux.com>
- * Alan Hourihane <alanh@fairlite.demon.co.uk>
- *
- * References:
- *
- * !!!! FIXME !!!!
- * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
- * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
- * 1999.
- *
- * !!!! FIXME !!!!
- * RAGE 128 Software Development Manual (Technical Reference Manual P/N
- * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
- *
- */
- /* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h
- * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT
- * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */
- #ifndef _RADEON_REG_H_
- #define _RADEON_REG_H_
- #include "r300_reg.h"
- #include "r500_reg.h"
- #include "r600_reg.h"
- #include "evergreen_reg.h"
- #define RADEON_MC_AGP_LOCATION 0x014c
- #define RADEON_MC_AGP_START_MASK 0x0000FFFF
- #define RADEON_MC_AGP_START_SHIFT 0
- #define RADEON_MC_AGP_TOP_MASK 0xFFFF0000
- #define RADEON_MC_AGP_TOP_SHIFT 16
- #define RADEON_MC_FB_LOCATION 0x0148
- #define RADEON_MC_FB_START_MASK 0x0000FFFF
- #define RADEON_MC_FB_START_SHIFT 0
- #define RADEON_MC_FB_TOP_MASK 0xFFFF0000
- #define RADEON_MC_FB_TOP_SHIFT 16
- #define RADEON_AGP_BASE_2 0x015c /* r200+ only */
- #define RADEON_AGP_BASE 0x0170
- #define ATI_DATATYPE_VQ 0
- #define ATI_DATATYPE_CI4 1
- #define ATI_DATATYPE_CI8 2
- #define ATI_DATATYPE_ARGB1555 3
- #define ATI_DATATYPE_RGB565 4
- #define ATI_DATATYPE_RGB888 5
- #define ATI_DATATYPE_ARGB8888 6
- #define ATI_DATATYPE_RGB332 7
- #define ATI_DATATYPE_Y8 8
- #define ATI_DATATYPE_RGB8 9
- #define ATI_DATATYPE_CI16 10
- #define ATI_DATATYPE_VYUY_422 11
- #define ATI_DATATYPE_YVYU_422 12
- #define ATI_DATATYPE_AYUV_444 14
- #define ATI_DATATYPE_ARGB4444 15
- /* Registers for 2D/Video/Overlay */
- #define RADEON_ADAPTER_ID 0x0f2c /* PCI */
- #define RADEON_AGP_BASE 0x0170
- #define RADEON_AGP_CNTL 0x0174
- # define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)
- # define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)
- # define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)
- # define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)
- # define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)
- # define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)
- # define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)
- # define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)
- #define RADEON_STATUS_PCI_CONFIG 0x06
- # define RADEON_CAP_LIST 0x100000
- #define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/
- # define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */
- # define RADEON_CAP_ID_NULL 0x00 /* End of capability list */
- # define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */
- # define RADEON_CAP_ID_EXP 0x10 /* PCI Express */
- #define RADEON_AGP_COMMAND 0x0f60 /* PCI */
- #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/
- # define RADEON_AGP_ENABLE (1<<8)
- #define RADEON_AGP_PLL_CNTL 0x000b /* PLL */
- #define RADEON_AGP_STATUS 0x0f5c /* PCI */
- # define RADEON_AGP_1X_MODE 0x01
- # define RADEON_AGP_2X_MODE 0x02
- # define RADEON_AGP_4X_MODE 0x04
- # define RADEON_AGP_FW_MODE 0x10
- # define RADEON_AGP_MODE_MASK 0x17
- # define RADEON_AGPv3_MODE 0x08
- # define RADEON_AGPv3_4X_MODE 0x01
- # define RADEON_AGPv3_8X_MODE 0x02
- #define RADEON_ATTRDR 0x03c1 /* VGA */
- #define RADEON_ATTRDW 0x03c0 /* VGA */
- #define RADEON_ATTRX 0x03c0 /* VGA */
- #define RADEON_AUX_SC_CNTL 0x1660
- # define RADEON_AUX1_SC_EN (1 << 0)
- # define RADEON_AUX1_SC_MODE_OR (0 << 1)
- # define RADEON_AUX1_SC_MODE_NAND (1 << 1)
- # define RADEON_AUX2_SC_EN (1 << 2)
- # define RADEON_AUX2_SC_MODE_OR (0 << 3)
- # define RADEON_AUX2_SC_MODE_NAND (1 << 3)
- # define RADEON_AUX3_SC_EN (1 << 4)
- # define RADEON_AUX3_SC_MODE_OR (0 << 5)
- # define RADEON_AUX3_SC_MODE_NAND (1 << 5)
- #define RADEON_AUX1_SC_BOTTOM 0x1670
- #define RADEON_AUX1_SC_LEFT 0x1664
- #define RADEON_AUX1_SC_RIGHT 0x1668
- #define RADEON_AUX1_SC_TOP 0x166c
- #define RADEON_AUX2_SC_BOTTOM 0x1680
- #define RADEON_AUX2_SC_LEFT 0x1674
- #define RADEON_AUX2_SC_RIGHT 0x1678
- #define RADEON_AUX2_SC_TOP 0x167c
- #define RADEON_AUX3_SC_BOTTOM 0x1690
- #define RADEON_AUX3_SC_LEFT 0x1684
- #define RADEON_AUX3_SC_RIGHT 0x1688
- #define RADEON_AUX3_SC_TOP 0x168c
- #define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8
- #define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc
- #define RADEON_BASE_CODE 0x0f0b
- #define RADEON_BIOS_0_SCRATCH 0x0010
- # define RADEON_FP_PANEL_SCALABLE (1 << 16)
- # define RADEON_FP_PANEL_SCALE_EN (1 << 17)
- # define RADEON_FP_CHIP_SCALE_EN (1 << 18)
- # define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26)
- # define RADEON_DISPLAY_ROT_MASK (3 << 28)
- # define RADEON_DISPLAY_ROT_00 (0 << 28)
- # define RADEON_DISPLAY_ROT_90 (1 << 28)
- # define RADEON_DISPLAY_ROT_180 (2 << 28)
- # define RADEON_DISPLAY_ROT_270 (3 << 28)
- #define RADEON_BIOS_1_SCRATCH 0x0014
- #define RADEON_BIOS_2_SCRATCH 0x0018
- #define RADEON_BIOS_3_SCRATCH 0x001c
- #define RADEON_BIOS_4_SCRATCH 0x0020
- # define RADEON_CRT1_ATTACHED_MASK (3 << 0)
- # define RADEON_CRT1_ATTACHED_MONO (1 << 0)
- # define RADEON_CRT1_ATTACHED_COLOR (2 << 0)
- # define RADEON_LCD1_ATTACHED (1 << 2)
- # define RADEON_DFP1_ATTACHED (1 << 3)
- # define RADEON_TV1_ATTACHED_MASK (3 << 4)
- # define RADEON_TV1_ATTACHED_COMP (1 << 4)
- # define RADEON_TV1_ATTACHED_SVIDEO (2 << 4)
- # define RADEON_CRT2_ATTACHED_MASK (3 << 8)
- # define RADEON_CRT2_ATTACHED_MONO (1 << 8)
- # define RADEON_CRT2_ATTACHED_COLOR (2 << 8)
- # define RADEON_DFP2_ATTACHED (1 << 11)
- #define RADEON_BIOS_5_SCRATCH 0x0024
- # define RADEON_LCD1_ON (1 << 0)
- # define RADEON_CRT1_ON (1 << 1)
- # define RADEON_TV1_ON (1 << 2)
- # define RADEON_DFP1_ON (1 << 3)
- # define RADEON_CRT2_ON (1 << 5)
- # define RADEON_CV1_ON (1 << 6)
- # define RADEON_DFP2_ON (1 << 7)
- # define RADEON_LCD1_CRTC_MASK (1 << 8)
- # define RADEON_LCD1_CRTC_SHIFT 8
- # define RADEON_CRT1_CRTC_MASK (1 << 9)
- # define RADEON_CRT1_CRTC_SHIFT 9
- # define RADEON_TV1_CRTC_MASK (1 << 10)
- # define RADEON_TV1_CRTC_SHIFT 10
- # define RADEON_DFP1_CRTC_MASK (1 << 11)
- # define RADEON_DFP1_CRTC_SHIFT 11
- # define RADEON_CRT2_CRTC_MASK (1 << 12)
- # define RADEON_CRT2_CRTC_SHIFT 12
- # define RADEON_CV1_CRTC_MASK (1 << 13)
- # define RADEON_CV1_CRTC_SHIFT 13
- # define RADEON_DFP2_CRTC_MASK (1 << 14)
- # define RADEON_DFP2_CRTC_SHIFT 14
- # define RADEON_ACC_REQ_LCD1 (1 << 16)
- # define RADEON_ACC_REQ_CRT1 (1 << 17)
- # define RADEON_ACC_REQ_TV1 (1 << 18)
- # define RADEON_ACC_REQ_DFP1 (1 << 19)
- # define RADEON_ACC_REQ_CRT2 (1 << 21)
- # define RADEON_ACC_REQ_TV2 (1 << 22)
- # define RADEON_ACC_REQ_DFP2 (1 << 23)
- #define RADEON_BIOS_6_SCRATCH 0x0028
- # define RADEON_ACC_MODE_CHANGE (1 << 2)
- # define RADEON_EXT_DESKTOP_MODE (1 << 3)
- # define RADEON_LCD_DPMS_ON (1 << 20)
- # define RADEON_CRT_DPMS_ON (1 << 21)
- # define RADEON_TV_DPMS_ON (1 << 22)
- # define RADEON_DFP_DPMS_ON (1 << 23)
- # define RADEON_DPMS_MASK (3 << 24)
- # define RADEON_DPMS_ON (0 << 24)
- # define RADEON_DPMS_STANDBY (1 << 24)
- # define RADEON_DPMS_SUSPEND (2 << 24)
- # define RADEON_DPMS_OFF (3 << 24)
- # define RADEON_SCREEN_BLANKING (1 << 26)
- # define RADEON_DRIVER_CRITICAL (1 << 27)
- # define RADEON_DISPLAY_SWITCHING_DIS (1 << 30)
- #define RADEON_BIOS_7_SCRATCH 0x002c
- # define RADEON_SYS_HOTKEY (1 << 10)
- # define RADEON_DRV_LOADED (1 << 12)
- #define RADEON_BIOS_ROM 0x0f30 /* PCI */
- #define RADEON_BIST 0x0f0f /* PCI */
- #define RADEON_BRUSH_DATA0 0x1480
- #define RADEON_BRUSH_DATA1 0x1484
- #define RADEON_BRUSH_DATA10 0x14a8
- #define RADEON_BRUSH_DATA11 0x14ac
- #define RADEON_BRUSH_DATA12 0x14b0
- #define RADEON_BRUSH_DATA13 0x14b4
- #define RADEON_BRUSH_DATA14 0x14b8
- #define RADEON_BRUSH_DATA15 0x14bc
- #define RADEON_BRUSH_DATA16 0x14c0
- #define RADEON_BRUSH_DATA17 0x14c4
- #define RADEON_BRUSH_DATA18 0x14c8
- #define RADEON_BRUSH_DATA19 0x14cc
- #define RADEON_BRUSH_DATA2 0x1488
- #define RADEON_BRUSH_DATA20 0x14d0
- #define RADEON_BRUSH_DATA21 0x14d4
- #define RADEON_BRUSH_DATA22 0x14d8
- #define RADEON_BRUSH_DATA23 0x14dc
- #define RADEON_BRUSH_DATA24 0x14e0
- #define RADEON_BRUSH_DATA25 0x14e4
- #define RADEON_BRUSH_DATA26 0x14e8
- #define RADEON_BRUSH_DATA27 0x14ec
- #define RADEON_BRUSH_DATA28 0x14f0
- #define RADEON_BRUSH_DATA29 0x14f4
- #define RADEON_BRUSH_DATA3 0x148c
- #define RADEON_BRUSH_DATA30 0x14f8
- #define RADEON_BRUSH_DATA31 0x14fc
- #define RADEON_BRUSH_DATA32 0x1500
- #define RADEON_BRUSH_DATA33 0x1504
- #define RADEON_BRUSH_DATA34 0x1508
- #define RADEON_BRUSH_DATA35 0x150c
- #define RADEON_BRUSH_DATA36 0x1510
- #define RADEON_BRUSH_DATA37 0x1514
- #define RADEON_BRUSH_DATA38 0x1518
- #define RADEON_BRUSH_DATA39 0x151c
- #define RADEON_BRUSH_DATA4 0x1490
- #define RADEON_BRUSH_DATA40 0x1520
- #define RADEON_BRUSH_DATA41 0x1524
- #define RADEON_BRUSH_DATA42 0x1528
- #define RADEON_BRUSH_DATA43 0x152c
- #define RADEON_BRUSH_DATA44 0x1530
- #define RADEON_BRUSH_DATA45 0x1534
- #define RADEON_BRUSH_DATA46 0x1538
- #define RADEON_BRUSH_DATA47 0x153c
- #define RADEON_BRUSH_DATA48 0x1540
- #define RADEON_BRUSH_DATA49 0x1544
- #define RADEON_BRUSH_DATA5 0x1494
- #define RADEON_BRUSH_DATA50 0x1548
- #define RADEON_BRUSH_DATA51 0x154c
- #define RADEON_BRUSH_DATA52 0x1550
- #define RADEON_BRUSH_DATA53 0x1554
- #define RADEON_BRUSH_DATA54 0x1558
- #define RADEON_BRUSH_DATA55 0x155c
- #define RADEON_BRUSH_DATA56 0x1560
- #define RADEON_BRUSH_DATA57 0x1564
- #define RADEON_BRUSH_DATA58 0x1568
- #define RADEON_BRUSH_DATA59 0x156c
- #define RADEON_BRUSH_DATA6 0x1498
- #define RADEON_BRUSH_DATA60 0x1570
- #define RADEON_BRUSH_DATA61 0x1574
- #define RADEON_BRUSH_DATA62 0x1578
- #define RADEON_BRUSH_DATA63 0x157c
- #define RADEON_BRUSH_DATA7 0x149c
- #define RADEON_BRUSH_DATA8 0x14a0
- #define RADEON_BRUSH_DATA9 0x14a4
- #define RADEON_BRUSH_SCALE 0x1470
- #define RADEON_BRUSH_Y_X 0x1474
- #define RADEON_BUS_CNTL 0x0030
- # define RADEON_BUS_MASTER_DIS (1 << 6)
- # define RADEON_BUS_BIOS_DIS_ROM (1 << 12)
- # define RS600_BUS_MASTER_DIS (1 << 14)
- # define RS600_MSI_REARM (1 << 20) /* rs600/rs690/rs740 */
- # define RADEON_BUS_RD_DISCARD_EN (1 << 24)
- # define RADEON_BUS_RD_ABORT_EN (1 << 25)
- # define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)
- # define RADEON_BUS_WRT_BURST (1 << 29)
- # define RADEON_BUS_READ_BURST (1 << 30)
- #define RADEON_BUS_CNTL1 0x0034
- # define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)
- /* rv370/rv380, rv410, r423/r430/r480, r5xx */
- #define RADEON_MSI_REARM_EN 0x0160
- # define RV370_MSI_REARM_EN (1 << 0)
- /* #define RADEON_PCIE_INDEX 0x0030 */
- /* #define RADEON_PCIE_DATA 0x0034 */
- #define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */
- # define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0
- # define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7
- # define RADEON_PCIE_LC_LINK_WIDTH_X0 0
- # define RADEON_PCIE_LC_LINK_WIDTH_X1 1
- # define RADEON_PCIE_LC_LINK_WIDTH_X2 2
- # define RADEON_PCIE_LC_LINK_WIDTH_X4 3
- # define RADEON_PCIE_LC_LINK_WIDTH_X8 4
- # define RADEON_PCIE_LC_LINK_WIDTH_X12 5
- # define RADEON_PCIE_LC_LINK_WIDTH_X16 6
- # define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4
- # define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70
- # define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8)
- # define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9)
- # define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10)
- #define RADEON_CACHE_CNTL 0x1724
- #define RADEON_CACHE_LINE 0x0f0c /* PCI */
- #define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */
- #define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */
- #define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */
- # define RADEON_DONT_USE_XTALIN (1 << 4)
- # define RADEON_SCLK_DYN_START_CNTL (1 << 15)
- #define RADEON_CLOCK_CNTL_DATA 0x000c
- #define RADEON_CLOCK_CNTL_INDEX 0x0008
- # define RADEON_PLL_WR_EN (1 << 7)
- # define RADEON_PLL_DIV_SEL (3 << 8)
- # define RADEON_PLL2_DIV_SEL_MASK (~(3 << 8))
- #define RADEON_CLK_PWRMGT_CNTL 0x0014
- # define RADEON_ENGIN_DYNCLK_MODE (1 << 12)
- # define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13)
- # define RADEON_ACTIVE_HILO_LAT_SHIFT 13
- # define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12)
- # define RADEON_MC_BUSY (1 << 16)
- # define RADEON_DLL_READY (1 << 19)
- # define RADEON_CG_NO1_DEBUG_0 (1 << 24)
- # define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24)
- # define RADEON_DYN_STOP_MODE_MASK (7 << 21)
- # define RADEON_TVPLL_PWRMGT_OFF (1 << 30)
- # define RADEON_TVCLK_TURNOFF (1 << 31)
- #define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */
- # define RADEON_PM_MODE_SEL (1 << 13)
- # define RADEON_TCL_BYPASS_DISABLE (1 << 20)
- #define RADEON_CLR_CMP_CLR_3D 0x1a24
- #define RADEON_CLR_CMP_CLR_DST 0x15c8
- #define RADEON_CLR_CMP_CLR_SRC 0x15c4
- #define RADEON_CLR_CMP_CNTL 0x15c0
- # define RADEON_SRC_CMP_EQ_COLOR (4 << 0)
- # define RADEON_SRC_CMP_NEQ_COLOR (5 << 0)
- # define RADEON_CLR_CMP_SRC_SOURCE (1 << 24)
- #define RADEON_CLR_CMP_MASK 0x15cc
- # define RADEON_CLR_CMP_MSK 0xffffffff
- #define RADEON_CLR_CMP_MASK_3D 0x1A28
- #define RADEON_COMMAND 0x0f04 /* PCI */
- #define RADEON_COMPOSITE_SHADOW_ID 0x1a0c
- #define RADEON_CONFIG_APER_0_BASE 0x0100
- #define RADEON_CONFIG_APER_1_BASE 0x0104
- #define RADEON_CONFIG_APER_SIZE 0x0108
- #define RADEON_CONFIG_BONDS 0x00e8
- #define RADEON_CONFIG_CNTL 0x00e0
- # define RADEON_CFG_ATI_REV_A11 (0 << 16)
- # define RADEON_CFG_ATI_REV_A12 (1 << 16)
- # define RADEON_CFG_ATI_REV_A13 (2 << 16)
- # define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16)
- #define RADEON_CONFIG_MEMSIZE 0x00f8
- #define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114
- #define RADEON_CONFIG_REG_1_BASE 0x010c
- #define RADEON_CONFIG_REG_APER_SIZE 0x0110
- #define RADEON_CONFIG_XSTRAP 0x00e4
- #define RADEON_CONSTANT_COLOR_C 0x1d34
- # define RADEON_CONSTANT_COLOR_MASK 0x00ffffff
- # define RADEON_CONSTANT_COLOR_ONE 0x00ffffff
- # define RADEON_CONSTANT_COLOR_ZERO 0x00000000
- #define RADEON_CRC_CMDFIFO_ADDR 0x0740
- #define RADEON_CRC_CMDFIFO_DOUT 0x0744
- #define RADEON_GRPH_BUFFER_CNTL 0x02f0
- # define RADEON_GRPH_START_REQ_MASK (0x7f)
- # define RADEON_GRPH_START_REQ_SHIFT 0
- # define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)
- # define RADEON_GRPH_STOP_REQ_SHIFT 8
- # define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)
- # define RADEON_GRPH_CRITICAL_POINT_SHIFT 16
- # define RADEON_GRPH_CRITICAL_CNTL (1<<28)
- # define RADEON_GRPH_BUFFER_SIZE (1<<29)
- # define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)
- # define RADEON_GRPH_STOP_CNTL (1<<31)
- #define RADEON_GRPH2_BUFFER_CNTL 0x03f0
- # define RADEON_GRPH2_START_REQ_MASK (0x7f)
- # define RADEON_GRPH2_START_REQ_SHIFT 0
- # define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)
- # define RADEON_GRPH2_STOP_REQ_SHIFT 8
- # define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)
- # define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16
- # define RADEON_GRPH2_CRITICAL_CNTL (1<<28)
- # define RADEON_GRPH2_BUFFER_SIZE (1<<29)
- # define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)
- # define RADEON_GRPH2_STOP_CNTL (1<<31)
- #define RADEON_CRTC_CRNT_FRAME 0x0214
- #define RADEON_CRTC_EXT_CNTL 0x0054
- # define RADEON_CRTC_VGA_XOVERSCAN (1 << 0)
- # define RADEON_VGA_ATI_LINEAR (1 << 3)
- # define RADEON_XCRT_CNT_EN (1 << 6)
- # define RADEON_CRTC_HSYNC_DIS (1 << 8)
- # define RADEON_CRTC_VSYNC_DIS (1 << 9)
- # define RADEON_CRTC_DISPLAY_DIS (1 << 10)
- # define RADEON_CRTC_SYNC_TRISTAT (1 << 11)
- # define RADEON_CRTC_CRT_ON (1 << 15)
- #define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055
- # define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0)
- # define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1)
- # define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2)
- #define RADEON_CRTC_GEN_CNTL 0x0050
- # define RADEON_CRTC_DBL_SCAN_EN (1 << 0)
- # define RADEON_CRTC_INTERLACE_EN (1 << 1)
- # define RADEON_CRTC_CSYNC_EN (1 << 4)
- # define RADEON_CRTC_ICON_EN (1 << 15)
- # define RADEON_CRTC_CUR_EN (1 << 16)
- # define RADEON_CRTC_CUR_MODE_MASK (7 << 20)
- # define RADEON_CRTC_CUR_MODE_SHIFT 20
- # define RADEON_CRTC_CUR_MODE_MONO 0
- # define RADEON_CRTC_CUR_MODE_24BPP 2
- # define RADEON_CRTC_EXT_DISP_EN (1 << 24)
- # define RADEON_CRTC_EN (1 << 25)
- # define RADEON_CRTC_DISP_REQ_EN_B (1 << 26)
- #define RADEON_CRTC2_GEN_CNTL 0x03f8
- # define RADEON_CRTC2_DBL_SCAN_EN (1 << 0)
- # define RADEON_CRTC2_INTERLACE_EN (1 << 1)
- # define RADEON_CRTC2_SYNC_TRISTAT (1 << 4)
- # define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5)
- # define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6)
- # define RADEON_CRTC2_CRT2_ON (1 << 7)
- # define RADEON_CRTC2_PIX_WIDTH_SHIFT 8
- # define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8)
- # define RADEON_CRTC2_ICON_EN (1 << 15)
- # define RADEON_CRTC2_CUR_EN (1 << 16)
- # define RADEON_CRTC2_CUR_MODE_MASK (7 << 20)
- # define RADEON_CRTC2_DISP_DIS (1 << 23)
- # define RADEON_CRTC2_EN (1 << 25)
- # define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26)
- # define RADEON_CRTC2_CSYNC_EN (1 << 27)
- # define RADEON_CRTC2_HSYNC_DIS (1 << 28)
- # define RADEON_CRTC2_VSYNC_DIS (1 << 29)
- #define RADEON_CRTC_MORE_CNTL 0x27c
- # define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2)
- # define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3)
- # define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
- # define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
- #define RADEON_CRTC_GUI_TRIG_VLINE 0x0218
- #define RADEON_CRTC_H_SYNC_STRT_WID 0x0204
- # define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0)
- # define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)
- # define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3
- # define RADEON_CRTC_H_SYNC_WID (0x3f << 16)
- # define RADEON_CRTC_H_SYNC_WID_SHIFT 16
- # define RADEON_CRTC_H_SYNC_POL (1 << 23)
- #define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304
- # define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0)
- # define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)
- # define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3
- # define RADEON_CRTC2_H_SYNC_WID (0x3f << 16)
- # define RADEON_CRTC2_H_SYNC_WID_SHIFT 16
- # define RADEON_CRTC2_H_SYNC_POL (1 << 23)
- #define RADEON_CRTC_H_TOTAL_DISP 0x0200
- # define RADEON_CRTC_H_TOTAL (0x03ff << 0)
- # define RADEON_CRTC_H_TOTAL_SHIFT 0
- # define RADEON_CRTC_H_DISP (0x01ff << 16)
- # define RADEON_CRTC_H_DISP_SHIFT 16
- #define RADEON_CRTC2_H_TOTAL_DISP 0x0300
- # define RADEON_CRTC2_H_TOTAL (0x03ff << 0)
- # define RADEON_CRTC2_H_TOTAL_SHIFT 0
- # define RADEON_CRTC2_H_DISP (0x01ff << 16)
- # define RADEON_CRTC2_H_DISP_SHIFT 16
- #define RADEON_CRTC_OFFSET_RIGHT 0x0220
- #define RADEON_CRTC_OFFSET 0x0224
- # define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30)
- # define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31)
- #define RADEON_CRTC2_OFFSET 0x0324
- # define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30)
- # define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31)
- #define RADEON_CRTC_OFFSET_CNTL 0x0228
- # define RADEON_CRTC_TILE_LINE_SHIFT 0
- # define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4
- # define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6)
- # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7)
- # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7)
- # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7)
- # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7)
- # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7)
- # define R300_CRTC_X_Y_MODE_EN (1 << 9)
- # define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10)
- # define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10)
- # define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10)
- # define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10)
- # define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10)
- # define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12)
- # define R300_CRTC_MICRO_TILE_EN (1 << 13)
- # define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14)
- # define R300_CRTC_MACRO_TILE_EN (1 << 15)
- # define RADEON_CRTC_TILE_EN_RIGHT (1 << 14)
- # define RADEON_CRTC_TILE_EN (1 << 15)
- # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
- # define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17)
- #define R300_CRTC_TILE_X0_Y0 0x0350
- #define R300_CRTC2_TILE_X0_Y0 0x0358
- #define RADEON_CRTC2_OFFSET_CNTL 0x0328
- # define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16)
- # define RADEON_CRTC2_TILE_EN (1 << 15)
- #define RADEON_CRTC_PITCH 0x022c
- # define RADEON_CRTC_PITCH__SHIFT 0
- # define RADEON_CRTC_PITCH__RIGHT_SHIFT 16
- #define RADEON_CRTC2_PITCH 0x032c
- #define RADEON_CRTC_STATUS 0x005c
- # define RADEON_CRTC_VBLANK_SAVE (1 << 1)
- # define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1)
- #define RADEON_CRTC2_STATUS 0x03fc
- # define RADEON_CRTC2_VBLANK_SAVE (1 << 1)
- # define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1)
- #define RADEON_CRTC_V_SYNC_STRT_WID 0x020c
- # define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0)
- # define RADEON_CRTC_V_SYNC_STRT_SHIFT 0
- # define RADEON_CRTC_V_SYNC_WID (0x1f << 16)
- # define RADEON_CRTC_V_SYNC_WID_SHIFT 16
- # define RADEON_CRTC_V_SYNC_POL (1 << 23)
- #define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c
- # define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0)
- # define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0
- # define RADEON_CRTC2_V_SYNC_WID (0x1f << 16)
- # define RADEON_CRTC2_V_SYNC_WID_SHIFT 16
- # define RADEON_CRTC2_V_SYNC_POL (1 << 23)
- #define RADEON_CRTC_V_TOTAL_DISP 0x0208
- # define RADEON_CRTC_V_TOTAL (0x07ff << 0)
- # define RADEON_CRTC_V_TOTAL_SHIFT 0
- # define RADEON_CRTC_V_DISP (0x07ff << 16)
- # define RADEON_CRTC_V_DISP_SHIFT 16
- #define RADEON_CRTC2_V_TOTAL_DISP 0x0308
- # define RADEON_CRTC2_V_TOTAL (0x07ff << 0)
- # define RADEON_CRTC2_V_TOTAL_SHIFT 0
- # define RADEON_CRTC2_V_DISP (0x07ff << 16)
- # define RADEON_CRTC2_V_DISP_SHIFT 16
- #define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210
- # define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16)
- #define RADEON_CRTC2_CRNT_FRAME 0x0314
- #define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318
- #define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310
- #define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */
- #define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */
- #define RADEON_CUR_CLR0 0x026c
- #define RADEON_CUR_CLR1 0x0270
- #define RADEON_CUR_HORZ_VERT_OFF 0x0268
- #define RADEON_CUR_HORZ_VERT_POSN 0x0264
- #define RADEON_CUR_OFFSET 0x0260
- # define RADEON_CUR_LOCK (1 << 31)
- #define RADEON_CUR2_CLR0 0x036c
- #define RADEON_CUR2_CLR1 0x0370
- #define RADEON_CUR2_HORZ_VERT_OFF 0x0368
- #define RADEON_CUR2_HORZ_VERT_POSN 0x0364
- #define RADEON_CUR2_OFFSET 0x0360
- # define RADEON_CUR2_LOCK (1 << 31)
- #define RADEON_DAC_CNTL 0x0058
- # define RADEON_DAC_RANGE_CNTL (3 << 0)
- # define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0)
- # define RADEON_DAC_RANGE_CNTL_MASK 0x03
- # define RADEON_DAC_BLANKING (1 << 2)
- # define RADEON_DAC_CMP_EN (1 << 3)
- # define RADEON_DAC_CMP_OUTPUT (1 << 7)
- # define RADEON_DAC_8BIT_EN (1 << 8)
- # define RADEON_DAC_TVO_EN (1 << 10)
- # define RADEON_DAC_VGA_ADR_EN (1 << 13)
- # define RADEON_DAC_PDWN (1 << 15)
- # define RADEON_DAC_MASK_ALL (0xff << 24)
- #define RADEON_DAC_CNTL2 0x007c
- # define RADEON_DAC2_TV_CLK_SEL (0 << 1)
- # define RADEON_DAC2_DAC_CLK_SEL (1 << 0)
- # define RADEON_DAC2_DAC2_CLK_SEL (1 << 1)
- # define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5)
- # define RADEON_DAC2_CMP_EN (1 << 7)
- # define RADEON_DAC2_CMP_OUT_R (1 << 8)
- # define RADEON_DAC2_CMP_OUT_G (1 << 9)
- # define RADEON_DAC2_CMP_OUT_B (1 << 10)
- # define RADEON_DAC2_CMP_OUTPUT (1 << 11)
- #define RADEON_DAC_EXT_CNTL 0x0280
- # define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0)
- # define RADEON_DAC2_FORCE_DATA_EN (1 << 1)
- # define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)
- # define RADEON_DAC_FORCE_DATA_EN (1 << 5)
- # define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)
- # define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6)
- # define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6)
- # define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6)
- # define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6)
- # define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00
- # define RADEON_DAC_FORCE_DATA_SHIFT 8
- #define RADEON_DAC_MACRO_CNTL 0x0d04
- # define RADEON_DAC_PDWN_R (1 << 16)
- # define RADEON_DAC_PDWN_G (1 << 17)
- # define RADEON_DAC_PDWN_B (1 << 18)
- #define RADEON_DISP_PWR_MAN 0x0d08
- # define RADEON_DISP_PWR_MAN_D3_CRTC_EN (1 << 0)
- # define RADEON_DISP_PWR_MAN_D3_CRTC2_EN (1 << 4)
- # define RADEON_DISP_PWR_MAN_DPMS_ON (0 << 8)
- # define RADEON_DISP_PWR_MAN_DPMS_STANDBY (1 << 8)
- # define RADEON_DISP_PWR_MAN_DPMS_SUSPEND (2 << 8)
- # define RADEON_DISP_PWR_MAN_DPMS_OFF (3 << 8)
- # define RADEON_DISP_D3_RST (1 << 16)
- # define RADEON_DISP_D3_REG_RST (1 << 17)
- # define RADEON_DISP_D3_GRPH_RST (1 << 18)
- # define RADEON_DISP_D3_SUBPIC_RST (1 << 19)
- # define RADEON_DISP_D3_OV0_RST (1 << 20)
- # define RADEON_DISP_D1D2_GRPH_RST (1 << 21)
- # define RADEON_DISP_D1D2_SUBPIC_RST (1 << 22)
- # define RADEON_DISP_D1D2_OV0_RST (1 << 23)
- # define RADEON_DIG_TMDS_ENABLE_RST (1 << 24)
- # define RADEON_TV_ENABLE_RST (1 << 25)
- # define RADEON_AUTO_PWRUP_EN (1 << 26)
- #define RADEON_TV_DAC_CNTL 0x088c
- # define RADEON_TV_DAC_NBLANK (1 << 0)
- # define RADEON_TV_DAC_NHOLD (1 << 1)
- # define RADEON_TV_DAC_PEDESTAL (1 << 2)
- # define RADEON_TV_MONITOR_DETECT_EN (1 << 4)
- # define RADEON_TV_DAC_CMPOUT (1 << 5)
- # define RADEON_TV_DAC_STD_MASK (3 << 8)
- # define RADEON_TV_DAC_STD_PAL (0 << 8)
- # define RADEON_TV_DAC_STD_NTSC (1 << 8)
- # define RADEON_TV_DAC_STD_PS2 (2 << 8)
- # define RADEON_TV_DAC_STD_RS343 (3 << 8)
- # define RADEON_TV_DAC_BGSLEEP (1 << 6)
- # define RADEON_TV_DAC_BGADJ_MASK (0xf << 16)
- # define RADEON_TV_DAC_BGADJ_SHIFT 16
- # define RADEON_TV_DAC_DACADJ_MASK (0xf << 20)
- # define RADEON_TV_DAC_DACADJ_SHIFT 20
- # define RADEON_TV_DAC_RDACPD (1 << 24)
- # define RADEON_TV_DAC_GDACPD (1 << 25)
- # define RADEON_TV_DAC_BDACPD (1 << 26)
- # define RADEON_TV_DAC_RDACDET (1 << 29)
- # define RADEON_TV_DAC_GDACDET (1 << 30)
- # define RADEON_TV_DAC_BDACDET (1 << 31)
- # define R420_TV_DAC_DACADJ_MASK (0x1f << 20)
- # define R420_TV_DAC_RDACPD (1 << 25)
- # define R420_TV_DAC_GDACPD (1 << 26)
- # define R420_TV_DAC_BDACPD (1 << 27)
- # define R420_TV_DAC_TVENABLE (1 << 28)
- #define RADEON_DISP_HW_DEBUG 0x0d14
- # define RADEON_CRT2_DISP1_SEL (1 << 5)
- #define RADEON_DISP_OUTPUT_CNTL 0x0d64
- # define RADEON_DISP_DAC_SOURCE_MASK 0x03
- # define RADEON_DISP_DAC2_SOURCE_MASK 0x0c
- # define RADEON_DISP_DAC_SOURCE_CRTC2 0x01
- # define RADEON_DISP_DAC_SOURCE_RMX 0x02
- # define RADEON_DISP_DAC_SOURCE_LTU 0x03
- # define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04
- # define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2)
- # define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0
- # define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2)
- # define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2)
- # define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2)
- # define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4)
- # define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4)
- # define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4)
- # define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4)
- # define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */
- # define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */
- #define RADEON_DISP_TV_OUT_CNTL 0x0d6c
- # define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16)
- # define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16)
- #define RADEON_DAC_CRC_SIG 0x02cc
- #define RADEON_DAC_DATA 0x03c9 /* VGA */
- #define RADEON_DAC_MASK 0x03c6 /* VGA */
- #define RADEON_DAC_R_INDEX 0x03c7 /* VGA */
- #define RADEON_DAC_W_INDEX 0x03c8 /* VGA */
- #define RADEON_DDA_CONFIG 0x02e0
- #define RADEON_DDA_ON_OFF 0x02e4
- #define RADEON_DEFAULT_OFFSET 0x16e0
- #define RADEON_DEFAULT_PITCH 0x16e4
- #define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8
- # define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
- # define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
- #define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820
- #define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824
- #define RADEON_DEVICE_ID 0x0f02 /* PCI */
- #define RADEON_DISP_MISC_CNTL 0x0d00
- # define RADEON_SOFT_RESET_GRPH_PP (1 << 0)
- #define RADEON_DISP_MERGE_CNTL 0x0d60
- # define RADEON_DISP_ALPHA_MODE_MASK 0x03
- # define RADEON_DISP_ALPHA_MODE_KEY 0
- # define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1
- # define RADEON_DISP_ALPHA_MODE_GLOBAL 2
- # define RADEON_DISP_RGB_OFFSET_EN (1 << 8)
- # define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16)
- # define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24)
- # define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)
- #define RADEON_DISP2_MERGE_CNTL 0x0d68
- # define RADEON_DISP2_RGB_OFFSET_EN (1 << 8)
- #define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80
- #define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84
- #define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88
- #define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c
- #define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90
- #define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98
- #define RADEON_DP_BRUSH_BKGD_CLR 0x1478
- #define RADEON_DP_BRUSH_FRGD_CLR 0x147c
- #define RADEON_DP_CNTL 0x16c0
- # define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0)
- # define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1)
- # define RADEON_DP_DST_TILE_LINEAR (0 << 3)
- # define RADEON_DP_DST_TILE_MACRO (1 << 3)
- # define RADEON_DP_DST_TILE_MICRO (2 << 3)
- # define RADEON_DP_DST_TILE_BOTH (3 << 3)
- #define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
- # define RADEON_DST_Y_MAJOR (1 << 2)
- # define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)
- # define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)
- #define RADEON_DP_DATATYPE 0x16c4
- # define RADEON_HOST_BIG_ENDIAN_EN (1 << 29)
- #define RADEON_DP_GUI_MASTER_CNTL 0x146c
- # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
- # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
- # define RADEON_GMC_SRC_CLIPPING (1 << 2)
- # define RADEON_GMC_DST_CLIPPING (1 << 3)
- # define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4)
- # define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4)
- # define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4)
- # define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4)
- # define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4)
- # define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4)
- # define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4)
- # define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4)
- # define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4)
- # define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4)
- # define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4)
- # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
- # define RADEON_GMC_BRUSH_NONE (15 << 4)
- # define RADEON_GMC_DST_8BPP_CI (2 << 8)
- # define RADEON_GMC_DST_15BPP (3 << 8)
- # define RADEON_GMC_DST_16BPP (4 << 8)
- # define RADEON_GMC_DST_24BPP (5 << 8)
- # define RADEON_GMC_DST_32BPP (6 << 8)
- # define RADEON_GMC_DST_8BPP_RGB (7 << 8)
- # define RADEON_GMC_DST_Y8 (8 << 8)
- # define RADEON_GMC_DST_RGB8 (9 << 8)
- # define RADEON_GMC_DST_VYUY (11 << 8)
- # define RADEON_GMC_DST_YVYU (12 << 8)
- # define RADEON_GMC_DST_AYUV444 (14 << 8)
- # define RADEON_GMC_DST_ARGB4444 (15 << 8)
- # define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8)
- # define RADEON_GMC_DST_DATATYPE_SHIFT 8
- # define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12)
- # define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)
- # define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)
- # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
- # define RADEON_GMC_BYTE_PIX_ORDER (1 << 14)
- # define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14)
- # define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14)
- # define RADEON_GMC_CONVERSION_TEMP (1 << 15)
- # define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15)
- # define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15)
- # define RADEON_GMC_ROP3_MASK (0xff << 16)
- # define RADEON_DP_SRC_SOURCE_MASK (7 << 24)
- # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
- # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
- # define RADEON_GMC_3D_FCN_EN (1 << 27)
- # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
- # define RADEON_GMC_AUX_CLIP_DIS (1 << 29)
- # define RADEON_GMC_WR_MSK_DIS (1 << 30)
- # define RADEON_GMC_LD_BRUSH_Y_X (1 << 31)
- # define RADEON_ROP3_ZERO 0x00000000
- # define RADEON_ROP3_DSa 0x00880000
- # define RADEON_ROP3_SDna 0x00440000
- # define RADEON_ROP3_S 0x00cc0000
- # define RADEON_ROP3_DSna 0x00220000
- # define RADEON_ROP3_D 0x00aa0000
- # define RADEON_ROP3_DSx 0x00660000
- # define RADEON_ROP3_DSo 0x00ee0000
- # define RADEON_ROP3_DSon 0x00110000
- # define RADEON_ROP3_DSxn 0x00990000
- # define RADEON_ROP3_Dn 0x00550000
- # define RADEON_ROP3_SDno 0x00dd0000
- # define RADEON_ROP3_Sn 0x00330000
- # define RADEON_ROP3_DSno 0x00bb0000
- # define RADEON_ROP3_DSan 0x00770000
- # define RADEON_ROP3_ONE 0x00ff0000
- # define RADEON_ROP3_DPa 0x00a00000
- # define RADEON_ROP3_PDna 0x00500000
- # define RADEON_ROP3_P 0x00f00000
- # define RADEON_ROP3_DPna 0x000a0000
- # define RADEON_ROP3_D 0x00aa0000
- # define RADEON_ROP3_DPx 0x005a0000
- # define RADEON_ROP3_DPo 0x00fa0000
- # define RADEON_ROP3_DPon 0x00050000
- # define RADEON_ROP3_PDxn 0x00a50000
- # define RADEON_ROP3_PDno 0x00f50000
- # define RADEON_ROP3_Pn 0x000f0000
- # define RADEON_ROP3_DPno 0x00af0000
- # define RADEON_ROP3_DPan 0x005f0000
- #define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84
- #define RADEON_DP_MIX 0x16c8
- #define RADEON_DP_SRC_BKGD_CLR 0x15dc
- #define RADEON_DP_SRC_FRGD_CLR 0x15d8
- #define RADEON_DP_WRITE_MASK 0x16cc
- #define RADEON_DST_BRES_DEC 0x1630
- #define RADEON_DST_BRES_ERR 0x1628
- #define RADEON_DST_BRES_INC 0x162c
- #define RADEON_DST_BRES_LNTH 0x1634
- #define RADEON_DST_BRES_LNTH_SUB 0x1638
- #define RADEON_DST_HEIGHT 0x1410
- #define RADEON_DST_HEIGHT_WIDTH 0x143c
- #define RADEON_DST_HEIGHT_WIDTH_8 0x158c
- #define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4
- #define RADEON_DST_HEIGHT_Y 0x15a0
- #define RADEON_DST_LINE_START 0x1600
- #define RADEON_DST_LINE_END 0x1604
- #define RADEON_DST_LINE_PATCOUNT 0x1608
- # define RADEON_BRES_CNTL_SHIFT 8
- #define RADEON_DST_OFFSET 0x1404
- #define RADEON_DST_PITCH 0x1408
- #define RADEON_DST_PITCH_OFFSET 0x142c
- #define RADEON_DST_PITCH_OFFSET_C 0x1c80
- # define RADEON_PITCH_SHIFT 21
- # define RADEON_DST_TILE_LINEAR (0 << 30)
- # define RADEON_DST_TILE_MACRO (1 << 30)
- # define RADEON_DST_TILE_MICRO (2 << 30)
- # define RADEON_DST_TILE_BOTH (3 << 30)
- #define RADEON_DST_WIDTH 0x140c
- #define RADEON_DST_WIDTH_HEIGHT 0x1598
- #define RADEON_DST_WIDTH_X 0x1588
- #define RADEON_DST_WIDTH_X_INCY 0x159c
- #define RADEON_DST_X 0x141c
- #define RADEON_DST_X_SUB 0x15a4
- #define RADEON_DST_X_Y 0x1594
- #define RADEON_DST_Y 0x1420
- #define RADEON_DST_Y_SUB 0x15a8
- #define RADEON_DST_Y_X 0x1438
- #define RADEON_FCP_CNTL 0x0910
- # define RADEON_FCP0_SRC_PCICLK 0
- # define RADEON_FCP0_SRC_PCLK 1
- # define RADEON_FCP0_SRC_PCLKb 2
- # define RADEON_FCP0_SRC_HREF 3
- # define RADEON_FCP0_SRC_GND 4
- # define RADEON_FCP0_SRC_HREFb 5
- #define RADEON_FLUSH_1 0x1704
- #define RADEON_FLUSH_2 0x1708
- #define RADEON_FLUSH_3 0x170c
- #define RADEON_FLUSH_4 0x1710
- #define RADEON_FLUSH_5 0x1714
- #define RADEON_FLUSH_6 0x1718
- #define RADEON_FLUSH_7 0x171c
- #define RADEON_FOG_3D_TABLE_START 0x1810
- #define RADEON_FOG_3D_TABLE_END 0x1814
- #define RADEON_FOG_3D_TABLE_DENSITY 0x181c
- #define RADEON_FOG_TABLE_INDEX 0x1a14
- #define RADEON_FOG_TABLE_DATA 0x1a18
- #define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250
- #define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254
- # define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff
- # define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000
- # define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff
- # define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000
- # define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
- # define RADEON_FP_H_SYNC_WID_MASK 0x003f0000
- # define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff
- # define RADEON_FP_V_SYNC_WID_MASK 0x001f0000
- # define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000
- # define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010
- # define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000
- # define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010
- # define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
- # define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010
- # define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000
- # define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010
- #define RADEON_FP_GEN_CNTL 0x0284
- # define RADEON_FP_FPON (1 << 0)
- # define RADEON_FP_BLANK_EN (1 << 1)
- # define RADEON_FP_TMDS_EN (1 << 2)
- # define RADEON_FP_PANEL_FORMAT (1 << 3)
- # define RADEON_FP_EN_TMDS (1 << 7)
- # define RADEON_FP_DETECT_SENSE (1 << 8)
- # define RADEON_FP_DETECT_INT_POL (1 << 9)
- # define R200_FP_SOURCE_SEL_MASK (3 << 10)
- # define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)
- # define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)
- # define R200_FP_SOURCE_SEL_RMX (2 << 10)
- # define R200_FP_SOURCE_SEL_TRANS (3 << 10)
- # define RADEON_FP_SEL_CRTC1 (0 << 13)
- # define RADEON_FP_SEL_CRTC2 (1 << 13)
- # define R300_HPD_SEL(x) ((x) << 13)
- # define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
- # define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
- # define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)
- # define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18)
- # define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
- # define RADEON_FP_DFP_SYNC_SEL (1 << 21)
- # define RADEON_FP_CRTC_LOCK_8DOT (1 << 22)
- # define RADEON_FP_CRT_SYNC_SEL (1 << 23)
- # define RADEON_FP_USE_SHADOW_EN (1 << 24)
- # define RADEON_FP_CRT_SYNC_ALT (1 << 26)
- #define RADEON_FP2_GEN_CNTL 0x0288
- # define RADEON_FP2_BLANK_EN (1 << 1)
- # define RADEON_FP2_ON (1 << 2)
- # define RADEON_FP2_PANEL_FORMAT (1 << 3)
- # define RADEON_FP2_DETECT_SENSE (1 << 8)
- # define RADEON_FP2_DETECT_INT_POL (1 << 9)
- # define R200_FP2_SOURCE_SEL_MASK (3 << 10)
- # define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10)
- # define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10)
- # define R200_FP2_SOURCE_SEL_RMX (2 << 10)
- # define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10)
- # define RADEON_FP2_SRC_SEL_MASK (3 << 13)
- # define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13)
- # define RADEON_FP2_FP_POL (1 << 16)
- # define RADEON_FP2_LP_POL (1 << 17)
- # define RADEON_FP2_SCK_POL (1 << 18)
- # define RADEON_FP2_LCD_CNTL_MASK (7 << 19)
- # define RADEON_FP2_PAD_FLOP_EN (1 << 22)
- # define RADEON_FP2_CRC_EN (1 << 23)
- # define RADEON_FP2_CRC_READ_EN (1 << 24)
- # define RADEON_FP2_DVO_EN (1 << 25)
- # define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26)
- # define R200_FP2_DVO_RATE_SEL_SDR (1 << 27)
- # define R300_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28)
- # define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29)
- #define RADEON_FP_H_SYNC_STRT_WID 0x02c4
- #define RADEON_FP_H2_SYNC_STRT_WID 0x03c4
- #define RADEON_FP_HORZ_STRETCH 0x028c
- #define RADEON_FP_HORZ2_STRETCH 0x038c
- # define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff
- # define RADEON_HORZ_STRETCH_RATIO_MAX 4096
- # define RADEON_HORZ_PANEL_SIZE (0x1ff << 16)
- # define RADEON_HORZ_PANEL_SHIFT 16
- # define RADEON_HORZ_STRETCH_PIXREP (0 << 25)
- # define RADEON_HORZ_STRETCH_BLEND (1 << 26)
- # define RADEON_HORZ_STRETCH_ENABLE (1 << 25)
- # define RADEON_HORZ_AUTO_RATIO (1 << 27)
- # define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28)
- # define RADEON_HORZ_AUTO_RATIO_INC (1 << 31)
- #define RADEON_FP_HORZ_VERT_ACTIVE 0x0278
- #define RADEON_FP_V_SYNC_STRT_WID 0x02c8
- #define RADEON_FP_VERT_STRETCH 0x0290
- #define RADEON_FP_V2_SYNC_STRT_WID 0x03c8
- #define RADEON_FP_VERT2_STRETCH 0x0390
- # define RADEON_VERT_PANEL_SIZE (0xfff << 12)
- # define RADEON_VERT_PANEL_SHIFT 12
- # define RADEON_VERT_STRETCH_RATIO_MASK 0xfff
- # define RADEON_VERT_STRETCH_RATIO_SHIFT 0
- # define RADEON_VERT_STRETCH_RATIO_MAX 4096
- # define RADEON_VERT_STRETCH_ENABLE (1 << 25)
- # define RADEON_VERT_STRETCH_LINEREP (0…