/drivers/gpu/drm/nouveau/nouveau_bo.c

https://bitbucket.org/cresqo/cm7-p500-kernel · C · 822 lines · 662 code · 113 blank · 47 comment · 111 complexity · 406d1a49b4a3ad2addb265077f498718 MD5 · raw file

  1. /*
  2. * Copyright 2007 Dave Airlied
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. */
  24. /*
  25. * Authors: Dave Airlied <airlied@linux.ie>
  26. * Ben Skeggs <darktama@iinet.net.au>
  27. * Jeremy Kolb <jkolb@brandeis.edu>
  28. */
  29. #include "drmP.h"
  30. #include "nouveau_drm.h"
  31. #include "nouveau_drv.h"
  32. #include "nouveau_dma.h"
  33. #include <linux/log2.h>
  34. #include <linux/slab.h>
  35. static void
  36. nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
  37. {
  38. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  39. struct drm_device *dev = dev_priv->dev;
  40. struct nouveau_bo *nvbo = nouveau_bo(bo);
  41. ttm_bo_kunmap(&nvbo->kmap);
  42. if (unlikely(nvbo->gem))
  43. DRM_ERROR("bo %p still attached to GEM object\n", bo);
  44. if (nvbo->tile)
  45. nv10_mem_expire_tiling(dev, nvbo->tile, NULL);
  46. spin_lock(&dev_priv->ttm.bo_list_lock);
  47. list_del(&nvbo->head);
  48. spin_unlock(&dev_priv->ttm.bo_list_lock);
  49. kfree(nvbo);
  50. }
  51. static void
  52. nouveau_bo_fixup_align(struct drm_device *dev,
  53. uint32_t tile_mode, uint32_t tile_flags,
  54. int *align, int *size)
  55. {
  56. struct drm_nouveau_private *dev_priv = dev->dev_private;
  57. /*
  58. * Some of the tile_flags have a periodic structure of N*4096 bytes,
  59. * align to to that as well as the page size. Align the size to the
  60. * appropriate boundaries. This does imply that sizes are rounded up
  61. * 3-7 pages, so be aware of this and do not waste memory by allocating
  62. * many small buffers.
  63. */
  64. if (dev_priv->card_type == NV_50) {
  65. uint32_t block_size = dev_priv->vram_size >> 15;
  66. int i;
  67. switch (tile_flags) {
  68. case 0x1800:
  69. case 0x2800:
  70. case 0x4800:
  71. case 0x7a00:
  72. if (is_power_of_2(block_size)) {
  73. for (i = 1; i < 10; i++) {
  74. *align = 12 * i * block_size;
  75. if (!(*align % 65536))
  76. break;
  77. }
  78. } else {
  79. for (i = 1; i < 10; i++) {
  80. *align = 8 * i * block_size;
  81. if (!(*align % 65536))
  82. break;
  83. }
  84. }
  85. *size = roundup(*size, *align);
  86. break;
  87. default:
  88. break;
  89. }
  90. } else {
  91. if (tile_mode) {
  92. if (dev_priv->chipset >= 0x40) {
  93. *align = 65536;
  94. *size = roundup(*size, 64 * tile_mode);
  95. } else if (dev_priv->chipset >= 0x30) {
  96. *align = 32768;
  97. *size = roundup(*size, 64 * tile_mode);
  98. } else if (dev_priv->chipset >= 0x20) {
  99. *align = 16384;
  100. *size = roundup(*size, 64 * tile_mode);
  101. } else if (dev_priv->chipset >= 0x10) {
  102. *align = 16384;
  103. *size = roundup(*size, 32 * tile_mode);
  104. }
  105. }
  106. }
  107. /* ALIGN works only on powers of two. */
  108. *size = roundup(*size, PAGE_SIZE);
  109. if (dev_priv->card_type == NV_50) {
  110. *size = roundup(*size, 65536);
  111. *align = max(65536, *align);
  112. }
  113. }
  114. int
  115. nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
  116. int size, int align, uint32_t flags, uint32_t tile_mode,
  117. uint32_t tile_flags, bool no_vm, bool mappable,
  118. struct nouveau_bo **pnvbo)
  119. {
  120. struct drm_nouveau_private *dev_priv = dev->dev_private;
  121. struct nouveau_bo *nvbo;
  122. int ret = 0;
  123. nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
  124. if (!nvbo)
  125. return -ENOMEM;
  126. INIT_LIST_HEAD(&nvbo->head);
  127. INIT_LIST_HEAD(&nvbo->entry);
  128. nvbo->mappable = mappable;
  129. nvbo->no_vm = no_vm;
  130. nvbo->tile_mode = tile_mode;
  131. nvbo->tile_flags = tile_flags;
  132. nouveau_bo_fixup_align(dev, tile_mode, tile_flags, &align, &size);
  133. align >>= PAGE_SHIFT;
  134. nvbo->placement.fpfn = 0;
  135. nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0;
  136. nouveau_bo_placement_set(nvbo, flags, 0);
  137. nvbo->channel = chan;
  138. ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
  139. ttm_bo_type_device, &nvbo->placement, align, 0,
  140. false, NULL, size, nouveau_bo_del_ttm);
  141. if (ret) {
  142. /* ttm will call nouveau_bo_del_ttm if it fails.. */
  143. return ret;
  144. }
  145. nvbo->channel = NULL;
  146. spin_lock(&dev_priv->ttm.bo_list_lock);
  147. list_add_tail(&nvbo->head, &dev_priv->ttm.bo_list);
  148. spin_unlock(&dev_priv->ttm.bo_list_lock);
  149. *pnvbo = nvbo;
  150. return 0;
  151. }
  152. static void
  153. set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
  154. {
  155. *n = 0;
  156. if (type & TTM_PL_FLAG_VRAM)
  157. pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
  158. if (type & TTM_PL_FLAG_TT)
  159. pl[(*n)++] = TTM_PL_FLAG_TT | flags;
  160. if (type & TTM_PL_FLAG_SYSTEM)
  161. pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
  162. }
  163. void
  164. nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
  165. {
  166. struct ttm_placement *pl = &nvbo->placement;
  167. uint32_t flags = TTM_PL_MASK_CACHING |
  168. (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
  169. pl->placement = nvbo->placements;
  170. set_placement_list(nvbo->placements, &pl->num_placement,
  171. type, flags);
  172. pl->busy_placement = nvbo->busy_placements;
  173. set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
  174. type | busy, flags);
  175. }
  176. int
  177. nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
  178. {
  179. struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
  180. struct ttm_buffer_object *bo = &nvbo->bo;
  181. int ret;
  182. if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
  183. NV_ERROR(nouveau_bdev(bo->bdev)->dev,
  184. "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
  185. 1 << bo->mem.mem_type, memtype);
  186. return -EINVAL;
  187. }
  188. if (nvbo->pin_refcnt++)
  189. return 0;
  190. ret = ttm_bo_reserve(bo, false, false, false, 0);
  191. if (ret)
  192. goto out;
  193. nouveau_bo_placement_set(nvbo, memtype, 0);
  194. ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false);
  195. if (ret == 0) {
  196. switch (bo->mem.mem_type) {
  197. case TTM_PL_VRAM:
  198. dev_priv->fb_aper_free -= bo->mem.size;
  199. break;
  200. case TTM_PL_TT:
  201. dev_priv->gart_info.aper_free -= bo->mem.size;
  202. break;
  203. default:
  204. break;
  205. }
  206. }
  207. ttm_bo_unreserve(bo);
  208. out:
  209. if (unlikely(ret))
  210. nvbo->pin_refcnt--;
  211. return ret;
  212. }
  213. int
  214. nouveau_bo_unpin(struct nouveau_bo *nvbo)
  215. {
  216. struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
  217. struct ttm_buffer_object *bo = &nvbo->bo;
  218. int ret;
  219. if (--nvbo->pin_refcnt)
  220. return 0;
  221. ret = ttm_bo_reserve(bo, false, false, false, 0);
  222. if (ret)
  223. return ret;
  224. nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
  225. ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false);
  226. if (ret == 0) {
  227. switch (bo->mem.mem_type) {
  228. case TTM_PL_VRAM:
  229. dev_priv->fb_aper_free += bo->mem.size;
  230. break;
  231. case TTM_PL_TT:
  232. dev_priv->gart_info.aper_free += bo->mem.size;
  233. break;
  234. default:
  235. break;
  236. }
  237. }
  238. ttm_bo_unreserve(bo);
  239. return ret;
  240. }
  241. int
  242. nouveau_bo_map(struct nouveau_bo *nvbo)
  243. {
  244. int ret;
  245. ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
  246. if (ret)
  247. return ret;
  248. ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
  249. ttm_bo_unreserve(&nvbo->bo);
  250. return ret;
  251. }
  252. void
  253. nouveau_bo_unmap(struct nouveau_bo *nvbo)
  254. {
  255. ttm_bo_kunmap(&nvbo->kmap);
  256. }
  257. u16
  258. nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
  259. {
  260. bool is_iomem;
  261. u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
  262. mem = &mem[index];
  263. if (is_iomem)
  264. return ioread16_native((void __force __iomem *)mem);
  265. else
  266. return *mem;
  267. }
  268. void
  269. nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
  270. {
  271. bool is_iomem;
  272. u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
  273. mem = &mem[index];
  274. if (is_iomem)
  275. iowrite16_native(val, (void __force __iomem *)mem);
  276. else
  277. *mem = val;
  278. }
  279. u32
  280. nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
  281. {
  282. bool is_iomem;
  283. u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
  284. mem = &mem[index];
  285. if (is_iomem)
  286. return ioread32_native((void __force __iomem *)mem);
  287. else
  288. return *mem;
  289. }
  290. void
  291. nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
  292. {
  293. bool is_iomem;
  294. u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
  295. mem = &mem[index];
  296. if (is_iomem)
  297. iowrite32_native(val, (void __force __iomem *)mem);
  298. else
  299. *mem = val;
  300. }
  301. static struct ttm_backend *
  302. nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
  303. {
  304. struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
  305. struct drm_device *dev = dev_priv->dev;
  306. switch (dev_priv->gart_info.type) {
  307. #if __OS_HAS_AGP
  308. case NOUVEAU_GART_AGP:
  309. return ttm_agp_backend_init(bdev, dev->agp->bridge);
  310. #endif
  311. case NOUVEAU_GART_SGDMA:
  312. return nouveau_sgdma_init_ttm(dev);
  313. default:
  314. NV_ERROR(dev, "Unknown GART type %d\n",
  315. dev_priv->gart_info.type);
  316. break;
  317. }
  318. return NULL;
  319. }
  320. static int
  321. nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
  322. {
  323. /* We'll do this from user space. */
  324. return 0;
  325. }
  326. static int
  327. nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
  328. struct ttm_mem_type_manager *man)
  329. {
  330. struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
  331. struct drm_device *dev = dev_priv->dev;
  332. switch (type) {
  333. case TTM_PL_SYSTEM:
  334. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  335. man->available_caching = TTM_PL_MASK_CACHING;
  336. man->default_caching = TTM_PL_FLAG_CACHED;
  337. break;
  338. case TTM_PL_VRAM:
  339. man->flags = TTM_MEMTYPE_FLAG_FIXED |
  340. TTM_MEMTYPE_FLAG_MAPPABLE;
  341. man->available_caching = TTM_PL_FLAG_UNCACHED |
  342. TTM_PL_FLAG_WC;
  343. man->default_caching = TTM_PL_FLAG_WC;
  344. man->gpu_offset = dev_priv->vm_vram_base;
  345. break;
  346. case TTM_PL_TT:
  347. switch (dev_priv->gart_info.type) {
  348. case NOUVEAU_GART_AGP:
  349. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
  350. man->available_caching = TTM_PL_FLAG_UNCACHED;
  351. man->default_caching = TTM_PL_FLAG_UNCACHED;
  352. break;
  353. case NOUVEAU_GART_SGDMA:
  354. man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
  355. TTM_MEMTYPE_FLAG_CMA;
  356. man->available_caching = TTM_PL_MASK_CACHING;
  357. man->default_caching = TTM_PL_FLAG_CACHED;
  358. break;
  359. default:
  360. NV_ERROR(dev, "Unknown GART type: %d\n",
  361. dev_priv->gart_info.type);
  362. return -EINVAL;
  363. }
  364. man->gpu_offset = dev_priv->vm_gart_base;
  365. break;
  366. default:
  367. NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
  368. return -EINVAL;
  369. }
  370. return 0;
  371. }
  372. static void
  373. nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
  374. {
  375. struct nouveau_bo *nvbo = nouveau_bo(bo);
  376. switch (bo->mem.mem_type) {
  377. case TTM_PL_VRAM:
  378. nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
  379. TTM_PL_FLAG_SYSTEM);
  380. break;
  381. default:
  382. nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
  383. break;
  384. }
  385. *pl = nvbo->placement;
  386. }
  387. /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
  388. * TTM_PL_{VRAM,TT} directly.
  389. */
  390. static int
  391. nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
  392. struct nouveau_bo *nvbo, bool evict,
  393. bool no_wait_reserve, bool no_wait_gpu,
  394. struct ttm_mem_reg *new_mem)
  395. {
  396. struct nouveau_fence *fence = NULL;
  397. int ret;
  398. ret = nouveau_fence_new(chan, &fence, true);
  399. if (ret)
  400. return ret;
  401. ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL,
  402. evict, no_wait_reserve, no_wait_gpu, new_mem);
  403. if (nvbo->channel && nvbo->channel != chan)
  404. ret = nouveau_fence_wait(fence, NULL, false, false);
  405. nouveau_fence_unref((void *)&fence);
  406. return ret;
  407. }
  408. static inline uint32_t
  409. nouveau_bo_mem_ctxdma(struct nouveau_bo *nvbo, struct nouveau_channel *chan,
  410. struct ttm_mem_reg *mem)
  411. {
  412. if (chan == nouveau_bdev(nvbo->bo.bdev)->channel) {
  413. if (mem->mem_type == TTM_PL_TT)
  414. return NvDmaGART;
  415. return NvDmaVRAM;
  416. }
  417. if (mem->mem_type == TTM_PL_TT)
  418. return chan->gart_handle;
  419. return chan->vram_handle;
  420. }
  421. static int
  422. nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
  423. bool no_wait_reserve, bool no_wait_gpu,
  424. struct ttm_mem_reg *new_mem)
  425. {
  426. struct nouveau_bo *nvbo = nouveau_bo(bo);
  427. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  428. struct ttm_mem_reg *old_mem = &bo->mem;
  429. struct nouveau_channel *chan;
  430. uint64_t src_offset, dst_offset;
  431. uint32_t page_count;
  432. int ret;
  433. chan = nvbo->channel;
  434. if (!chan || nvbo->tile_flags || nvbo->no_vm)
  435. chan = dev_priv->channel;
  436. src_offset = old_mem->mm_node->start << PAGE_SHIFT;
  437. dst_offset = new_mem->mm_node->start << PAGE_SHIFT;
  438. if (chan != dev_priv->channel) {
  439. if (old_mem->mem_type == TTM_PL_TT)
  440. src_offset += dev_priv->vm_gart_base;
  441. else
  442. src_offset += dev_priv->vm_vram_base;
  443. if (new_mem->mem_type == TTM_PL_TT)
  444. dst_offset += dev_priv->vm_gart_base;
  445. else
  446. dst_offset += dev_priv->vm_vram_base;
  447. }
  448. ret = RING_SPACE(chan, 3);
  449. if (ret)
  450. return ret;
  451. BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
  452. OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, old_mem));
  453. OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, new_mem));
  454. if (dev_priv->card_type >= NV_50) {
  455. ret = RING_SPACE(chan, 4);
  456. if (ret)
  457. return ret;
  458. BEGIN_RING(chan, NvSubM2MF, 0x0200, 1);
  459. OUT_RING(chan, 1);
  460. BEGIN_RING(chan, NvSubM2MF, 0x021c, 1);
  461. OUT_RING(chan, 1);
  462. }
  463. page_count = new_mem->num_pages;
  464. while (page_count) {
  465. int line_count = (page_count > 2047) ? 2047 : page_count;
  466. if (dev_priv->card_type >= NV_50) {
  467. ret = RING_SPACE(chan, 3);
  468. if (ret)
  469. return ret;
  470. BEGIN_RING(chan, NvSubM2MF, 0x0238, 2);
  471. OUT_RING(chan, upper_32_bits(src_offset));
  472. OUT_RING(chan, upper_32_bits(dst_offset));
  473. }
  474. ret = RING_SPACE(chan, 11);
  475. if (ret)
  476. return ret;
  477. BEGIN_RING(chan, NvSubM2MF,
  478. NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
  479. OUT_RING(chan, lower_32_bits(src_offset));
  480. OUT_RING(chan, lower_32_bits(dst_offset));
  481. OUT_RING(chan, PAGE_SIZE); /* src_pitch */
  482. OUT_RING(chan, PAGE_SIZE); /* dst_pitch */
  483. OUT_RING(chan, PAGE_SIZE); /* line_length */
  484. OUT_RING(chan, line_count);
  485. OUT_RING(chan, (1<<8)|(1<<0));
  486. OUT_RING(chan, 0);
  487. BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
  488. OUT_RING(chan, 0);
  489. page_count -= line_count;
  490. src_offset += (PAGE_SIZE * line_count);
  491. dst_offset += (PAGE_SIZE * line_count);
  492. }
  493. return nouveau_bo_move_accel_cleanup(chan, nvbo, evict, no_wait_reserve, no_wait_gpu, new_mem);
  494. }
  495. static int
  496. nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
  497. bool no_wait_reserve, bool no_wait_gpu,
  498. struct ttm_mem_reg *new_mem)
  499. {
  500. u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
  501. struct ttm_placement placement;
  502. struct ttm_mem_reg tmp_mem;
  503. int ret;
  504. placement.fpfn = placement.lpfn = 0;
  505. placement.num_placement = placement.num_busy_placement = 1;
  506. placement.placement = placement.busy_placement = &placement_memtype;
  507. tmp_mem = *new_mem;
  508. tmp_mem.mm_node = NULL;
  509. ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
  510. if (ret)
  511. return ret;
  512. ret = ttm_tt_bind(bo->ttm, &tmp_mem);
  513. if (ret)
  514. goto out;
  515. ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
  516. if (ret)
  517. goto out;
  518. ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
  519. out:
  520. if (tmp_mem.mm_node) {
  521. spin_lock(&bo->bdev->glob->lru_lock);
  522. drm_mm_put_block(tmp_mem.mm_node);
  523. spin_unlock(&bo->bdev->glob->lru_lock);
  524. }
  525. return ret;
  526. }
  527. static int
  528. nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
  529. bool no_wait_reserve, bool no_wait_gpu,
  530. struct ttm_mem_reg *new_mem)
  531. {
  532. u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
  533. struct ttm_placement placement;
  534. struct ttm_mem_reg tmp_mem;
  535. int ret;
  536. placement.fpfn = placement.lpfn = 0;
  537. placement.num_placement = placement.num_busy_placement = 1;
  538. placement.placement = placement.busy_placement = &placement_memtype;
  539. tmp_mem = *new_mem;
  540. tmp_mem.mm_node = NULL;
  541. ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
  542. if (ret)
  543. return ret;
  544. ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, &tmp_mem);
  545. if (ret)
  546. goto out;
  547. ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
  548. if (ret)
  549. goto out;
  550. out:
  551. if (tmp_mem.mm_node) {
  552. spin_lock(&bo->bdev->glob->lru_lock);
  553. drm_mm_put_block(tmp_mem.mm_node);
  554. spin_unlock(&bo->bdev->glob->lru_lock);
  555. }
  556. return ret;
  557. }
  558. static int
  559. nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
  560. struct nouveau_tile_reg **new_tile)
  561. {
  562. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  563. struct drm_device *dev = dev_priv->dev;
  564. struct nouveau_bo *nvbo = nouveau_bo(bo);
  565. uint64_t offset;
  566. int ret;
  567. if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) {
  568. /* Nothing to do. */
  569. *new_tile = NULL;
  570. return 0;
  571. }
  572. offset = new_mem->mm_node->start << PAGE_SHIFT;
  573. if (dev_priv->card_type == NV_50) {
  574. ret = nv50_mem_vm_bind_linear(dev,
  575. offset + dev_priv->vm_vram_base,
  576. new_mem->size, nvbo->tile_flags,
  577. offset);
  578. if (ret)
  579. return ret;
  580. } else if (dev_priv->card_type >= NV_10) {
  581. *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
  582. nvbo->tile_mode);
  583. }
  584. return 0;
  585. }
  586. static void
  587. nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
  588. struct nouveau_tile_reg *new_tile,
  589. struct nouveau_tile_reg **old_tile)
  590. {
  591. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  592. struct drm_device *dev = dev_priv->dev;
  593. if (dev_priv->card_type >= NV_10 &&
  594. dev_priv->card_type < NV_50) {
  595. if (*old_tile)
  596. nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj);
  597. *old_tile = new_tile;
  598. }
  599. }
  600. static int
  601. nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
  602. bool no_wait_reserve, bool no_wait_gpu,
  603. struct ttm_mem_reg *new_mem)
  604. {
  605. struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  606. struct nouveau_bo *nvbo = nouveau_bo(bo);
  607. struct ttm_mem_reg *old_mem = &bo->mem;
  608. struct nouveau_tile_reg *new_tile = NULL;
  609. int ret = 0;
  610. ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
  611. if (ret)
  612. return ret;
  613. /* Software copy if the card isn't up and running yet. */
  614. if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE ||
  615. !dev_priv->channel) {
  616. ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
  617. goto out;
  618. }
  619. /* Fake bo copy. */
  620. if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
  621. BUG_ON(bo->mem.mm_node != NULL);
  622. bo->mem = *new_mem;
  623. new_mem->mm_node = NULL;
  624. goto out;
  625. }
  626. /* Hardware assisted copy. */
  627. if (new_mem->mem_type == TTM_PL_SYSTEM)
  628. ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
  629. else if (old_mem->mem_type == TTM_PL_SYSTEM)
  630. ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
  631. else
  632. ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
  633. if (!ret)
  634. goto out;
  635. /* Fallback to software copy. */
  636. ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
  637. out:
  638. if (ret)
  639. nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
  640. else
  641. nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
  642. return ret;
  643. }
  644. static int
  645. nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
  646. {
  647. return 0;
  648. }
  649. static int
  650. nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
  651. {
  652. struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
  653. struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
  654. struct drm_device *dev = dev_priv->dev;
  655. mem->bus.addr = NULL;
  656. mem->bus.offset = 0;
  657. mem->bus.size = mem->num_pages << PAGE_SHIFT;
  658. mem->bus.base = 0;
  659. mem->bus.is_iomem = false;
  660. if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
  661. return -EINVAL;
  662. switch (mem->mem_type) {
  663. case TTM_PL_SYSTEM:
  664. /* System memory */
  665. return 0;
  666. case TTM_PL_TT:
  667. #if __OS_HAS_AGP
  668. if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
  669. mem->bus.offset = mem->mm_node->start << PAGE_SHIFT;
  670. mem->bus.base = dev_priv->gart_info.aper_base;
  671. mem->bus.is_iomem = true;
  672. }
  673. #endif
  674. break;
  675. case TTM_PL_VRAM:
  676. mem->bus.offset = mem->mm_node->start << PAGE_SHIFT;
  677. mem->bus.base = drm_get_resource_start(dev, 1);
  678. mem->bus.is_iomem = true;
  679. break;
  680. default:
  681. return -EINVAL;
  682. }
  683. return 0;
  684. }
  685. static void
  686. nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
  687. {
  688. }
  689. static int
  690. nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
  691. {
  692. return 0;
  693. }
  694. struct ttm_bo_driver nouveau_bo_driver = {
  695. .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
  696. .invalidate_caches = nouveau_bo_invalidate_caches,
  697. .init_mem_type = nouveau_bo_init_mem_type,
  698. .evict_flags = nouveau_bo_evict_flags,
  699. .move = nouveau_bo_move,
  700. .verify_access = nouveau_bo_verify_access,
  701. .sync_obj_signaled = nouveau_fence_signalled,
  702. .sync_obj_wait = nouveau_fence_wait,
  703. .sync_obj_flush = nouveau_fence_flush,
  704. .sync_obj_unref = nouveau_fence_unref,
  705. .sync_obj_ref = nouveau_fence_ref,
  706. .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
  707. .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
  708. .io_mem_free = &nouveau_ttm_io_mem_free,
  709. };