/drivers/edac/edac_core.h

https://bitbucket.org/cresqo/cm7-p500-kernel · C Header · 900 lines · 439 code · 129 blank · 332 comment · 10 complexity · 2eb901de764e56e04a33b2bfde2c06e3 MD5 · raw file

  1. /*
  2. * Defines, structures, APIs for edac_core module
  3. *
  4. * (C) 2007 Linux Networx (http://lnxi.com)
  5. * This file may be distributed under the terms of the
  6. * GNU General Public License.
  7. *
  8. * Written by Thayne Harbaugh
  9. * Based on work by Dan Hollis <goemon at anime dot net> and others.
  10. * http://www.anime.net/~goemon/linux-ecc/
  11. *
  12. * NMI handling support added by
  13. * Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
  14. *
  15. * Refactored for multi-source files:
  16. * Doug Thompson <norsk5@xmission.com>
  17. *
  18. */
  19. #ifndef _EDAC_CORE_H_
  20. #define _EDAC_CORE_H_
  21. #include <linux/kernel.h>
  22. #include <linux/types.h>
  23. #include <linux/module.h>
  24. #include <linux/spinlock.h>
  25. #include <linux/smp.h>
  26. #include <linux/pci.h>
  27. #include <linux/time.h>
  28. #include <linux/nmi.h>
  29. #include <linux/rcupdate.h>
  30. #include <linux/completion.h>
  31. #include <linux/kobject.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/sysdev.h>
  34. #include <linux/workqueue.h>
  35. #define EDAC_MC_LABEL_LEN 31
  36. #define EDAC_DEVICE_NAME_LEN 31
  37. #define EDAC_ATTRIB_VALUE_LEN 15
  38. #define MC_PROC_NAME_MAX_LEN 7
  39. #if PAGE_SHIFT < 20
  40. #define PAGES_TO_MiB( pages ) ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
  41. #else /* PAGE_SHIFT > 20 */
  42. #define PAGES_TO_MiB( pages ) ( ( pages ) << ( PAGE_SHIFT - 20 ) )
  43. #endif
  44. #define edac_printk(level, prefix, fmt, arg...) \
  45. printk(level "EDAC " prefix ": " fmt, ##arg)
  46. #define edac_printk_verbose(level, prefix, fmt, arg...) \
  47. printk(level "EDAC " prefix ": " "in %s, line at %d: " fmt, \
  48. __FILE__, __LINE__, ##arg)
  49. #define edac_mc_printk(mci, level, fmt, arg...) \
  50. printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
  51. #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
  52. printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
  53. /* edac_device printk */
  54. #define edac_device_printk(ctl, level, fmt, arg...) \
  55. printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
  56. /* edac_pci printk */
  57. #define edac_pci_printk(ctl, level, fmt, arg...) \
  58. printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)
  59. /* prefixes for edac_printk() and edac_mc_printk() */
  60. #define EDAC_MC "MC"
  61. #define EDAC_PCI "PCI"
  62. #define EDAC_DEBUG "DEBUG"
  63. #ifdef CONFIG_EDAC_DEBUG
  64. extern int edac_debug_level;
  65. extern const char *edac_mem_types[];
  66. #ifndef CONFIG_EDAC_DEBUG_VERBOSE
  67. #define edac_debug_printk(level, fmt, arg...) \
  68. do { \
  69. if (level <= edac_debug_level) \
  70. edac_printk(KERN_DEBUG, EDAC_DEBUG, \
  71. "%s: " fmt, __func__, ##arg); \
  72. } while (0)
  73. #else /* CONFIG_EDAC_DEBUG_VERBOSE */
  74. #define edac_debug_printk(level, fmt, arg...) \
  75. do { \
  76. if (level <= edac_debug_level) \
  77. edac_printk_verbose(KERN_DEBUG, EDAC_DEBUG, fmt, \
  78. ##arg); \
  79. } while (0)
  80. #endif
  81. #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
  82. #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
  83. #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
  84. #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
  85. #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
  86. #else /* !CONFIG_EDAC_DEBUG */
  87. #define debugf0( ... )
  88. #define debugf1( ... )
  89. #define debugf2( ... )
  90. #define debugf3( ... )
  91. #define debugf4( ... )
  92. #endif /* !CONFIG_EDAC_DEBUG */
  93. #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
  94. PCI_DEVICE_ID_ ## vend ## _ ## dev
  95. #define edac_dev_name(dev) (dev)->dev_name
  96. /* memory devices */
  97. enum dev_type {
  98. DEV_UNKNOWN = 0,
  99. DEV_X1,
  100. DEV_X2,
  101. DEV_X4,
  102. DEV_X8,
  103. DEV_X16,
  104. DEV_X32, /* Do these parts exist? */
  105. DEV_X64 /* Do these parts exist? */
  106. };
  107. #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
  108. #define DEV_FLAG_X1 BIT(DEV_X1)
  109. #define DEV_FLAG_X2 BIT(DEV_X2)
  110. #define DEV_FLAG_X4 BIT(DEV_X4)
  111. #define DEV_FLAG_X8 BIT(DEV_X8)
  112. #define DEV_FLAG_X16 BIT(DEV_X16)
  113. #define DEV_FLAG_X32 BIT(DEV_X32)
  114. #define DEV_FLAG_X64 BIT(DEV_X64)
  115. /* memory types */
  116. enum mem_type {
  117. MEM_EMPTY = 0, /* Empty csrow */
  118. MEM_RESERVED, /* Reserved csrow type */
  119. MEM_UNKNOWN, /* Unknown csrow type */
  120. MEM_FPM, /* Fast page mode */
  121. MEM_EDO, /* Extended data out */
  122. MEM_BEDO, /* Burst Extended data out */
  123. MEM_SDR, /* Single data rate SDRAM */
  124. MEM_RDR, /* Registered single data rate SDRAM */
  125. MEM_DDR, /* Double data rate SDRAM */
  126. MEM_RDDR, /* Registered Double data rate SDRAM */
  127. MEM_RMBS, /* Rambus DRAM */
  128. MEM_DDR2, /* DDR2 RAM */
  129. MEM_FB_DDR2, /* fully buffered DDR2 */
  130. MEM_RDDR2, /* Registered DDR2 RAM */
  131. MEM_XDR, /* Rambus XDR */
  132. MEM_DDR3, /* DDR3 RAM */
  133. MEM_RDDR3, /* Registered DDR3 RAM */
  134. };
  135. #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
  136. #define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
  137. #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
  138. #define MEM_FLAG_FPM BIT(MEM_FPM)
  139. #define MEM_FLAG_EDO BIT(MEM_EDO)
  140. #define MEM_FLAG_BEDO BIT(MEM_BEDO)
  141. #define MEM_FLAG_SDR BIT(MEM_SDR)
  142. #define MEM_FLAG_RDR BIT(MEM_RDR)
  143. #define MEM_FLAG_DDR BIT(MEM_DDR)
  144. #define MEM_FLAG_RDDR BIT(MEM_RDDR)
  145. #define MEM_FLAG_RMBS BIT(MEM_RMBS)
  146. #define MEM_FLAG_DDR2 BIT(MEM_DDR2)
  147. #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
  148. #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
  149. #define MEM_FLAG_XDR BIT(MEM_XDR)
  150. #define MEM_FLAG_DDR3 BIT(MEM_DDR3)
  151. #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
  152. /* chipset Error Detection and Correction capabilities and mode */
  153. enum edac_type {
  154. EDAC_UNKNOWN = 0, /* Unknown if ECC is available */
  155. EDAC_NONE, /* Doesnt support ECC */
  156. EDAC_RESERVED, /* Reserved ECC type */
  157. EDAC_PARITY, /* Detects parity errors */
  158. EDAC_EC, /* Error Checking - no correction */
  159. EDAC_SECDED, /* Single bit error correction, Double detection */
  160. EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */
  161. EDAC_S4ECD4ED, /* Chipkill x4 devices */
  162. EDAC_S8ECD8ED, /* Chipkill x8 devices */
  163. EDAC_S16ECD16ED, /* Chipkill x16 devices */
  164. };
  165. #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
  166. #define EDAC_FLAG_NONE BIT(EDAC_NONE)
  167. #define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
  168. #define EDAC_FLAG_EC BIT(EDAC_EC)
  169. #define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
  170. #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
  171. #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
  172. #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
  173. #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
  174. /* scrubbing capabilities */
  175. enum scrub_type {
  176. SCRUB_UNKNOWN = 0, /* Unknown if scrubber is available */
  177. SCRUB_NONE, /* No scrubber */
  178. SCRUB_SW_PROG, /* SW progressive (sequential) scrubbing */
  179. SCRUB_SW_SRC, /* Software scrub only errors */
  180. SCRUB_SW_PROG_SRC, /* Progressive software scrub from an error */
  181. SCRUB_SW_TUNABLE, /* Software scrub frequency is tunable */
  182. SCRUB_HW_PROG, /* HW progressive (sequential) scrubbing */
  183. SCRUB_HW_SRC, /* Hardware scrub only errors */
  184. SCRUB_HW_PROG_SRC, /* Progressive hardware scrub from an error */
  185. SCRUB_HW_TUNABLE /* Hardware scrub frequency is tunable */
  186. };
  187. #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
  188. #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
  189. #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
  190. #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
  191. #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
  192. #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
  193. #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
  194. #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
  195. /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
  196. /* EDAC internal operation states */
  197. #define OP_ALLOC 0x100
  198. #define OP_RUNNING_POLL 0x201
  199. #define OP_RUNNING_INTERRUPT 0x202
  200. #define OP_RUNNING_POLL_INTR 0x203
  201. #define OP_OFFLINE 0x300
  202. /*
  203. * There are several things to be aware of that aren't at all obvious:
  204. *
  205. *
  206. * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
  207. *
  208. * These are some of the many terms that are thrown about that don't always
  209. * mean what people think they mean (Inconceivable!). In the interest of
  210. * creating a common ground for discussion, terms and their definitions
  211. * will be established.
  212. *
  213. * Memory devices: The individual chip on a memory stick. These devices
  214. * commonly output 4 and 8 bits each. Grouping several
  215. * of these in parallel provides 64 bits which is common
  216. * for a memory stick.
  217. *
  218. * Memory Stick: A printed circuit board that agregates multiple
  219. * memory devices in parallel. This is the atomic
  220. * memory component that is purchaseable by Joe consumer
  221. * and loaded into a memory socket.
  222. *
  223. * Socket: A physical connector on the motherboard that accepts
  224. * a single memory stick.
  225. *
  226. * Channel: Set of memory devices on a memory stick that must be
  227. * grouped in parallel with one or more additional
  228. * channels from other memory sticks. This parallel
  229. * grouping of the output from multiple channels are
  230. * necessary for the smallest granularity of memory access.
  231. * Some memory controllers are capable of single channel -
  232. * which means that memory sticks can be loaded
  233. * individually. Other memory controllers are only
  234. * capable of dual channel - which means that memory
  235. * sticks must be loaded as pairs (see "socket set").
  236. *
  237. * Chip-select row: All of the memory devices that are selected together.
  238. * for a single, minimum grain of memory access.
  239. * This selects all of the parallel memory devices across
  240. * all of the parallel channels. Common chip-select rows
  241. * for single channel are 64 bits, for dual channel 128
  242. * bits.
  243. *
  244. * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
  245. * Motherboards commonly drive two chip-select pins to
  246. * a memory stick. A single-ranked stick, will occupy
  247. * only one of those rows. The other will be unused.
  248. *
  249. * Double-Ranked stick: A double-ranked stick has two chip-select rows which
  250. * access different sets of memory devices. The two
  251. * rows cannot be accessed concurrently.
  252. *
  253. * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
  254. * A double-sided stick has two chip-select rows which
  255. * access different sets of memory devices. The two
  256. * rows cannot be accessed concurrently. "Double-sided"
  257. * is irrespective of the memory devices being mounted
  258. * on both sides of the memory stick.
  259. *
  260. * Socket set: All of the memory sticks that are required for
  261. * a single memory access or all of the memory sticks
  262. * spanned by a chip-select row. A single socket set
  263. * has two chip-select rows and if double-sided sticks
  264. * are used these will occupy those chip-select rows.
  265. *
  266. * Bank: This term is avoided because it is unclear when
  267. * needing to distinguish between chip-select rows and
  268. * socket sets.
  269. *
  270. * Controller pages:
  271. *
  272. * Physical pages:
  273. *
  274. * Virtual pages:
  275. *
  276. *
  277. * STRUCTURE ORGANIZATION AND CHOICES
  278. *
  279. *
  280. *
  281. * PS - I enjoyed writing all that about as much as you enjoyed reading it.
  282. */
  283. struct channel_info {
  284. int chan_idx; /* channel index */
  285. u32 ce_count; /* Correctable Errors for this CHANNEL */
  286. char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
  287. struct csrow_info *csrow; /* the parent */
  288. };
  289. struct csrow_info {
  290. unsigned long first_page; /* first page number in dimm */
  291. unsigned long last_page; /* last page number in dimm */
  292. unsigned long page_mask; /* used for interleaving -
  293. * 0UL for non intlv
  294. */
  295. u32 nr_pages; /* number of pages in csrow */
  296. u32 grain; /* granularity of reported error in bytes */
  297. int csrow_idx; /* the chip-select row */
  298. enum dev_type dtype; /* memory device type */
  299. u32 ue_count; /* Uncorrectable Errors for this csrow */
  300. u32 ce_count; /* Correctable Errors for this csrow */
  301. enum mem_type mtype; /* memory csrow type */
  302. enum edac_type edac_mode; /* EDAC mode for this csrow */
  303. struct mem_ctl_info *mci; /* the parent */
  304. struct kobject kobj; /* sysfs kobject for this csrow */
  305. /* channel information for this csrow */
  306. u32 nr_channels;
  307. struct channel_info *channels;
  308. };
  309. struct mcidev_sysfs_group {
  310. const char *name; /* group name */
  311. struct mcidev_sysfs_attribute *mcidev_attr; /* group attributes */
  312. };
  313. struct mcidev_sysfs_group_kobj {
  314. struct list_head list; /* list for all instances within a mc */
  315. struct kobject kobj; /* kobj for the group */
  316. struct mcidev_sysfs_group *grp; /* group description table */
  317. struct mem_ctl_info *mci; /* the parent */
  318. };
  319. /* mcidev_sysfs_attribute structure
  320. * used for driver sysfs attributes and in mem_ctl_info
  321. * sysfs top level entries
  322. */
  323. struct mcidev_sysfs_attribute {
  324. /* It should use either attr or grp */
  325. struct attribute attr;
  326. struct mcidev_sysfs_group *grp; /* Points to a group of attributes */
  327. /* Ops for show/store values at the attribute - not used on group */
  328. ssize_t (*show)(struct mem_ctl_info *,char *);
  329. ssize_t (*store)(struct mem_ctl_info *, const char *,size_t);
  330. };
  331. /* MEMORY controller information structure
  332. */
  333. struct mem_ctl_info {
  334. struct list_head link; /* for global list of mem_ctl_info structs */
  335. struct module *owner; /* Module owner of this control struct */
  336. unsigned long mtype_cap; /* memory types supported by mc */
  337. unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
  338. unsigned long edac_cap; /* configuration capabilities - this is
  339. * closely related to edac_ctl_cap. The
  340. * difference is that the controller may be
  341. * capable of s4ecd4ed which would be listed
  342. * in edac_ctl_cap, but if channels aren't
  343. * capable of s4ecd4ed then the edac_cap would
  344. * not have that capability.
  345. */
  346. unsigned long scrub_cap; /* chipset scrub capabilities */
  347. enum scrub_type scrub_mode; /* current scrub mode */
  348. /* Translates sdram memory scrub rate given in bytes/sec to the
  349. internal representation and configures whatever else needs
  350. to be configured.
  351. */
  352. int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
  353. /* Get the current sdram memory scrub rate from the internal
  354. representation and converts it to the closest matching
  355. bandwith in bytes/sec.
  356. */
  357. int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
  358. /* pointer to edac checking routine */
  359. void (*edac_check) (struct mem_ctl_info * mci);
  360. /*
  361. * Remaps memory pages: controller pages to physical pages.
  362. * For most MC's, this will be NULL.
  363. */
  364. /* FIXME - why not send the phys page to begin with? */
  365. unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
  366. unsigned long page);
  367. int mc_idx;
  368. int nr_csrows;
  369. struct csrow_info *csrows;
  370. /*
  371. * FIXME - what about controllers on other busses? - IDs must be
  372. * unique. dev pointer should be sufficiently unique, but
  373. * BUS:SLOT.FUNC numbers may not be unique.
  374. */
  375. struct device *dev;
  376. const char *mod_name;
  377. const char *mod_ver;
  378. const char *ctl_name;
  379. const char *dev_name;
  380. char proc_name[MC_PROC_NAME_MAX_LEN + 1];
  381. void *pvt_info;
  382. u32 ue_noinfo_count; /* Uncorrectable Errors w/o info */
  383. u32 ce_noinfo_count; /* Correctable Errors w/o info */
  384. u32 ue_count; /* Total Uncorrectable Errors for this MC */
  385. u32 ce_count; /* Total Correctable Errors for this MC */
  386. unsigned long start_time; /* mci load start time (in jiffies) */
  387. /* this stuff is for safe removal of mc devices from global list while
  388. * NMI handlers may be traversing list
  389. */
  390. struct rcu_head rcu;
  391. struct completion complete;
  392. /* edac sysfs device control */
  393. struct kobject edac_mci_kobj;
  394. /* list for all grp instances within a mc */
  395. struct list_head grp_kobj_list;
  396. /* Additional top controller level attributes, but specified
  397. * by the low level driver.
  398. *
  399. * Set by the low level driver to provide attributes at the
  400. * controller level, same level as 'ue_count' and 'ce_count' above.
  401. * An array of structures, NULL terminated
  402. *
  403. * If attributes are desired, then set to array of attributes
  404. * If no attributes are desired, leave NULL
  405. */
  406. struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
  407. /* work struct for this MC */
  408. struct delayed_work work;
  409. /* the internal state of this controller instance */
  410. int op_state;
  411. };
  412. /*
  413. * The following are the structures to provide for a generic
  414. * or abstract 'edac_device'. This set of structures and the
  415. * code that implements the APIs for the same, provide for
  416. * registering EDAC type devices which are NOT standard memory.
  417. *
  418. * CPU caches (L1 and L2)
  419. * DMA engines
  420. * Core CPU swithces
  421. * Fabric switch units
  422. * PCIe interface controllers
  423. * other EDAC/ECC type devices that can be monitored for
  424. * errors, etc.
  425. *
  426. * It allows for a 2 level set of hiearchry. For example:
  427. *
  428. * cache could be composed of L1, L2 and L3 levels of cache.
  429. * Each CPU core would have its own L1 cache, while sharing
  430. * L2 and maybe L3 caches.
  431. *
  432. * View them arranged, via the sysfs presentation:
  433. * /sys/devices/system/edac/..
  434. *
  435. * mc/ <existing memory device directory>
  436. * cpu/cpu0/.. <L1 and L2 block directory>
  437. * /L1-cache/ce_count
  438. * /ue_count
  439. * /L2-cache/ce_count
  440. * /ue_count
  441. * cpu/cpu1/.. <L1 and L2 block directory>
  442. * /L1-cache/ce_count
  443. * /ue_count
  444. * /L2-cache/ce_count
  445. * /ue_count
  446. * ...
  447. *
  448. * the L1 and L2 directories would be "edac_device_block's"
  449. */
  450. struct edac_device_counter {
  451. u32 ue_count;
  452. u32 ce_count;
  453. };
  454. /* forward reference */
  455. struct edac_device_ctl_info;
  456. struct edac_device_block;
  457. /* edac_dev_sysfs_attribute structure
  458. * used for driver sysfs attributes in mem_ctl_info
  459. * for extra controls and attributes:
  460. * like high level error Injection controls
  461. */
  462. struct edac_dev_sysfs_attribute {
  463. struct attribute attr;
  464. ssize_t (*show)(struct edac_device_ctl_info *, char *);
  465. ssize_t (*store)(struct edac_device_ctl_info *, const char *, size_t);
  466. };
  467. /* edac_dev_sysfs_block_attribute structure
  468. *
  469. * used in leaf 'block' nodes for adding controls/attributes
  470. *
  471. * each block in each instance of the containing control structure
  472. * can have an array of the following. The show and store functions
  473. * will be filled in with the show/store function in the
  474. * low level driver.
  475. *
  476. * The 'value' field will be the actual value field used for
  477. * counting
  478. */
  479. struct edac_dev_sysfs_block_attribute {
  480. struct attribute attr;
  481. ssize_t (*show)(struct kobject *, struct attribute *, char *);
  482. ssize_t (*store)(struct kobject *, struct attribute *,
  483. const char *, size_t);
  484. struct edac_device_block *block;
  485. unsigned int value;
  486. };
  487. /* device block control structure */
  488. struct edac_device_block {
  489. struct edac_device_instance *instance; /* Up Pointer */
  490. char name[EDAC_DEVICE_NAME_LEN + 1];
  491. struct edac_device_counter counters; /* basic UE and CE counters */
  492. int nr_attribs; /* how many attributes */
  493. /* this block's attributes, could be NULL */
  494. struct edac_dev_sysfs_block_attribute *block_attributes;
  495. /* edac sysfs device control */
  496. struct kobject kobj;
  497. };
  498. /* device instance control structure */
  499. struct edac_device_instance {
  500. struct edac_device_ctl_info *ctl; /* Up pointer */
  501. char name[EDAC_DEVICE_NAME_LEN + 4];
  502. struct edac_device_counter counters; /* instance counters */
  503. u32 nr_blocks; /* how many blocks */
  504. struct edac_device_block *blocks; /* block array */
  505. /* edac sysfs device control */
  506. struct kobject kobj;
  507. };
  508. /*
  509. * Abstract edac_device control info structure
  510. *
  511. */
  512. struct edac_device_ctl_info {
  513. /* for global list of edac_device_ctl_info structs */
  514. struct list_head link;
  515. struct module *owner; /* Module owner of this control struct */
  516. int dev_idx;
  517. /* Per instance controls for this edac_device */
  518. int log_ue; /* boolean for logging UEs */
  519. int log_ce; /* boolean for logging CEs */
  520. int panic_on_ue; /* boolean for panic'ing on an UE */
  521. unsigned poll_msec; /* number of milliseconds to poll interval */
  522. unsigned long delay; /* number of jiffies for poll_msec */
  523. /* Additional top controller level attributes, but specified
  524. * by the low level driver.
  525. *
  526. * Set by the low level driver to provide attributes at the
  527. * controller level, same level as 'ue_count' and 'ce_count' above.
  528. * An array of structures, NULL terminated
  529. *
  530. * If attributes are desired, then set to array of attributes
  531. * If no attributes are desired, leave NULL
  532. */
  533. struct edac_dev_sysfs_attribute *sysfs_attributes;
  534. /* pointer to main 'edac' class in sysfs */
  535. struct sysdev_class *edac_class;
  536. /* the internal state of this controller instance */
  537. int op_state;
  538. /* work struct for this instance */
  539. struct delayed_work work;
  540. /* pointer to edac polling checking routine:
  541. * If NOT NULL: points to polling check routine
  542. * If NULL: Then assumes INTERRUPT operation, where
  543. * MC driver will receive events
  544. */
  545. void (*edac_check) (struct edac_device_ctl_info * edac_dev);
  546. struct device *dev; /* pointer to device structure */
  547. const char *mod_name; /* module name */
  548. const char *ctl_name; /* edac controller name */
  549. const char *dev_name; /* pci/platform/etc... name */
  550. void *pvt_info; /* pointer to 'private driver' info */
  551. unsigned long start_time; /* edac_device load start time (jiffies) */
  552. /* these are for safe removal of mc devices from global list while
  553. * NMI handlers may be traversing list
  554. */
  555. struct rcu_head rcu;
  556. struct completion removal_complete;
  557. /* sysfs top name under 'edac' directory
  558. * and instance name:
  559. * cpu/cpu0/...
  560. * cpu/cpu1/...
  561. * cpu/cpu2/...
  562. * ...
  563. */
  564. char name[EDAC_DEVICE_NAME_LEN + 1];
  565. /* Number of instances supported on this control structure
  566. * and the array of those instances
  567. */
  568. u32 nr_instances;
  569. struct edac_device_instance *instances;
  570. /* Event counters for the this whole EDAC Device */
  571. struct edac_device_counter counters;
  572. /* edac sysfs device control for the 'name'
  573. * device this structure controls
  574. */
  575. struct kobject kobj;
  576. };
  577. /* To get from the instance's wq to the beginning of the ctl structure */
  578. #define to_edac_mem_ctl_work(w) \
  579. container_of(w, struct mem_ctl_info, work)
  580. #define to_edac_device_ctl_work(w) \
  581. container_of(w,struct edac_device_ctl_info,work)
  582. /*
  583. * The alloc() and free() functions for the 'edac_device' control info
  584. * structure. A MC driver will allocate one of these for each edac_device
  585. * it is going to control/register with the EDAC CORE.
  586. */
  587. extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
  588. unsigned sizeof_private,
  589. char *edac_device_name, unsigned nr_instances,
  590. char *edac_block_name, unsigned nr_blocks,
  591. unsigned offset_value,
  592. struct edac_dev_sysfs_block_attribute *block_attributes,
  593. unsigned nr_attribs,
  594. int device_index);
  595. /* The offset value can be:
  596. * -1 indicating no offset value
  597. * 0 for zero-based block numbers
  598. * 1 for 1-based block number
  599. * other for other-based block number
  600. */
  601. #define BLOCK_OFFSET_VALUE_OFF ((unsigned) -1)
  602. extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);
  603. #ifdef CONFIG_PCI
  604. struct edac_pci_counter {
  605. atomic_t pe_count;
  606. atomic_t npe_count;
  607. };
  608. /*
  609. * Abstract edac_pci control info structure
  610. *
  611. */
  612. struct edac_pci_ctl_info {
  613. /* for global list of edac_pci_ctl_info structs */
  614. struct list_head link;
  615. int pci_idx;
  616. struct sysdev_class *edac_class; /* pointer to class */
  617. /* the internal state of this controller instance */
  618. int op_state;
  619. /* work struct for this instance */
  620. struct delayed_work work;
  621. /* pointer to edac polling checking routine:
  622. * If NOT NULL: points to polling check routine
  623. * If NULL: Then assumes INTERRUPT operation, where
  624. * MC driver will receive events
  625. */
  626. void (*edac_check) (struct edac_pci_ctl_info * edac_dev);
  627. struct device *dev; /* pointer to device structure */
  628. const char *mod_name; /* module name */
  629. const char *ctl_name; /* edac controller name */
  630. const char *dev_name; /* pci/platform/etc... name */
  631. void *pvt_info; /* pointer to 'private driver' info */
  632. unsigned long start_time; /* edac_pci load start time (jiffies) */
  633. /* these are for safe removal of devices from global list while
  634. * NMI handlers may be traversing list
  635. */
  636. struct rcu_head rcu;
  637. struct completion complete;
  638. /* sysfs top name under 'edac' directory
  639. * and instance name:
  640. * cpu/cpu0/...
  641. * cpu/cpu1/...
  642. * cpu/cpu2/...
  643. * ...
  644. */
  645. char name[EDAC_DEVICE_NAME_LEN + 1];
  646. /* Event counters for the this whole EDAC Device */
  647. struct edac_pci_counter counters;
  648. /* edac sysfs device control for the 'name'
  649. * device this structure controls
  650. */
  651. struct kobject kobj;
  652. struct completion kobj_complete;
  653. };
  654. #define to_edac_pci_ctl_work(w) \
  655. container_of(w, struct edac_pci_ctl_info,work)
  656. /* write all or some bits in a byte-register*/
  657. static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
  658. u8 mask)
  659. {
  660. if (mask != 0xff) {
  661. u8 buf;
  662. pci_read_config_byte(pdev, offset, &buf);
  663. value &= mask;
  664. buf &= ~mask;
  665. value |= buf;
  666. }
  667. pci_write_config_byte(pdev, offset, value);
  668. }
  669. /* write all or some bits in a word-register*/
  670. static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
  671. u16 value, u16 mask)
  672. {
  673. if (mask != 0xffff) {
  674. u16 buf;
  675. pci_read_config_word(pdev, offset, &buf);
  676. value &= mask;
  677. buf &= ~mask;
  678. value |= buf;
  679. }
  680. pci_write_config_word(pdev, offset, value);
  681. }
  682. /*
  683. * pci_write_bits32
  684. *
  685. * edac local routine to do pci_write_config_dword, but adds
  686. * a mask parameter. If mask is all ones, ignore the mask.
  687. * Otherwise utilize the mask to isolate specified bits
  688. *
  689. * write all or some bits in a dword-register
  690. */
  691. static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
  692. u32 value, u32 mask)
  693. {
  694. if (mask != 0xffffffff) {
  695. u32 buf;
  696. pci_read_config_dword(pdev, offset, &buf);
  697. value &= mask;
  698. buf &= ~mask;
  699. value |= buf;
  700. }
  701. pci_write_config_dword(pdev, offset, value);
  702. }
  703. #endif /* CONFIG_PCI */
  704. extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
  705. unsigned nr_chans, int edac_index);
  706. extern int edac_mc_add_mc(struct mem_ctl_info *mci);
  707. extern void edac_mc_free(struct mem_ctl_info *mci);
  708. extern struct mem_ctl_info *edac_mc_find(int idx);
  709. extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev);
  710. extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
  711. unsigned long page);
  712. /*
  713. * The no info errors are used when error overflows are reported.
  714. * There are a limited number of error logging registers that can
  715. * be exausted. When all registers are exhausted and an additional
  716. * error occurs then an error overflow register records that an
  717. * error occured and the type of error, but doesn't have any
  718. * further information. The ce/ue versions make for cleaner
  719. * reporting logic and function interface - reduces conditional
  720. * statement clutter and extra function arguments.
  721. */
  722. extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
  723. unsigned long page_frame_number,
  724. unsigned long offset_in_page,
  725. unsigned long syndrome, int row, int channel,
  726. const char *msg);
  727. extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
  728. const char *msg);
  729. extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
  730. unsigned long page_frame_number,
  731. unsigned long offset_in_page, int row,
  732. const char *msg);
  733. extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
  734. const char *msg);
  735. extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow,
  736. unsigned int channel0, unsigned int channel1,
  737. char *msg);
  738. extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow,
  739. unsigned int channel, char *msg);
  740. /*
  741. * edac_device APIs
  742. */
  743. extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev);
  744. extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev);
  745. extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
  746. int inst_nr, int block_nr, const char *msg);
  747. extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
  748. int inst_nr, int block_nr, const char *msg);
  749. extern int edac_device_alloc_index(void);
  750. /*
  751. * edac_pci APIs
  752. */
  753. extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt,
  754. const char *edac_pci_name);
  755. extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);
  756. extern void edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci,
  757. unsigned long value);
  758. extern int edac_pci_alloc_index(void);
  759. extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
  760. extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);
  761. extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(
  762. struct device *dev,
  763. const char *mod_name);
  764. extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
  765. extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
  766. extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);
  767. /*
  768. * edac misc APIs
  769. */
  770. extern char *edac_op_state_to_string(int op_state);
  771. #endif /* _EDAC_CORE_H_ */