/drivers/crypto/msm/inc/qce.h

https://bitbucket.org/cresqo/cm7-p500-kernel · C Header · 142 lines · 91 code · 18 blank · 33 comment · 0 complexity · 9a09ba4bcfd2e1f7da7e7f39a6ce35a8 MD5 · raw file

  1. /* Qualcomm Crypto Engine driver API
  2. *
  3. * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions are
  7. * met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above
  11. * copyright notice, this list of conditions and the following
  12. * disclaimer in the documentation and/or other materials provided
  13. * with the distribution.
  14. * * Neither the name of Code Aurora Forum, Inc. nor the names of its
  15. * contributors may be used to endorse or promote products derived
  16. * from this software without specific prior written permission.
  17. *
  18. * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  19. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  20. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
  21. * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22. * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  25. * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  26. * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  27. * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  28. * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29. */
  30. #ifndef __CRYPTO_MSM_QCE_H
  31. #define __CRYPTO_MSM_QCE_H
  32. #include <linux/types.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/crypto.h>
  35. #include <crypto/algapi.h>
  36. #include <crypto/aes.h>
  37. #include <crypto/des.h>
  38. #include <crypto/sha.h>
  39. #include <crypto/aead.h>
  40. #include <crypto/authenc.h>
  41. #include <crypto/scatterwalk.h>
  42. /* SHA digest size in bytes */
  43. #define SHA256_DIGESTSIZE 32
  44. #define SHA1_DIGESTSIZE 20
  45. /* key size in bytes */
  46. #define HMAC_KEY_SIZE (SHA1_DIGESTSIZE) /* hmac-sha1 */
  47. #define DES_KEY_SIZE 8
  48. #define TRIPLE_DES_KEY_SIZE 24
  49. #define AES128_KEY_SIZE 16
  50. #define AES192_KEY_SIZE 24
  51. #define AES256_KEY_SIZE 32
  52. #define MAX_CIPHER_KEY_SIZE AES256_KEY_SIZE
  53. /* iv length in bytes */
  54. #define AES_IV_LENGTH 16
  55. #define DES_IV_LENGTH 8
  56. #define MAX_IV_LENGTH AES_IV_LENGTH
  57. /* Maximum number of bytes per transfer */
  58. #define QCE_MAX_OPER_DATA 0x8000
  59. typedef void (*qce_comp_func_ptr_t)(void *areq,
  60. unsigned char *icv, unsigned char *iv, int ret);
  61. enum qce_cipher_alg_enum {
  62. CIPHER_ALG_DES = 0,
  63. CIPHER_ALG_3DES = 1,
  64. CIPHER_ALG_AES = 2,
  65. CIPHER_ALG_LAST
  66. };
  67. enum qce_hash_alg_enum {
  68. QCE_HASH_SHA1 = 0,
  69. QCE_HASH_SHA256 = 1,
  70. QCE_HASH_LAST
  71. };
  72. enum qce_cipher_dir_enum {
  73. QCE_ENCRYPT = 0,
  74. QCE_DECRYPT = 1,
  75. QCE_CIPHER_DIR_LAST
  76. };
  77. enum qce_cipher_mode_enum {
  78. QCE_MODE_CBC = 0,
  79. QCE_MODE_ECB = 1,
  80. QCE_MODE_CTR = 2,
  81. QCE_CIPHER_MODE_LAST
  82. };
  83. enum qce_req_op_enum {
  84. QCE_REQ_ABLK_CIPHER = 0,
  85. QCE_REQ_ABLK_CIPHER_NO_KEY = 1,
  86. QCE_REQ_AEAD = 2,
  87. QCE_REQ_LAST
  88. };
  89. struct qce_sha_req {
  90. qce_comp_func_ptr_t qce_cb;
  91. enum qce_hash_alg_enum alg;
  92. unsigned char *digest;
  93. struct scatterlist *src;
  94. uint32_t auth_data[2];
  95. bool first_blk;
  96. bool last_blk;
  97. unsigned int size;
  98. void *areq;
  99. };
  100. struct qce_req {
  101. enum qce_req_op_enum op;
  102. qce_comp_func_ptr_t qce_cb;
  103. void *areq;
  104. enum qce_cipher_alg_enum alg;
  105. enum qce_cipher_dir_enum dir;
  106. enum qce_cipher_mode_enum mode;
  107. unsigned char *authkey;
  108. unsigned int authklen;
  109. unsigned char *enckey;
  110. unsigned int encklen;
  111. unsigned char *iv;
  112. unsigned int ivsize;
  113. unsigned int cryptlen;
  114. unsigned int use_pmem;
  115. struct qcedev_pmem_info *pmem;
  116. };
  117. void *qce_open(struct platform_device *pdev, int *rc);
  118. int qce_close(void *handle);
  119. int qce_aead_req(void *handle, struct qce_req *req);
  120. int qce_ablk_cipher_req(void *handle, struct qce_req *req);
  121. int qce_ota_support(void *handle);
  122. int qce_hmac_support(void *handle);
  123. int qce_process_sha_req(void *handle, struct qce_sha_req *s_req);
  124. #endif /* __CRYPTO_MSM_QCE_H */