/drivers/atm/idt77252.c
C | 3848 lines | 3016 code | 692 blank | 140 comment | 456 complexity | e0b7d4123871e1c07ce850d5ba2a4253 MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
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1/*******************************************************************
2 *
3 * Copyright (c) 2000 ATecoM GmbH
4 *
5 * The author may be reached at ecd@atecom.com.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 *******************************************************************/
28
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/poison.h>
32#include <linux/skbuff.h>
33#include <linux/kernel.h>
34#include <linux/vmalloc.h>
35#include <linux/netdevice.h>
36#include <linux/atmdev.h>
37#include <linux/atm.h>
38#include <linux/delay.h>
39#include <linux/init.h>
40#include <linux/bitops.h>
41#include <linux/wait.h>
42#include <linux/jiffies.h>
43#include <linux/mutex.h>
44#include <linux/slab.h>
45
46#include <asm/io.h>
47#include <asm/uaccess.h>
48#include <asm/atomic.h>
49#include <asm/byteorder.h>
50
51#ifdef CONFIG_ATM_IDT77252_USE_SUNI
52#include "suni.h"
53#endif /* CONFIG_ATM_IDT77252_USE_SUNI */
54
55
56#include "idt77252.h"
57#include "idt77252_tables.h"
58
59static unsigned int vpibits = 1;
60
61
62#define ATM_IDT77252_SEND_IDLE 1
63
64
65/*
66 * Debug HACKs.
67 */
68#define DEBUG_MODULE 1
69#undef HAVE_EEPROM /* does not work, yet. */
70
71#ifdef CONFIG_ATM_IDT77252_DEBUG
72static unsigned long debug = DBG_GENERAL;
73#endif
74
75
76#define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY)
77
78
79/*
80 * SCQ Handling.
81 */
82static struct scq_info *alloc_scq(struct idt77252_dev *, int);
83static void free_scq(struct idt77252_dev *, struct scq_info *);
84static int queue_skb(struct idt77252_dev *, struct vc_map *,
85 struct sk_buff *, int oam);
86static void drain_scq(struct idt77252_dev *, struct vc_map *);
87static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *);
88static void fill_scd(struct idt77252_dev *, struct scq_info *, int);
89
90/*
91 * FBQ Handling.
92 */
93static int push_rx_skb(struct idt77252_dev *,
94 struct sk_buff *, int queue);
95static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *);
96static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *);
97static void recycle_rx_pool_skb(struct idt77252_dev *,
98 struct rx_pool *);
99static void add_rx_skb(struct idt77252_dev *, int queue,
100 unsigned int size, unsigned int count);
101
102/*
103 * RSQ Handling.
104 */
105static int init_rsq(struct idt77252_dev *);
106static void deinit_rsq(struct idt77252_dev *);
107static void idt77252_rx(struct idt77252_dev *);
108
109/*
110 * TSQ handling.
111 */
112static int init_tsq(struct idt77252_dev *);
113static void deinit_tsq(struct idt77252_dev *);
114static void idt77252_tx(struct idt77252_dev *);
115
116
117/*
118 * ATM Interface.
119 */
120static void idt77252_dev_close(struct atm_dev *dev);
121static int idt77252_open(struct atm_vcc *vcc);
122static void idt77252_close(struct atm_vcc *vcc);
123static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb);
124static int idt77252_send_oam(struct atm_vcc *vcc, void *cell,
125 int flags);
126static void idt77252_phy_put(struct atm_dev *dev, unsigned char value,
127 unsigned long addr);
128static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr);
129static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos,
130 int flags);
131static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos,
132 char *page);
133static void idt77252_softint(struct work_struct *work);
134
135
136static struct atmdev_ops idt77252_ops =
137{
138 .dev_close = idt77252_dev_close,
139 .open = idt77252_open,
140 .close = idt77252_close,
141 .send = idt77252_send,
142 .send_oam = idt77252_send_oam,
143 .phy_put = idt77252_phy_put,
144 .phy_get = idt77252_phy_get,
145 .change_qos = idt77252_change_qos,
146 .proc_read = idt77252_proc_read,
147 .owner = THIS_MODULE
148};
149
150static struct idt77252_dev *idt77252_chain = NULL;
151static unsigned int idt77252_sram_write_errors = 0;
152
153/*****************************************************************************/
154/* */
155/* I/O and Utility Bus */
156/* */
157/*****************************************************************************/
158
159static void
160waitfor_idle(struct idt77252_dev *card)
161{
162 u32 stat;
163
164 stat = readl(SAR_REG_STAT);
165 while (stat & SAR_STAT_CMDBZ)
166 stat = readl(SAR_REG_STAT);
167}
168
169static u32
170read_sram(struct idt77252_dev *card, unsigned long addr)
171{
172 unsigned long flags;
173 u32 value;
174
175 spin_lock_irqsave(&card->cmd_lock, flags);
176 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD);
177 waitfor_idle(card);
178 value = readl(SAR_REG_DR0);
179 spin_unlock_irqrestore(&card->cmd_lock, flags);
180 return value;
181}
182
183static void
184write_sram(struct idt77252_dev *card, unsigned long addr, u32 value)
185{
186 unsigned long flags;
187
188 if ((idt77252_sram_write_errors == 0) &&
189 (((addr > card->tst[0] + card->tst_size - 2) &&
190 (addr < card->tst[0] + card->tst_size)) ||
191 ((addr > card->tst[1] + card->tst_size - 2) &&
192 (addr < card->tst[1] + card->tst_size)))) {
193 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n",
194 card->name, addr, value);
195 }
196
197 spin_lock_irqsave(&card->cmd_lock, flags);
198 writel(value, SAR_REG_DR0);
199 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
200 waitfor_idle(card);
201 spin_unlock_irqrestore(&card->cmd_lock, flags);
202}
203
204static u8
205read_utility(void *dev, unsigned long ubus_addr)
206{
207 struct idt77252_dev *card = dev;
208 unsigned long flags;
209 u8 value;
210
211 if (!card) {
212 printk("Error: No such device.\n");
213 return -1;
214 }
215
216 spin_lock_irqsave(&card->cmd_lock, flags);
217 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD);
218 waitfor_idle(card);
219 value = readl(SAR_REG_DR0);
220 spin_unlock_irqrestore(&card->cmd_lock, flags);
221 return value;
222}
223
224static void
225write_utility(void *dev, unsigned long ubus_addr, u8 value)
226{
227 struct idt77252_dev *card = dev;
228 unsigned long flags;
229
230 if (!card) {
231 printk("Error: No such device.\n");
232 return;
233 }
234
235 spin_lock_irqsave(&card->cmd_lock, flags);
236 writel((u32) value, SAR_REG_DR0);
237 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD);
238 waitfor_idle(card);
239 spin_unlock_irqrestore(&card->cmd_lock, flags);
240}
241
242#ifdef HAVE_EEPROM
243static u32 rdsrtab[] =
244{
245 SAR_GP_EECS | SAR_GP_EESCLK,
246 0,
247 SAR_GP_EESCLK, /* 0 */
248 0,
249 SAR_GP_EESCLK, /* 0 */
250 0,
251 SAR_GP_EESCLK, /* 0 */
252 0,
253 SAR_GP_EESCLK, /* 0 */
254 0,
255 SAR_GP_EESCLK, /* 0 */
256 SAR_GP_EEDO,
257 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
258 0,
259 SAR_GP_EESCLK, /* 0 */
260 SAR_GP_EEDO,
261 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
262};
263
264static u32 wrentab[] =
265{
266 SAR_GP_EECS | SAR_GP_EESCLK,
267 0,
268 SAR_GP_EESCLK, /* 0 */
269 0,
270 SAR_GP_EESCLK, /* 0 */
271 0,
272 SAR_GP_EESCLK, /* 0 */
273 0,
274 SAR_GP_EESCLK, /* 0 */
275 SAR_GP_EEDO,
276 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
277 SAR_GP_EEDO,
278 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
279 0,
280 SAR_GP_EESCLK, /* 0 */
281 0,
282 SAR_GP_EESCLK /* 0 */
283};
284
285static u32 rdtab[] =
286{
287 SAR_GP_EECS | SAR_GP_EESCLK,
288 0,
289 SAR_GP_EESCLK, /* 0 */
290 0,
291 SAR_GP_EESCLK, /* 0 */
292 0,
293 SAR_GP_EESCLK, /* 0 */
294 0,
295 SAR_GP_EESCLK, /* 0 */
296 0,
297 SAR_GP_EESCLK, /* 0 */
298 0,
299 SAR_GP_EESCLK, /* 0 */
300 SAR_GP_EEDO,
301 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
302 SAR_GP_EEDO,
303 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
304};
305
306static u32 wrtab[] =
307{
308 SAR_GP_EECS | SAR_GP_EESCLK,
309 0,
310 SAR_GP_EESCLK, /* 0 */
311 0,
312 SAR_GP_EESCLK, /* 0 */
313 0,
314 SAR_GP_EESCLK, /* 0 */
315 0,
316 SAR_GP_EESCLK, /* 0 */
317 0,
318 SAR_GP_EESCLK, /* 0 */
319 0,
320 SAR_GP_EESCLK, /* 0 */
321 SAR_GP_EEDO,
322 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
323 0,
324 SAR_GP_EESCLK /* 0 */
325};
326
327static u32 clktab[] =
328{
329 0,
330 SAR_GP_EESCLK,
331 0,
332 SAR_GP_EESCLK,
333 0,
334 SAR_GP_EESCLK,
335 0,
336 SAR_GP_EESCLK,
337 0,
338 SAR_GP_EESCLK,
339 0,
340 SAR_GP_EESCLK,
341 0,
342 SAR_GP_EESCLK,
343 0,
344 SAR_GP_EESCLK,
345 0
346};
347
348static u32
349idt77252_read_gp(struct idt77252_dev *card)
350{
351 u32 gp;
352
353 gp = readl(SAR_REG_GP);
354#if 0
355 printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0");
356#endif
357 return gp;
358}
359
360static void
361idt77252_write_gp(struct idt77252_dev *card, u32 value)
362{
363 unsigned long flags;
364
365#if 0
366 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS",
367 value & SAR_GP_EESCLK ? "HIGH" : "LOW ",
368 value & SAR_GP_EEDO ? "1" : "0");
369#endif
370
371 spin_lock_irqsave(&card->cmd_lock, flags);
372 waitfor_idle(card);
373 writel(value, SAR_REG_GP);
374 spin_unlock_irqrestore(&card->cmd_lock, flags);
375}
376
377static u8
378idt77252_eeprom_read_status(struct idt77252_dev *card)
379{
380 u8 byte;
381 u32 gp;
382 int i, j;
383
384 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
385
386 for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) {
387 idt77252_write_gp(card, gp | rdsrtab[i]);
388 udelay(5);
389 }
390 idt77252_write_gp(card, gp | SAR_GP_EECS);
391 udelay(5);
392
393 byte = 0;
394 for (i = 0, j = 0; i < 8; i++) {
395 byte <<= 1;
396
397 idt77252_write_gp(card, gp | clktab[j++]);
398 udelay(5);
399
400 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
401
402 idt77252_write_gp(card, gp | clktab[j++]);
403 udelay(5);
404 }
405 idt77252_write_gp(card, gp | SAR_GP_EECS);
406 udelay(5);
407
408 return byte;
409}
410
411static u8
412idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset)
413{
414 u8 byte;
415 u32 gp;
416 int i, j;
417
418 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
419
420 for (i = 0; i < ARRAY_SIZE(rdtab); i++) {
421 idt77252_write_gp(card, gp | rdtab[i]);
422 udelay(5);
423 }
424 idt77252_write_gp(card, gp | SAR_GP_EECS);
425 udelay(5);
426
427 for (i = 0, j = 0; i < 8; i++) {
428 idt77252_write_gp(card, gp | clktab[j++] |
429 (offset & 1 ? SAR_GP_EEDO : 0));
430 udelay(5);
431
432 idt77252_write_gp(card, gp | clktab[j++] |
433 (offset & 1 ? SAR_GP_EEDO : 0));
434 udelay(5);
435
436 offset >>= 1;
437 }
438 idt77252_write_gp(card, gp | SAR_GP_EECS);
439 udelay(5);
440
441 byte = 0;
442 for (i = 0, j = 0; i < 8; i++) {
443 byte <<= 1;
444
445 idt77252_write_gp(card, gp | clktab[j++]);
446 udelay(5);
447
448 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
449
450 idt77252_write_gp(card, gp | clktab[j++]);
451 udelay(5);
452 }
453 idt77252_write_gp(card, gp | SAR_GP_EECS);
454 udelay(5);
455
456 return byte;
457}
458
459static void
460idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data)
461{
462 u32 gp;
463 int i, j;
464
465 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
466
467 for (i = 0; i < ARRAY_SIZE(wrentab); i++) {
468 idt77252_write_gp(card, gp | wrentab[i]);
469 udelay(5);
470 }
471 idt77252_write_gp(card, gp | SAR_GP_EECS);
472 udelay(5);
473
474 for (i = 0; i < ARRAY_SIZE(wrtab); i++) {
475 idt77252_write_gp(card, gp | wrtab[i]);
476 udelay(5);
477 }
478 idt77252_write_gp(card, gp | SAR_GP_EECS);
479 udelay(5);
480
481 for (i = 0, j = 0; i < 8; i++) {
482 idt77252_write_gp(card, gp | clktab[j++] |
483 (offset & 1 ? SAR_GP_EEDO : 0));
484 udelay(5);
485
486 idt77252_write_gp(card, gp | clktab[j++] |
487 (offset & 1 ? SAR_GP_EEDO : 0));
488 udelay(5);
489
490 offset >>= 1;
491 }
492 idt77252_write_gp(card, gp | SAR_GP_EECS);
493 udelay(5);
494
495 for (i = 0, j = 0; i < 8; i++) {
496 idt77252_write_gp(card, gp | clktab[j++] |
497 (data & 1 ? SAR_GP_EEDO : 0));
498 udelay(5);
499
500 idt77252_write_gp(card, gp | clktab[j++] |
501 (data & 1 ? SAR_GP_EEDO : 0));
502 udelay(5);
503
504 data >>= 1;
505 }
506 idt77252_write_gp(card, gp | SAR_GP_EECS);
507 udelay(5);
508}
509
510static void
511idt77252_eeprom_init(struct idt77252_dev *card)
512{
513 u32 gp;
514
515 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
516
517 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
518 udelay(5);
519 idt77252_write_gp(card, gp | SAR_GP_EECS);
520 udelay(5);
521 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
522 udelay(5);
523 idt77252_write_gp(card, gp | SAR_GP_EECS);
524 udelay(5);
525}
526#endif /* HAVE_EEPROM */
527
528
529#ifdef CONFIG_ATM_IDT77252_DEBUG
530static void
531dump_tct(struct idt77252_dev *card, int index)
532{
533 unsigned long tct;
534 int i;
535
536 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE);
537
538 printk("%s: TCT %x:", card->name, index);
539 for (i = 0; i < 8; i++) {
540 printk(" %08x", read_sram(card, tct + i));
541 }
542 printk("\n");
543}
544
545static void
546idt77252_tx_dump(struct idt77252_dev *card)
547{
548 struct atm_vcc *vcc;
549 struct vc_map *vc;
550 int i;
551
552 printk("%s\n", __func__);
553 for (i = 0; i < card->tct_size; i++) {
554 vc = card->vcs[i];
555 if (!vc)
556 continue;
557
558 vcc = NULL;
559 if (vc->rx_vcc)
560 vcc = vc->rx_vcc;
561 else if (vc->tx_vcc)
562 vcc = vc->tx_vcc;
563
564 if (!vcc)
565 continue;
566
567 printk("%s: Connection %d:\n", card->name, vc->index);
568 dump_tct(card, vc->index);
569 }
570}
571#endif
572
573
574/*****************************************************************************/
575/* */
576/* SCQ Handling */
577/* */
578/*****************************************************************************/
579
580static int
581sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue)
582{
583 struct sb_pool *pool = &card->sbpool[queue];
584 int index;
585
586 index = pool->index;
587 while (pool->skb[index]) {
588 index = (index + 1) & FBQ_MASK;
589 if (index == pool->index)
590 return -ENOBUFS;
591 }
592
593 pool->skb[index] = skb;
594 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index);
595
596 pool->index = (index + 1) & FBQ_MASK;
597 return 0;
598}
599
600static void
601sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb)
602{
603 unsigned int queue, index;
604 u32 handle;
605
606 handle = IDT77252_PRV_POOL(skb);
607
608 queue = POOL_QUEUE(handle);
609 if (queue > 3)
610 return;
611
612 index = POOL_INDEX(handle);
613 if (index > FBQ_SIZE - 1)
614 return;
615
616 card->sbpool[queue].skb[index] = NULL;
617}
618
619static struct sk_buff *
620sb_pool_skb(struct idt77252_dev *card, u32 handle)
621{
622 unsigned int queue, index;
623
624 queue = POOL_QUEUE(handle);
625 if (queue > 3)
626 return NULL;
627
628 index = POOL_INDEX(handle);
629 if (index > FBQ_SIZE - 1)
630 return NULL;
631
632 return card->sbpool[queue].skb[index];
633}
634
635static struct scq_info *
636alloc_scq(struct idt77252_dev *card, int class)
637{
638 struct scq_info *scq;
639
640 scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL);
641 if (!scq)
642 return NULL;
643 scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE,
644 &scq->paddr);
645 if (scq->base == NULL) {
646 kfree(scq);
647 return NULL;
648 }
649 memset(scq->base, 0, SCQ_SIZE);
650
651 scq->next = scq->base;
652 scq->last = scq->base + (SCQ_ENTRIES - 1);
653 atomic_set(&scq->used, 0);
654
655 spin_lock_init(&scq->lock);
656 spin_lock_init(&scq->skblock);
657
658 skb_queue_head_init(&scq->transmit);
659 skb_queue_head_init(&scq->pending);
660
661 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n",
662 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr);
663
664 return scq;
665}
666
667static void
668free_scq(struct idt77252_dev *card, struct scq_info *scq)
669{
670 struct sk_buff *skb;
671 struct atm_vcc *vcc;
672
673 pci_free_consistent(card->pcidev, SCQ_SIZE,
674 scq->base, scq->paddr);
675
676 while ((skb = skb_dequeue(&scq->transmit))) {
677 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
678 skb->len, PCI_DMA_TODEVICE);
679
680 vcc = ATM_SKB(skb)->vcc;
681 if (vcc->pop)
682 vcc->pop(vcc, skb);
683 else
684 dev_kfree_skb(skb);
685 }
686
687 while ((skb = skb_dequeue(&scq->pending))) {
688 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
689 skb->len, PCI_DMA_TODEVICE);
690
691 vcc = ATM_SKB(skb)->vcc;
692 if (vcc->pop)
693 vcc->pop(vcc, skb);
694 else
695 dev_kfree_skb(skb);
696 }
697
698 kfree(scq);
699}
700
701
702static int
703push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb)
704{
705 struct scq_info *scq = vc->scq;
706 unsigned long flags;
707 struct scqe *tbd;
708 int entries;
709
710 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next);
711
712 atomic_inc(&scq->used);
713 entries = atomic_read(&scq->used);
714 if (entries > (SCQ_ENTRIES - 1)) {
715 atomic_dec(&scq->used);
716 goto out;
717 }
718
719 skb_queue_tail(&scq->transmit, skb);
720
721 spin_lock_irqsave(&vc->lock, flags);
722 if (vc->estimator) {
723 struct atm_vcc *vcc = vc->tx_vcc;
724 struct sock *sk = sk_atm(vcc);
725
726 vc->estimator->cells += (skb->len + 47) / 48;
727 if (atomic_read(&sk->sk_wmem_alloc) >
728 (sk->sk_sndbuf >> 1)) {
729 u32 cps = vc->estimator->maxcps;
730
731 vc->estimator->cps = cps;
732 vc->estimator->avcps = cps << 5;
733 if (vc->lacr < vc->init_er) {
734 vc->lacr = vc->init_er;
735 writel(TCMDQ_LACR | (vc->lacr << 16) |
736 vc->index, SAR_REG_TCMDQ);
737 }
738 }
739 }
740 spin_unlock_irqrestore(&vc->lock, flags);
741
742 tbd = &IDT77252_PRV_TBD(skb);
743
744 spin_lock_irqsave(&scq->lock, flags);
745 scq->next->word_1 = cpu_to_le32(tbd->word_1 |
746 SAR_TBD_TSIF | SAR_TBD_GTSI);
747 scq->next->word_2 = cpu_to_le32(tbd->word_2);
748 scq->next->word_3 = cpu_to_le32(tbd->word_3);
749 scq->next->word_4 = cpu_to_le32(tbd->word_4);
750
751 if (scq->next == scq->last)
752 scq->next = scq->base;
753 else
754 scq->next++;
755
756 write_sram(card, scq->scd,
757 scq->paddr +
758 (u32)((unsigned long)scq->next - (unsigned long)scq->base));
759 spin_unlock_irqrestore(&scq->lock, flags);
760
761 scq->trans_start = jiffies;
762
763 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) {
764 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index,
765 SAR_REG_TCMDQ);
766 }
767
768 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used));
769
770 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n",
771 card->name, atomic_read(&scq->used),
772 read_sram(card, scq->scd + 1), scq->next);
773
774 return 0;
775
776out:
777 if (time_after(jiffies, scq->trans_start + HZ)) {
778 printk("%s: Error pushing TBD for %d.%d\n",
779 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci);
780#ifdef CONFIG_ATM_IDT77252_DEBUG
781 idt77252_tx_dump(card);
782#endif
783 scq->trans_start = jiffies;
784 }
785
786 return -ENOBUFS;
787}
788
789
790static void
791drain_scq(struct idt77252_dev *card, struct vc_map *vc)
792{
793 struct scq_info *scq = vc->scq;
794 struct sk_buff *skb;
795 struct atm_vcc *vcc;
796
797 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n",
798 card->name, atomic_read(&scq->used), scq->next);
799
800 skb = skb_dequeue(&scq->transmit);
801 if (skb) {
802 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb);
803
804 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
805 skb->len, PCI_DMA_TODEVICE);
806
807 vcc = ATM_SKB(skb)->vcc;
808
809 if (vcc->pop)
810 vcc->pop(vcc, skb);
811 else
812 dev_kfree_skb(skb);
813
814 atomic_inc(&vcc->stats->tx);
815 }
816
817 atomic_dec(&scq->used);
818
819 spin_lock(&scq->skblock);
820 while ((skb = skb_dequeue(&scq->pending))) {
821 if (push_on_scq(card, vc, skb)) {
822 skb_queue_head(&vc->scq->pending, skb);
823 break;
824 }
825 }
826 spin_unlock(&scq->skblock);
827}
828
829static int
830queue_skb(struct idt77252_dev *card, struct vc_map *vc,
831 struct sk_buff *skb, int oam)
832{
833 struct atm_vcc *vcc;
834 struct scqe *tbd;
835 unsigned long flags;
836 int error;
837 int aal;
838
839 if (skb->len == 0) {
840 printk("%s: invalid skb->len (%d)\n", card->name, skb->len);
841 return -EINVAL;
842 }
843
844 TXPRINTK("%s: Sending %d bytes of data.\n",
845 card->name, skb->len);
846
847 tbd = &IDT77252_PRV_TBD(skb);
848 vcc = ATM_SKB(skb)->vcc;
849
850 IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data,
851 skb->len, PCI_DMA_TODEVICE);
852
853 error = -EINVAL;
854
855 if (oam) {
856 if (skb->len != 52)
857 goto errout;
858
859 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU;
860 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
861 tbd->word_3 = 0x00000000;
862 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
863 (skb->data[2] << 8) | (skb->data[3] << 0);
864
865 if (test_bit(VCF_RSV, &vc->flags))
866 vc = card->vcs[0];
867
868 goto done;
869 }
870
871 if (test_bit(VCF_RSV, &vc->flags)) {
872 printk("%s: Trying to transmit on reserved VC\n", card->name);
873 goto errout;
874 }
875
876 aal = vcc->qos.aal;
877
878 switch (aal) {
879 case ATM_AAL0:
880 case ATM_AAL34:
881 if (skb->len > 52)
882 goto errout;
883
884 if (aal == ATM_AAL0)
885 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 |
886 ATM_CELL_PAYLOAD;
887 else
888 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 |
889 ATM_CELL_PAYLOAD;
890
891 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
892 tbd->word_3 = 0x00000000;
893 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
894 (skb->data[2] << 8) | (skb->data[3] << 0);
895 break;
896
897 case ATM_AAL5:
898 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len;
899 tbd->word_2 = IDT77252_PRV_PADDR(skb);
900 tbd->word_3 = skb->len;
901 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) |
902 (vcc->vci << SAR_TBD_VCI_SHIFT);
903 break;
904
905 case ATM_AAL1:
906 case ATM_AAL2:
907 default:
908 printk("%s: Traffic type not supported.\n", card->name);
909 error = -EPROTONOSUPPORT;
910 goto errout;
911 }
912
913done:
914 spin_lock_irqsave(&vc->scq->skblock, flags);
915 skb_queue_tail(&vc->scq->pending, skb);
916
917 while ((skb = skb_dequeue(&vc->scq->pending))) {
918 if (push_on_scq(card, vc, skb)) {
919 skb_queue_head(&vc->scq->pending, skb);
920 break;
921 }
922 }
923 spin_unlock_irqrestore(&vc->scq->skblock, flags);
924
925 return 0;
926
927errout:
928 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
929 skb->len, PCI_DMA_TODEVICE);
930 return error;
931}
932
933static unsigned long
934get_free_scd(struct idt77252_dev *card, struct vc_map *vc)
935{
936 int i;
937
938 for (i = 0; i < card->scd_size; i++) {
939 if (!card->scd2vc[i]) {
940 card->scd2vc[i] = vc;
941 vc->scd_index = i;
942 return card->scd_base + i * SAR_SRAM_SCD_SIZE;
943 }
944 }
945 return 0;
946}
947
948static void
949fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
950{
951 write_sram(card, scq->scd, scq->paddr);
952 write_sram(card, scq->scd + 1, 0x00000000);
953 write_sram(card, scq->scd + 2, 0xffffffff);
954 write_sram(card, scq->scd + 3, 0x00000000);
955}
956
957static void
958clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
959{
960 return;
961}
962
963/*****************************************************************************/
964/* */
965/* RSQ Handling */
966/* */
967/*****************************************************************************/
968
969static int
970init_rsq(struct idt77252_dev *card)
971{
972 struct rsq_entry *rsqe;
973
974 card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
975 &card->rsq.paddr);
976 if (card->rsq.base == NULL) {
977 printk("%s: can't allocate RSQ.\n", card->name);
978 return -1;
979 }
980 memset(card->rsq.base, 0, RSQSIZE);
981
982 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1;
983 card->rsq.next = card->rsq.last;
984 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++)
985 rsqe->word_4 = 0;
986
987 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base,
988 SAR_REG_RSQH);
989 writel(card->rsq.paddr, SAR_REG_RSQB);
990
991 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name,
992 (unsigned long) card->rsq.base,
993 readl(SAR_REG_RSQB));
994 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n",
995 card->name,
996 readl(SAR_REG_RSQH),
997 readl(SAR_REG_RSQB),
998 readl(SAR_REG_RSQT));
999
1000 return 0;
1001}
1002
1003static void
1004deinit_rsq(struct idt77252_dev *card)
1005{
1006 pci_free_consistent(card->pcidev, RSQSIZE,
1007 card->rsq.base, card->rsq.paddr);
1008}
1009
1010static void
1011dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)
1012{
1013 struct atm_vcc *vcc;
1014 struct sk_buff *skb;
1015 struct rx_pool *rpp;
1016 struct vc_map *vc;
1017 u32 header, vpi, vci;
1018 u32 stat;
1019 int i;
1020
1021 stat = le32_to_cpu(rsqe->word_4);
1022
1023 if (stat & SAR_RSQE_IDLE) {
1024 RXPRINTK("%s: message about inactive connection.\n",
1025 card->name);
1026 return;
1027 }
1028
1029 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2));
1030 if (skb == NULL) {
1031 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n",
1032 card->name, __func__,
1033 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2),
1034 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4));
1035 return;
1036 }
1037
1038 header = le32_to_cpu(rsqe->word_1);
1039 vpi = (header >> 16) & 0x00ff;
1040 vci = (header >> 0) & 0xffff;
1041
1042 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n",
1043 card->name, vpi, vci, skb, skb->data);
1044
1045 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) {
1046 printk("%s: SDU received for out-of-range vc %u.%u\n",
1047 card->name, vpi, vci);
1048 recycle_rx_skb(card, skb);
1049 return;
1050 }
1051
1052 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1053 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1054 printk("%s: SDU received on non RX vc %u.%u\n",
1055 card->name, vpi, vci);
1056 recycle_rx_skb(card, skb);
1057 return;
1058 }
1059
1060 vcc = vc->rx_vcc;
1061
1062 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(skb),
1063 skb_end_pointer(skb) - skb->data,
1064 PCI_DMA_FROMDEVICE);
1065
1066 if ((vcc->qos.aal == ATM_AAL0) ||
1067 (vcc->qos.aal == ATM_AAL34)) {
1068 struct sk_buff *sb;
1069 unsigned char *cell;
1070 u32 aal0;
1071
1072 cell = skb->data;
1073 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) {
1074 if ((sb = dev_alloc_skb(64)) == NULL) {
1075 printk("%s: Can't allocate buffers for aal0.\n",
1076 card->name);
1077 atomic_add(i, &vcc->stats->rx_drop);
1078 break;
1079 }
1080 if (!atm_charge(vcc, sb->truesize)) {
1081 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n",
1082 card->name);
1083 atomic_add(i - 1, &vcc->stats->rx_drop);
1084 dev_kfree_skb(sb);
1085 break;
1086 }
1087 aal0 = (vpi << ATM_HDR_VPI_SHIFT) |
1088 (vci << ATM_HDR_VCI_SHIFT);
1089 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0;
1090 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0;
1091
1092 *((u32 *) sb->data) = aal0;
1093 skb_put(sb, sizeof(u32));
1094 memcpy(skb_put(sb, ATM_CELL_PAYLOAD),
1095 cell, ATM_CELL_PAYLOAD);
1096
1097 ATM_SKB(sb)->vcc = vcc;
1098 __net_timestamp(sb);
1099 vcc->push(vcc, sb);
1100 atomic_inc(&vcc->stats->rx);
1101
1102 cell += ATM_CELL_PAYLOAD;
1103 }
1104
1105 recycle_rx_skb(card, skb);
1106 return;
1107 }
1108 if (vcc->qos.aal != ATM_AAL5) {
1109 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n",
1110 card->name, vcc->qos.aal);
1111 recycle_rx_skb(card, skb);
1112 return;
1113 }
1114 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD;
1115
1116 rpp = &vc->rcv.rx_pool;
1117
1118 __skb_queue_tail(&rpp->queue, skb);
1119 rpp->len += skb->len;
1120
1121 if (stat & SAR_RSQE_EPDU) {
1122 unsigned char *l1l2;
1123 unsigned int len;
1124
1125 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6);
1126
1127 len = (l1l2[0] << 8) | l1l2[1];
1128 len = len ? len : 0x10000;
1129
1130 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len);
1131
1132 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) {
1133 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. "
1134 "(CDC: %08x)\n",
1135 card->name, len, rpp->len, readl(SAR_REG_CDC));
1136 recycle_rx_pool_skb(card, rpp);
1137 atomic_inc(&vcc->stats->rx_err);
1138 return;
1139 }
1140 if (stat & SAR_RSQE_CRC) {
1141 RXPRINTK("%s: AAL5 CRC error.\n", card->name);
1142 recycle_rx_pool_skb(card, rpp);
1143 atomic_inc(&vcc->stats->rx_err);
1144 return;
1145 }
1146 if (skb_queue_len(&rpp->queue) > 1) {
1147 struct sk_buff *sb;
1148
1149 skb = dev_alloc_skb(rpp->len);
1150 if (!skb) {
1151 RXPRINTK("%s: Can't alloc RX skb.\n",
1152 card->name);
1153 recycle_rx_pool_skb(card, rpp);
1154 atomic_inc(&vcc->stats->rx_err);
1155 return;
1156 }
1157 if (!atm_charge(vcc, skb->truesize)) {
1158 recycle_rx_pool_skb(card, rpp);
1159 dev_kfree_skb(skb);
1160 return;
1161 }
1162 skb_queue_walk(&rpp->queue, sb)
1163 memcpy(skb_put(skb, sb->len),
1164 sb->data, sb->len);
1165
1166 recycle_rx_pool_skb(card, rpp);
1167
1168 skb_trim(skb, len);
1169 ATM_SKB(skb)->vcc = vcc;
1170 __net_timestamp(skb);
1171
1172 vcc->push(vcc, skb);
1173 atomic_inc(&vcc->stats->rx);
1174
1175 return;
1176 }
1177
1178 flush_rx_pool(card, rpp);
1179
1180 if (!atm_charge(vcc, skb->truesize)) {
1181 recycle_rx_skb(card, skb);
1182 return;
1183 }
1184
1185 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1186 skb_end_pointer(skb) - skb->data,
1187 PCI_DMA_FROMDEVICE);
1188 sb_pool_remove(card, skb);
1189
1190 skb_trim(skb, len);
1191 ATM_SKB(skb)->vcc = vcc;
1192 __net_timestamp(skb);
1193
1194 vcc->push(vcc, skb);
1195 atomic_inc(&vcc->stats->rx);
1196
1197 if (skb->truesize > SAR_FB_SIZE_3)
1198 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1);
1199 else if (skb->truesize > SAR_FB_SIZE_2)
1200 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1);
1201 else if (skb->truesize > SAR_FB_SIZE_1)
1202 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1);
1203 else
1204 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1);
1205 return;
1206 }
1207}
1208
1209static void
1210idt77252_rx(struct idt77252_dev *card)
1211{
1212 struct rsq_entry *rsqe;
1213
1214 if (card->rsq.next == card->rsq.last)
1215 rsqe = card->rsq.base;
1216 else
1217 rsqe = card->rsq.next + 1;
1218
1219 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) {
1220 RXPRINTK("%s: no entry in RSQ.\n", card->name);
1221 return;
1222 }
1223
1224 do {
1225 dequeue_rx(card, rsqe);
1226 rsqe->word_4 = 0;
1227 card->rsq.next = rsqe;
1228 if (card->rsq.next == card->rsq.last)
1229 rsqe = card->rsq.base;
1230 else
1231 rsqe = card->rsq.next + 1;
1232 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID);
1233
1234 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base,
1235 SAR_REG_RSQH);
1236}
1237
1238static void
1239idt77252_rx_raw(struct idt77252_dev *card)
1240{
1241 struct sk_buff *queue;
1242 u32 head, tail;
1243 struct atm_vcc *vcc;
1244 struct vc_map *vc;
1245 struct sk_buff *sb;
1246
1247 if (card->raw_cell_head == NULL) {
1248 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1));
1249 card->raw_cell_head = sb_pool_skb(card, handle);
1250 }
1251
1252 queue = card->raw_cell_head;
1253 if (!queue)
1254 return;
1255
1256 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16);
1257 tail = readl(SAR_REG_RAWCT);
1258
1259 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(queue),
1260 skb_end_pointer(queue) - queue->head - 16,
1261 PCI_DMA_FROMDEVICE);
1262
1263 while (head != tail) {
1264 unsigned int vpi, vci, pti;
1265 u32 header;
1266
1267 header = le32_to_cpu(*(u32 *) &queue->data[0]);
1268
1269 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;
1270 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;
1271 pti = (header & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT;
1272
1273#ifdef CONFIG_ATM_IDT77252_DEBUG
1274 if (debug & DBG_RAW_CELL) {
1275 int i;
1276
1277 printk("%s: raw cell %x.%02x.%04x.%x.%x\n",
1278 card->name, (header >> 28) & 0x000f,
1279 (header >> 20) & 0x00ff,
1280 (header >> 4) & 0xffff,
1281 (header >> 1) & 0x0007,
1282 (header >> 0) & 0x0001);
1283 for (i = 16; i < 64; i++)
1284 printk(" %02x", queue->data[i]);
1285 printk("\n");
1286 }
1287#endif
1288
1289 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) {
1290 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n",
1291 card->name, vpi, vci);
1292 goto drop;
1293 }
1294
1295 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1296 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1297 RPRINTK("%s: SDU received on non RX vc %u.%u\n",
1298 card->name, vpi, vci);
1299 goto drop;
1300 }
1301
1302 vcc = vc->rx_vcc;
1303
1304 if (vcc->qos.aal != ATM_AAL0) {
1305 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n",
1306 card->name, vpi, vci);
1307 atomic_inc(&vcc->stats->rx_drop);
1308 goto drop;
1309 }
1310
1311 if ((sb = dev_alloc_skb(64)) == NULL) {
1312 printk("%s: Can't allocate buffers for AAL0.\n",
1313 card->name);
1314 atomic_inc(&vcc->stats->rx_err);
1315 goto drop;
1316 }
1317
1318 if (!atm_charge(vcc, sb->truesize)) {
1319 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n",
1320 card->name);
1321 dev_kfree_skb(sb);
1322 goto drop;
1323 }
1324
1325 *((u32 *) sb->data) = header;
1326 skb_put(sb, sizeof(u32));
1327 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]),
1328 ATM_CELL_PAYLOAD);
1329
1330 ATM_SKB(sb)->vcc = vcc;
1331 __net_timestamp(sb);
1332 vcc->push(vcc, sb);
1333 atomic_inc(&vcc->stats->rx);
1334
1335drop:
1336 skb_pull(queue, 64);
1337
1338 head = IDT77252_PRV_PADDR(queue)
1339 + (queue->data - queue->head - 16);
1340
1341 if (queue->len < 128) {
1342 struct sk_buff *next;
1343 u32 handle;
1344
1345 head = le32_to_cpu(*(u32 *) &queue->data[0]);
1346 handle = le32_to_cpu(*(u32 *) &queue->data[4]);
1347
1348 next = sb_pool_skb(card, handle);
1349 recycle_rx_skb(card, queue);
1350
1351 if (next) {
1352 card->raw_cell_head = next;
1353 queue = card->raw_cell_head;
1354 pci_dma_sync_single_for_cpu(card->pcidev,
1355 IDT77252_PRV_PADDR(queue),
1356 (skb_end_pointer(queue) -
1357 queue->data),
1358 PCI_DMA_FROMDEVICE);
1359 } else {
1360 card->raw_cell_head = NULL;
1361 printk("%s: raw cell queue overrun\n",
1362 card->name);
1363 break;
1364 }
1365 }
1366 }
1367}
1368
1369
1370/*****************************************************************************/
1371/* */
1372/* TSQ Handling */
1373/* */
1374/*****************************************************************************/
1375
1376static int
1377init_tsq(struct idt77252_dev *card)
1378{
1379 struct tsq_entry *tsqe;
1380
1381 card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
1382 &card->tsq.paddr);
1383 if (card->tsq.base == NULL) {
1384 printk("%s: can't allocate TSQ.\n", card->name);
1385 return -1;
1386 }
1387 memset(card->tsq.base, 0, TSQSIZE);
1388
1389 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1;
1390 card->tsq.next = card->tsq.last;
1391 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++)
1392 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1393
1394 writel(card->tsq.paddr, SAR_REG_TSQB);
1395 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base,
1396 SAR_REG_TSQH);
1397
1398 return 0;
1399}
1400
1401static void
1402deinit_tsq(struct idt77252_dev *card)
1403{
1404 pci_free_consistent(card->pcidev, TSQSIZE,
1405 card->tsq.base, card->tsq.paddr);
1406}
1407
1408static void
1409idt77252_tx(struct idt77252_dev *card)
1410{
1411 struct tsq_entry *tsqe;
1412 unsigned int vpi, vci;
1413 struct vc_map *vc;
1414 u32 conn, stat;
1415
1416 if (card->tsq.next == card->tsq.last)
1417 tsqe = card->tsq.base;
1418 else
1419 tsqe = card->tsq.next + 1;
1420
1421 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe,
1422 card->tsq.base, card->tsq.next, card->tsq.last);
1423 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n",
1424 readl(SAR_REG_TSQB),
1425 readl(SAR_REG_TSQT),
1426 readl(SAR_REG_TSQH));
1427
1428 stat = le32_to_cpu(tsqe->word_2);
1429
1430 if (stat & SAR_TSQE_INVALID)
1431 return;
1432
1433 do {
1434 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe,
1435 le32_to_cpu(tsqe->word_1),
1436 le32_to_cpu(tsqe->word_2));
1437
1438 switch (stat & SAR_TSQE_TYPE) {
1439 case SAR_TSQE_TYPE_TIMER:
1440 TXPRINTK("%s: Timer RollOver detected.\n", card->name);
1441 break;
1442
1443 case SAR_TSQE_TYPE_IDLE:
1444
1445 conn = le32_to_cpu(tsqe->word_1);
1446
1447 if (SAR_TSQE_TAG(stat) == 0x10) {
1448#ifdef NOTDEF
1449 printk("%s: Connection %d halted.\n",
1450 card->name,
1451 le32_to_cpu(tsqe->word_1) & 0x1fff);
1452#endif
1453 break;
1454 }
1455
1456 vc = card->vcs[conn & 0x1fff];
1457 if (!vc) {
1458 printk("%s: could not find VC from conn %d\n",
1459 card->name, conn & 0x1fff);
1460 break;
1461 }
1462
1463 printk("%s: Connection %d IDLE.\n",
1464 card->name, vc->index);
1465
1466 set_bit(VCF_IDLE, &vc->flags);
1467 break;
1468
1469 case SAR_TSQE_TYPE_TSR:
1470
1471 conn = le32_to_cpu(tsqe->word_1);
1472
1473 vc = card->vcs[conn & 0x1fff];
1474 if (!vc) {
1475 printk("%s: no VC at index %d\n",
1476 card->name,
1477 le32_to_cpu(tsqe->word_1) & 0x1fff);
1478 break;
1479 }
1480
1481 drain_scq(card, vc);
1482 break;
1483
1484 case SAR_TSQE_TYPE_TBD_COMP:
1485
1486 conn = le32_to_cpu(tsqe->word_1);
1487
1488 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff;
1489 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff;
1490
1491 if (vpi >= (1 << card->vpibits) ||
1492 vci >= (1 << card->vcibits)) {
1493 printk("%s: TBD complete: "
1494 "out of range VPI.VCI %u.%u\n",
1495 card->name, vpi, vci);
1496 break;
1497 }
1498
1499 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1500 if (!vc) {
1501 printk("%s: TBD complete: "
1502 "no VC at VPI.VCI %u.%u\n",
1503 card->name, vpi, vci);
1504 break;
1505 }
1506
1507 drain_scq(card, vc);
1508 break;
1509 }
1510
1511 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1512
1513 card->tsq.next = tsqe;
1514 if (card->tsq.next == card->tsq.last)
1515 tsqe = card->tsq.base;
1516 else
1517 tsqe = card->tsq.next + 1;
1518
1519 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe,
1520 card->tsq.base, card->tsq.next, card->tsq.last);
1521
1522 stat = le32_to_cpu(tsqe->word_2);
1523
1524 } while (!(stat & SAR_TSQE_INVALID));
1525
1526 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base,
1527 SAR_REG_TSQH);
1528
1529 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n",
1530 card->index, readl(SAR_REG_TSQH),
1531 readl(SAR_REG_TSQT), card->tsq.next);
1532}
1533
1534
1535static void
1536tst_timer(unsigned long data)
1537{
1538 struct idt77252_dev *card = (struct idt77252_dev *)data;
1539 unsigned long base, idle, jump;
1540 unsigned long flags;
1541 u32 pc;
1542 int e;
1543
1544 spin_lock_irqsave(&card->tst_lock, flags);
1545
1546 base = card->tst[card->tst_index];
1547 idle = card->tst[card->tst_index ^ 1];
1548
1549 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) {
1550 jump = base + card->tst_size - 2;
1551
1552 pc = readl(SAR_REG_NOW) >> 2;
1553 if ((pc ^ idle) & ~(card->tst_size - 1)) {
1554 mod_timer(&card->tst_timer, jiffies + 1);
1555 goto out;
1556 }
1557
1558 clear_bit(TST_SWITCH_WAIT, &card->tst_state);
1559
1560 card->tst_index ^= 1;
1561 write_sram(card, jump, TSTE_OPC_JMP | (base << 2));
1562
1563 base = card->tst[card->tst_index];
1564 idle = card->tst[card->tst_index ^ 1];
1565
1566 for (e = 0; e < card->tst_size - 2; e++) {
1567 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) {
1568 write_sram(card, idle + e,
1569 card->soft_tst[e].tste & TSTE_MASK);
1570 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE);
1571 }
1572 }
1573 }
1574
1575 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) {
1576
1577 for (e = 0; e < card->tst_size - 2; e++) {
1578 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) {
1579 write_sram(card, idle + e,
1580 card->soft_tst[e].tste & TSTE_MASK);
1581 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE);
1582 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1583 }
1584 }
1585
1586 jump = base + card->tst_size - 2;
1587
1588 write_sram(card, jump, TSTE_OPC_NULL);
1589 set_bit(TST_SWITCH_WAIT, &card->tst_state);
1590
1591 mod_timer(&card->tst_timer, jiffies + 1);
1592 }
1593
1594out:
1595 spin_unlock_irqrestore(&card->tst_lock, flags);
1596}
1597
1598static int
1599__fill_tst(struct idt77252_dev *card, struct vc_map *vc,
1600 int n, unsigned int opc)
1601{
1602 unsigned long cl, avail;
1603 unsigned long idle;
1604 int e, r;
1605 u32 data;
1606
1607 avail = card->tst_size - 2;
1608 for (e = 0; e < avail; e++) {
1609 if (card->soft_tst[e].vc == NULL)
1610 break;
1611 }
1612 if (e >= avail) {
1613 printk("%s: No free TST entries found\n", card->name);
1614 return -1;
1615 }
1616
1617 NPRINTK("%s: conn %d: first TST entry at %d.\n",
1618 card->name, vc ? vc->index : -1, e);
1619
1620 r = n;
1621 cl = avail;
1622 data = opc & TSTE_OPC_MASK;
1623 if (vc && (opc != TSTE_OPC_NULL))
1624 data = opc | vc->index;
1625
1626 idle = card->tst[card->tst_index ^ 1];
1627
1628 /*
1629 * Fill Soft TST.
1630 */
1631 while (r > 0) {
1632 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) {
1633 if (vc)
1634 card->soft_tst[e].vc = vc;
1635 else
1636 card->soft_tst[e].vc = (void *)-1;
1637
1638 card->soft_tst[e].tste = data;
1639 if (timer_pending(&card->tst_timer))
1640 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1641 else {
1642 write_sram(card, idle + e, data);
1643 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1644 }
1645
1646 cl -= card->tst_size;
1647 r--;
1648 }
1649
1650 if (++e == avail)
1651 e = 0;
1652 cl += n;
1653 }
1654
1655 return 0;
1656}
1657
1658static int
1659fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)
1660{
1661 unsigned long flags;
1662 int res;
1663
1664 spin_lock_irqsave(&card->tst_lock, flags);
1665
1666 res = __fill_tst(card, vc, n, opc);
1667
1668 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1669 if (!timer_pending(&card->tst_timer))
1670 mod_timer(&card->tst_timer, jiffies + 1);
1671
1672 spin_unlock_irqrestore(&card->tst_lock, flags);
1673 return res;
1674}
1675
1676static int
1677__clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1678{
1679 unsigned long idle;
1680 int e;
1681
1682 idle = card->tst[card->tst_index ^ 1];
1683
1684 for (e = 0; e < card->tst_size - 2; e++) {
1685 if (card->soft_tst[e].vc == vc) {
1686 card->soft_tst[e].vc = NULL;
1687
1688 card->soft_tst[e].tste = TSTE_OPC_VAR;
1689 if (timer_pending(&card->tst_timer))
1690 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1691 else {
1692 write_sram(card, idle + e, TSTE_OPC_VAR);
1693 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1694 }
1695 }
1696 }
1697
1698 return 0;
1699}
1700
1701static int
1702clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1703{
1704 unsigned long flags;
1705 int res;
1706
1707 spin_lock_irqsave(&card->tst_lock, flags);
1708
1709 res = __clear_tst(card, vc);
1710
1711 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1712 if (!timer_pending(&card->tst_timer))
1713 mod_timer(&card->tst_timer, jiffies + 1);
1714
1715 spin_unlock_irqrestore(&card->tst_lock, flags);
1716 return res;
1717}
1718
1719static int
1720change_tst(struct idt77252_dev *card, struct vc_map *vc,
1721 int n, unsigned int opc)
1722{
1723 unsigned long flags;
1724 int res;
1725
1726 spin_lock_irqsave(&card->tst_lock, flags);
1727
1728 __clear_tst(card, vc);
1729 res = __fill_tst(card, vc, n, opc);
1730
1731 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1732 if (!timer_pending(&card->tst_timer))
1733 mod_timer(&card->tst_timer, jiffies + 1);
1734
1735 spin_unlock_irqrestore(&card->tst_lock, flags);
1736 return res;
1737}
1738
1739
1740static int
1741set_tct(struct idt77252_dev *card, struct vc_map *vc)
1742{
1743 unsigned long tct;
1744
1745 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE);
1746
1747 switch (vc->class) {
1748 case SCHED_CBR:
1749 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1750 card->name, tct, vc->scq->scd);
1751
1752 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd);
1753 write_sram(card, tct + 1, 0);
1754 write_sram(card, tct + 2, 0);
1755 write_sram(card, tct + 3, 0);
1756 write_sram(card, tct + 4, 0);
1757 write_sram(card, tct + 5, 0);
1758 write_sram(card, tct + 6, 0);
1759 write_sram(card, tct + 7, 0);
1760 break;
1761
1762 case SCHED_UBR:
1763 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1764 card->name, tct, vc->scq->scd);
1765
1766 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd);
1767 write_sram(card, tct + 1, 0);
1768 write_sram(card, tct + 2, TCT_TSIF);
1769 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE);
1770 write_sram(card, tct + 4, 0);
1771 write_sram(card, tct + 5, vc->init_er);
1772 write_sram(card, tct + 6, 0);
1773 write_sram(card, tct + 7, TCT_FLAG_UBR);
1774 break;
1775
1776 case SCHED_VBR:
1777 case SCHED_ABR:
1778 default:
1779 return -ENOSYS;
1780 }
1781
1782 return 0;
1783}
1784
1785/*****************************************************************************/
1786/* */
1787/* FBQ Handling */
1788/* */
1789/*****************************************************************************/
1790
1791static __inline__ int
1792idt77252_fbq_level(struct idt77252_dev *card, int queue)
1793{
1794 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f;
1795}
1796
1797static __inline__ int
1798idt77252_fbq_full(struct idt77252_dev *card, int queue)
1799{
1800 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f;
1801}
1802
1803static int
1804push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue)
1805{
1806 unsigned long flags;
1807 u32 handle;
1808 u32 addr;
1809
1810 skb->data = skb->head;
1811 skb_reset_tail_pointer(skb);
1812 skb->len = 0;
1813
1814 skb_reserve(skb, 16);
1815
1816 switch (queue) {
1817 case 0:
1818 skb_put(skb, SAR_FB_SIZE_0);
1819 break;
1820 case 1:
1821 skb_put(skb, SAR_FB_SIZE_1);
1822 break;
1823 case 2:
1824 skb_put(skb, SAR_FB_SIZE_2);
1825 break;
1826 case 3:
1827 skb_put(skb, SAR_FB_SIZE_3);
1828 break;
1829 default:
1830 return -1;
1831 }
1832
1833 if (idt77252_fbq_full(card, queue))
1834 return -1;
1835
1836 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32));
1837
1838 handle = IDT77252_PRV_POOL(skb);
1839 addr = IDT77252_PRV_PADDR(skb);
1840
1841 spin_lock_irqsave(&card->cmd_lock, flags);
1842 writel(handle, card->fbq[queue]);
1843 writel(addr, card->fbq[queue]);
1844 spin_unlock_irqrestore(&card->cmd_lock, flags);
1845
1846 return 0;
1847}
1848
1849static void
1850add_rx_skb(struct idt77252_dev *card, int queue,
1851 unsigned int size, unsigned int count)
1852{
1853 struct sk_buff *skb;
1854 dma_addr_t paddr;
1855 u32 handle;
1856
1857 while (count--) {
1858 skb = dev_alloc_skb(size);
1859 if (!skb)
1860 return;
1861
1862 if (sb_pool_add(card, skb, queue)) {
1863 printk("%s: SB POOL full\n", __func__);
1864 goto outfree;
1865 }
1866
1867 paddr = pci_map_single(card->pcidev, skb->data,
1868 skb_end_pointer(skb) - skb->data,
1869 PCI_DMA_FROMDEVICE);
1870 IDT77252_PRV_PADDR(skb) = paddr;
1871
1872 if (push_rx_skb(card, skb, queue)) {
1873 printk("%s: FB QUEUE full\n", __func__);
1874 goto outunmap;
1875 }
1876 }
1877
1878 return;
1879
1880outunmap:
1881 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1882 skb_end_pointer(skb) - skb->data, PCI_DMA_FROMDEVICE);
1883
1884 handle = IDT77252_PRV_POOL(skb);
1885 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL;
1886
1887outfree:
1888 dev_kfree_skb(skb);
1889}
1890
1891
1892static void
1893recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb)
1894{
1895 u32 handle = IDT77252_PRV_POOL(skb);
1896 int err;
1897
1898 pci_dma_sync_single_for_device(card->pcidev, IDT77252_PRV_PADDR(skb),
1899 skb_end_pointer(skb) - skb->data,
1900 PCI_DMA_FROMDEVICE);
1901
1902 err = push_rx_skb(card, skb, POOL_QUEUE(handle));
1903 if (err) {
1904 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1905 skb_end_pointer(skb) - skb->data,
1906 PCI_DMA_FROMDEVICE);
1907 sb_pool_remove(card, skb);
1908 dev_kfree_skb(skb);
1909 }
1910}
1911
1912static void
1913flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp)
1914{
1915 skb_queue_head_init(&rpp->queue);
1916 rpp->len = 0;
1917}
1918
1919static void
1920recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp)
1921{
1922 struct sk_buff *skb, *tmp;
1923
1924 skb_queue_walk_safe(&rpp->queue, skb, tmp)
1925 recycle_rx_skb(card, skb);
1926
1927 flush_rx_pool(card, rpp);
1928}
1929
1930/*****************************************************************************/
1931/* */
1932/* ATM Interface */
1933/* */
1934/*****************************************************************************/
1935
1936static void
1937idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr)
1938{
1939 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value);
1940}
1941
1942static unsigned char
1943idt77252_phy_get(struct atm_dev *dev, unsigned long addr)
1944{
1945 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff));
1946}
1947
1948static inline int
1949idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam)
1950{
1951 struct atm_dev *dev = vcc->dev;
1952 struct idt77252_dev *card = dev->dev_data;
1953 struct vc_map *vc = vcc->dev_data;
1954 int err;
1955
1956 if (vc == NULL) {
1957 printk("%s: NULL connection in send().\n", card->name);
1958 atomic_inc(&vcc->stats->tx_err);
1959 dev_kfree_skb(skb);
1960 return -EINVAL;
1961 }
1962 if (!test_bit(VCF_TX, &vc->flags)) {
1963 printk("%s: Trying to transmit on a non-tx VC.\n", card->name);
1964 atomic_inc(&vcc->stats->tx_err);
1965 dev_kfree_skb(skb);
1966 return -EINVAL;
1967 }
1968
1969 switch (vcc->qos.aal) {
1970 case ATM_AAL0:
1971 case ATM_AAL1:
1972 case ATM_AAL5:
1973 break;
1974 default:
1975 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
1976 atomic_inc(&vcc->stats->tx_err);
1977 dev_kfree_skb(skb);
1978 return -EINVAL;
1979 }
1980
1981 if (skb_shinfo(skb)->nr_frags != 0) {
1982 printk("%s: No scatter-gather yet.\n", card->name);
1983 atomic_inc(&vcc->stats->tx_err);
1984 dev_kfree_skb(skb);
1985 return -EINVAL;
1986 }
1987 ATM_SKB(skb)->vcc = vcc;
1988
1989 err = queue_skb(card, vc, skb, oam);
1990 if (err) {
1991 atomic_inc(&vcc->stats->tx_err);
1992 dev_kfree_skb(skb);
1993 return err;
1994 }
1995
1996 return 0;
1997}
1998
1999static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb)
2000{
2001 return idt77252_send_skb(vcc, skb, 0);
2002}
2003
2004static int
2005idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags)
2006{
2007 struct atm_dev *dev = vcc->dev;
2008 struct idt77252_dev *card = dev->dev_data;
2009 struct sk_buff *skb;
2010
2011 skb = dev_alloc_skb(64);
2012 if (!skb) {
2013 printk("%s: Out of memory in send_oam().\n", card->name);
2014 atomic_inc(&vcc->stats->tx_err);
2015 return -ENOMEM;
2016 }
2017 atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);
2018
2019 memcpy(skb_put(skb, 52), cell, 52);
2020
2021 return idt77252_send_skb(vcc, skb, 1);
2022}
2023
2024static __inline__ unsigned int
2025idt77252_fls(unsigned int x)
2026{
2027 int r = 1;
2028
2029 if (x == 0)
2030 return 0;
2031 if (x & 0xffff0000) {
2032 x >>= 16;
2033 r += 16;
2034 }
2035 if (x & 0xff00) {
2036 x >>= 8;
2037 r += 8;
2038 }
2039 if (x & 0xf0) {
2040 x >>= 4;
2041 r += 4;
2042 }
2043 if (x & 0xc) {
2044 x >>= 2;
2045 r += 2;
2046 }
2047 if (x & 0x2)
2048 r += 1;
2049 return r;
2050}
2051
2052static u16
2053idt77252_int_to_atmfp(unsigned int rate)
2054{
2055 u16 m, e;
2056
2057 if (rate == 0)
2058 return 0;
2059 e = idt77252_fls(rate) - 1;
2060 if (e < 9)
2061 m = (rate - (1 << e)) << (9 - e);
2062 else if (e == 9)
2063 m = (rate - (1 << e));
2064 else /* e > 9 */
2065 m = (rate - (1 << e)) >> (e - 9);
2066 return 0x4000 | (e << 9) | m;
2067}
2068
2069static u8
2070idt77252_rate_logindex(struct idt77252_dev *card, int pcr)
2071{
2072 u16 afp;
2073
2074 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr);
2075 if (pcr < 0)
2076 return rate_to_log[(afp >> 5) & 0x1ff];
2077 return rate_to_log[((afp >> 5) + 1) & 0x1ff];
2078}
2079
2080static void
2081idt77252_est_timer(unsigned long data)
2082{
2083 struct vc_map *vc = (struct vc_map *)data;
2084 struct idt77252_dev *card = vc->card;
2085 struct rate_estimator *est;
2086 unsigned long flags;
2087 u32 rate, cps;
2088 u64 ncells;
2089 u8 lacr;
2090
2091 spin_lock_irqsave(&vc->lock, flags);
2092 est = vc->estimator;
2093 if (!est)
2094 goto out;
2095
2096 ncells = est->cells;
2097
2098 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval);
2099 est->last_cells = ncells;
2100 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log;
2101 est->cps = (est->avcps + 0x1f) >> 5;
2102
2103 cps = est->cps;
2104 if (cps < (est->maxcps >> 4))
2105 cps = est->maxcps >> 4;
2106
2107 lacr = idt77252_rate_logindex(card, cps);
2108 if (lacr > vc->max_er)
2109 lacr = vc->max_er;
2110
2111 if (lacr != vc->lacr) {
2112 vc->lacr = lacr;
2113 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ);
2114 }
2115
2116 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2117 add_timer(&est->timer);
2118
2119out:
2120 spin_unlock_irqrestore(&vc->lock, flags);
2121}
2122
2123static struct rate_estimator *
2124idt77252_init_est(struct vc_map *vc, int pcr)
2125{
2126 struct rate_estimator *est;
2127
2128 est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL);
2129 if (!est)
2130 return NULL;
2131 est->maxcps = pcr < 0 ? -pcr : pcr;
2132 est->cps = est->maxcps;
2133 est->avcps = est->cps << 5;
2134
2135 est->interval = 2; /* XXX: make this configurable */
2136 est->ewma_log = 2; /* XXX: make this configurable */
2137 init_timer(&est->timer);
2138 est->timer.data = (unsigned long)vc;
2139 est->timer.function = idt77252_est_timer;
2140
2141 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2142 add_timer(&est->timer);
2143
2144 return est;
2145}
2146
2147static int
2148idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc,
2149 struct atm_vcc *vcc, struct atm_qos *qos)
2150{
2151 int tst_free, tst_used, tst_entries;
2152 unsig…Large files files are truncated, but you can click here to view the full file