/arch/x86/pci/i386.c

  1/*
  2 *	Low-Level PCI Access for i386 machines
  3 *
  4 * Copyright 1993, 1994 Drew Eckhardt
  5 *      Visionary Computing
  6 *      (Unix and Linux consulting and custom programming)
  7 *      Drew@Colorado.EDU
  8 *      +1 (303) 786-7975
  9 *
 10 * Drew's work was sponsored by:
 11 *	iX Multiuser Multitasking Magazine
 12 *	Hannover, Germany
 13 *	hm@ix.de
 14 *
 15 * Copyright 1997--2000 Martin Mares <mj@ucw.cz>
 16 *
 17 * For more information, please consult the following manuals (look at
 18 * http://www.pcisig.com/ for how to get them):
 19 *
 20 * PCI BIOS Specification
 21 * PCI Local Bus Specification
 22 * PCI to PCI Bridge Specification
 23 * PCI System Design Guide
 24 *
 25 */
 26
 27#include <linux/types.h>
 28#include <linux/kernel.h>
 29#include <linux/pci.h>
 30#include <linux/init.h>
 31#include <linux/ioport.h>
 32#include <linux/errno.h>
 33#include <linux/bootmem.h>
 34
 35#include <asm/pat.h>
 36#include <asm/e820.h>
 37#include <asm/pci_x86.h>
 38#include <asm/io_apic.h>
 39
 40
 41static int
 42skip_isa_ioresource_align(struct pci_dev *dev) {
 43
 44	if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) &&
 45	    !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
 46		return 1;
 47	return 0;
 48}
 49
 50/*
 51 * We need to avoid collisions with `mirrored' VGA ports
 52 * and other strange ISA hardware, so we always want the
 53 * addresses to be allocated in the 0x000-0x0ff region
 54 * modulo 0x400.
 55 *
 56 * Why? Because some silly external IO cards only decode
 57 * the low 10 bits of the IO address. The 0x00-0xff region
 58 * is reserved for motherboard devices that decode all 16
 59 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 60 * but we want to try to avoid allocating at 0x2900-0x2bff
 61 * which might have be mirrored at 0x0100-0x03ff..
 62 */
 63resource_size_t
 64pcibios_align_resource(void *data, const struct resource *res,
 65			resource_size_t size, resource_size_t align)
 66{
 67	struct pci_dev *dev = data;
 68	resource_size_t start = res->start;
 69
 70	if (res->flags & IORESOURCE_IO) {
 71		if (skip_isa_ioresource_align(dev))
 72			return start;
 73		if (start & 0x300)
 74			start = (start + 0x3ff) & ~0x3ff;
 75	} else if (res->flags & IORESOURCE_MEM) {
 76		if (start < BIOS_END)
 77			start = BIOS_END;
 78	}
 79	return start;
 80}
 81EXPORT_SYMBOL(pcibios_align_resource);
 82
 83/*
 84 *  Handle resources of PCI devices.  If the world were perfect, we could
 85 *  just allocate all the resource regions and do nothing more.  It isn't.
 86 *  On the other hand, we cannot just re-allocate all devices, as it would
 87 *  require us to know lots of host bridge internals.  So we attempt to
 88 *  keep as much of the original configuration as possible, but tweak it
 89 *  when it's found to be wrong.
 90 *
 91 *  Known BIOS problems we have to work around:
 92 *	- I/O or memory regions not configured
 93 *	- regions configured, but not enabled in the command register
 94 *	- bogus I/O addresses above 64K used
 95 *	- expansion ROMs left enabled (this may sound harmless, but given
 96 *	  the fact the PCI specs explicitly allow address decoders to be
 97 *	  shared between expansion ROMs and other resource regions, it's
 98 *	  at least dangerous)
 99 *	- bad resource sizes or overlaps with other regions
100 *
101 *  Our solution:
102 *	(1) Allocate resources for all buses behind PCI-to-PCI bridges.
103 *	    This gives us fixed barriers on where we can allocate.
104 *	(2) Allocate resources for all enabled devices.  If there is
105 *	    a collision, just mark the resource as unallocated. Also
106 *	    disable expansion ROMs during this step.
107 *	(3) Try to allocate resources for disabled devices.  If the
108 *	    resources were assigned correctly, everything goes well,
109 *	    if they weren't, they won't disturb allocation of other
110 *	    resources.
111 *	(4) Assign new addresses to resources which were either
112 *	    not configured at all or misconfigured.  If explicitly
113 *	    requested by the user, configure expansion ROM address
114 *	    as well.
115 */
116
117static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
118{
119	struct pci_bus *bus;
120	struct pci_dev *dev;
121	int idx;
122	struct resource *r;
123
124	/* Depth-First Search on bus tree */
125	list_for_each_entry(bus, bus_list, node) {
126		if ((dev = bus->self)) {
127			for (idx = PCI_BRIDGE_RESOURCES;
128			    idx < PCI_NUM_RESOURCES; idx++) {
129				r = &dev->resource[idx];
130				if (!r->flags)
131					continue;
132				if (!r->start ||
133				    pci_claim_resource(dev, idx) < 0) {
134					/*
135					 * Something is wrong with the region.
136					 * Invalidate the resource to prevent
137					 * child resource allocations in this
138					 * range.
139					 */
140					r->start = r->end = 0;
141					r->flags = 0;
142				}
143			}
144		}
145		pcibios_allocate_bus_resources(&bus->children);
146	}
147}
148
149struct pci_check_idx_range {
150	int start;
151	int end;
152};
153
154static void __init pcibios_allocate_resources(int pass)
155{
156	struct pci_dev *dev = NULL;
157	int idx, disabled, i;
158	u16 command;
159	struct resource *r;
160
161	struct pci_check_idx_range idx_range[] = {
162		{ PCI_STD_RESOURCES, PCI_STD_RESOURCE_END },
163#ifdef CONFIG_PCI_IOV
164		{ PCI_IOV_RESOURCES, PCI_IOV_RESOURCE_END },
165#endif
166	};
167
168	for_each_pci_dev(dev) {
169		pci_read_config_word(dev, PCI_COMMAND, &command);
170		for (i = 0; i < ARRAY_SIZE(idx_range); i++)
171		for (idx = idx_range[i].start; idx <= idx_range[i].end; idx++) {
172			r = &dev->resource[idx];
173			if (r->parent)		/* Already allocated */
174				continue;
175			if (!r->start)		/* Address not assigned at all */
176				continue;
177			if (r->flags & IORESOURCE_IO)
178				disabled = !(command & PCI_COMMAND_IO);
179			else
180				disabled = !(command & PCI_COMMAND_MEMORY);
181			if (pass == disabled) {
182				dev_dbg(&dev->dev,
183					"BAR %d: reserving %pr (d=%d, p=%d)\n",
184					idx, r, disabled, pass);
185				if (pci_claim_resource(dev, idx) < 0) {
186					/* We'll assign a new address later */
187					dev->fw_addr[idx] = r->start;
188					r->end -= r->start;
189					r->start = 0;
190				}
191			}
192		}
193		if (!pass) {
194			r = &dev->resource[PCI_ROM_RESOURCE];
195			if (r->flags & IORESOURCE_ROM_ENABLE) {
196				/* Turn the ROM off, leave the resource region,
197				 * but keep it unregistered. */
198				u32 reg;
199				dev_dbg(&dev->dev, "disabling ROM %pR\n", r);
200				r->flags &= ~IORESOURCE_ROM_ENABLE;
201				pci_read_config_dword(dev,
202						dev->rom_base_reg, &reg);
203				pci_write_config_dword(dev, dev->rom_base_reg,
204						reg & ~PCI_ROM_ADDRESS_ENABLE);
205			}
206		}
207	}
208}
209
210static int __init pcibios_assign_resources(void)
211{
212	struct pci_dev *dev = NULL;
213	struct resource *r;
214
215	if (!(pci_probe & PCI_ASSIGN_ROMS)) {
216		/*
217		 * Try to use BIOS settings for ROMs, otherwise let
218		 * pci_assign_unassigned_resources() allocate the new
219		 * addresses.
220		 */
221		for_each_pci_dev(dev) {
222			r = &dev->resource[PCI_ROM_RESOURCE];
223			if (!r->flags || !r->start)
224				continue;
225			if (pci_claim_resource(dev, PCI_ROM_RESOURCE) < 0) {
226				r->end -= r->start;
227				r->start = 0;
228			}
229		}
230	}
231
232	pci_assign_unassigned_resources();
233
234	return 0;
235}
236
237void __init pcibios_resource_survey(void)
238{
239	DBG("PCI: Allocating resources\n");
240	pcibios_allocate_bus_resources(&pci_root_buses);
241	pcibios_allocate_resources(0);
242	pcibios_allocate_resources(1);
243
244	e820_reserve_resources_late();
245	/*
246	 * Insert the IO APIC resources after PCI initialization has
247	 * occured to handle IO APICS that are mapped in on a BAR in
248	 * PCI space, but before trying to assign unassigned pci res.
249	 */
250	ioapic_insert_resources();
251}
252
253/**
254 * called in fs_initcall (one below subsys_initcall),
255 * give a chance for motherboard reserve resources
256 */
257fs_initcall(pcibios_assign_resources);
258
259/*
260 *  If we set up a device for bus mastering, we need to check the latency
261 *  timer as certain crappy BIOSes forget to set it properly.
262 */
263unsigned int pcibios_max_latency = 255;
264
265void pcibios_set_master(struct pci_dev *dev)
266{
267	u8 lat;
268	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
269	if (lat < 16)
270		lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
271	else if (lat > pcibios_max_latency)
272		lat = pcibios_max_latency;
273	else
274		return;
275	dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
276	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
277}
278
279static const struct vm_operations_struct pci_mmap_ops = {
280	.access = generic_access_phys,
281};
282
283int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
284			enum pci_mmap_state mmap_state, int write_combine)
285{
286	unsigned long prot;
287
288	/* I/O space cannot be accessed via normal processor loads and
289	 * stores on this platform.
290	 */
291	if (mmap_state == pci_mmap_io)
292		return -EINVAL;
293
294	prot = pgprot_val(vma->vm_page_prot);
295
296	/*
297 	 * Return error if pat is not enabled and write_combine is requested.
298 	 * Caller can followup with UC MINUS request and add a WC mtrr if there
299 	 * is a free mtrr slot.
300 	 */
301	if (!pat_enabled && write_combine)
302		return -EINVAL;
303
304	if (pat_enabled && write_combine)
305		prot |= _PAGE_CACHE_WC;
306	else if (pat_enabled || boot_cpu_data.x86 > 3)
307		/*
308		 * ioremap() and ioremap_nocache() defaults to UC MINUS for now.
309		 * To avoid attribute conflicts, request UC MINUS here
310		 * aswell.
311		 */
312		prot |= _PAGE_CACHE_UC_MINUS;
313
314	vma->vm_page_prot = __pgprot(prot);
315
316	if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
317			       vma->vm_end - vma->vm_start,
318			       vma->vm_page_prot))
319		return -EAGAIN;
320
321	vma->vm_ops = &pci_mmap_ops;
322
323	return 0;
324}