/arch/x86/include/asm/msr-index.h
C Header | 404 lines | 325 code | 54 blank | 25 comment | 0 complexity | 6e20484109c4b5855391d08359e52533 MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
1#ifndef _ASM_X86_MSR_INDEX_H
2#define _ASM_X86_MSR_INDEX_H
3
4/* CPU model specific register (MSR) numbers */
5
6/* x86-64 specific MSRs */
7#define MSR_EFER 0xc0000080 /* extended feature register */
8#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
9#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
10#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
11#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
12#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
13#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
14#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
15#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
16
17/* EFER bits: */
18#define _EFER_SCE 0 /* SYSCALL/SYSRET */
19#define _EFER_LME 8 /* Long mode enable */
20#define _EFER_LMA 10 /* Long mode active (read-only) */
21#define _EFER_NX 11 /* No execute enable */
22#define _EFER_SVME 12 /* Enable virtualization */
23#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
24
25#define EFER_SCE (1<<_EFER_SCE)
26#define EFER_LME (1<<_EFER_LME)
27#define EFER_LMA (1<<_EFER_LMA)
28#define EFER_NX (1<<_EFER_NX)
29#define EFER_SVME (1<<_EFER_SVME)
30#define EFER_FFXSR (1<<_EFER_FFXSR)
31
32/* Intel MSRs. Some also available on other CPUs */
33#define MSR_IA32_PERFCTR0 0x000000c1
34#define MSR_IA32_PERFCTR1 0x000000c2
35#define MSR_FSB_FREQ 0x000000cd
36
37#define MSR_MTRRcap 0x000000fe
38#define MSR_IA32_BBL_CR_CTL 0x00000119
39
40#define MSR_IA32_SYSENTER_CS 0x00000174
41#define MSR_IA32_SYSENTER_ESP 0x00000175
42#define MSR_IA32_SYSENTER_EIP 0x00000176
43
44#define MSR_IA32_MCG_CAP 0x00000179
45#define MSR_IA32_MCG_STATUS 0x0000017a
46#define MSR_IA32_MCG_CTL 0x0000017b
47
48#define MSR_IA32_PEBS_ENABLE 0x000003f1
49#define MSR_IA32_DS_AREA 0x00000600
50#define MSR_IA32_PERF_CAPABILITIES 0x00000345
51
52#define MSR_MTRRfix64K_00000 0x00000250
53#define MSR_MTRRfix16K_80000 0x00000258
54#define MSR_MTRRfix16K_A0000 0x00000259
55#define MSR_MTRRfix4K_C0000 0x00000268
56#define MSR_MTRRfix4K_C8000 0x00000269
57#define MSR_MTRRfix4K_D0000 0x0000026a
58#define MSR_MTRRfix4K_D8000 0x0000026b
59#define MSR_MTRRfix4K_E0000 0x0000026c
60#define MSR_MTRRfix4K_E8000 0x0000026d
61#define MSR_MTRRfix4K_F0000 0x0000026e
62#define MSR_MTRRfix4K_F8000 0x0000026f
63#define MSR_MTRRdefType 0x000002ff
64
65#define MSR_IA32_CR_PAT 0x00000277
66
67#define MSR_IA32_DEBUGCTLMSR 0x000001d9
68#define MSR_IA32_LASTBRANCHFROMIP 0x000001db
69#define MSR_IA32_LASTBRANCHTOIP 0x000001dc
70#define MSR_IA32_LASTINTFROMIP 0x000001dd
71#define MSR_IA32_LASTINTTOIP 0x000001de
72
73/* DEBUGCTLMSR bits (others vary by model): */
74#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
75#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
76#define DEBUGCTLMSR_TR (1UL << 6)
77#define DEBUGCTLMSR_BTS (1UL << 7)
78#define DEBUGCTLMSR_BTINT (1UL << 8)
79#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
80#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
81#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
82
83#define MSR_IA32_MC0_CTL 0x00000400
84#define MSR_IA32_MC0_STATUS 0x00000401
85#define MSR_IA32_MC0_ADDR 0x00000402
86#define MSR_IA32_MC0_MISC 0x00000403
87
88#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
89#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
90#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
91#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
92
93/* These are consecutive and not in the normal 4er MCE bank block */
94#define MSR_IA32_MC0_CTL2 0x00000280
95#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
96
97#define CMCI_EN (1ULL << 30)
98#define CMCI_THRESHOLD_MASK 0xffffULL
99
100#define MSR_P6_PERFCTR0 0x000000c1
101#define MSR_P6_PERFCTR1 0x000000c2
102#define MSR_P6_EVNTSEL0 0x00000186
103#define MSR_P6_EVNTSEL1 0x00000187
104
105/* AMD64 MSRs. Not complete. See the architecture manual for a more
106 complete list. */
107
108#define MSR_AMD64_PATCH_LEVEL 0x0000008b
109#define MSR_AMD64_NB_CFG 0xc001001f
110#define MSR_AMD64_PATCH_LOADER 0xc0010020
111#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
112#define MSR_AMD64_OSVW_STATUS 0xc0010141
113#define MSR_AMD64_DC_CFG 0xc0011022
114#define MSR_AMD64_IBSFETCHCTL 0xc0011030
115#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
116#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
117#define MSR_AMD64_IBSOPCTL 0xc0011033
118#define MSR_AMD64_IBSOPRIP 0xc0011034
119#define MSR_AMD64_IBSOPDATA 0xc0011035
120#define MSR_AMD64_IBSOPDATA2 0xc0011036
121#define MSR_AMD64_IBSOPDATA3 0xc0011037
122#define MSR_AMD64_IBSDCLINAD 0xc0011038
123#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
124#define MSR_AMD64_IBSCTL 0xc001103a
125
126/* Fam 10h MSRs */
127#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
128#define FAM10H_MMIO_CONF_ENABLE (1<<0)
129#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
130#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
131#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffff
132#define FAM10H_MMIO_CONF_BASE_SHIFT 20
133#define MSR_FAM10H_NODE_ID 0xc001100c
134
135/* K8 MSRs */
136#define MSR_K8_TOP_MEM1 0xc001001a
137#define MSR_K8_TOP_MEM2 0xc001001d
138#define MSR_K8_SYSCFG 0xc0010010
139#define MSR_K8_INT_PENDING_MSG 0xc0010055
140/* C1E active bits in int pending message */
141#define K8_INTP_C1E_ACTIVE_MASK 0x18000000
142#define MSR_K8_TSEG_ADDR 0xc0010112
143#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
144#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
145#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
146
147/* K7 MSRs */
148#define MSR_K7_EVNTSEL0 0xc0010000
149#define MSR_K7_PERFCTR0 0xc0010004
150#define MSR_K7_EVNTSEL1 0xc0010001
151#define MSR_K7_PERFCTR1 0xc0010005
152#define MSR_K7_EVNTSEL2 0xc0010002
153#define MSR_K7_PERFCTR2 0xc0010006
154#define MSR_K7_EVNTSEL3 0xc0010003
155#define MSR_K7_PERFCTR3 0xc0010007
156#define MSR_K7_CLK_CTL 0xc001001b
157#define MSR_K7_HWCR 0xc0010015
158#define MSR_K7_FID_VID_CTL 0xc0010041
159#define MSR_K7_FID_VID_STATUS 0xc0010042
160
161/* K6 MSRs */
162#define MSR_K6_EFER 0xc0000080
163#define MSR_K6_STAR 0xc0000081
164#define MSR_K6_WHCR 0xc0000082
165#define MSR_K6_UWCCR 0xc0000085
166#define MSR_K6_EPMR 0xc0000086
167#define MSR_K6_PSOR 0xc0000087
168#define MSR_K6_PFIR 0xc0000088
169
170/* Centaur-Hauls/IDT defined MSRs. */
171#define MSR_IDT_FCR1 0x00000107
172#define MSR_IDT_FCR2 0x00000108
173#define MSR_IDT_FCR3 0x00000109
174#define MSR_IDT_FCR4 0x0000010a
175
176#define MSR_IDT_MCR0 0x00000110
177#define MSR_IDT_MCR1 0x00000111
178#define MSR_IDT_MCR2 0x00000112
179#define MSR_IDT_MCR3 0x00000113
180#define MSR_IDT_MCR4 0x00000114
181#define MSR_IDT_MCR5 0x00000115
182#define MSR_IDT_MCR6 0x00000116
183#define MSR_IDT_MCR7 0x00000117
184#define MSR_IDT_MCR_CTRL 0x00000120
185
186/* VIA Cyrix defined MSRs*/
187#define MSR_VIA_FCR 0x00001107
188#define MSR_VIA_LONGHAUL 0x0000110a
189#define MSR_VIA_RNG 0x0000110b
190#define MSR_VIA_BCR2 0x00001147
191
192/* Transmeta defined MSRs */
193#define MSR_TMTA_LONGRUN_CTRL 0x80868010
194#define MSR_TMTA_LONGRUN_FLAGS 0x80868011
195#define MSR_TMTA_LRTI_READOUT 0x80868018
196#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
197
198/* Intel defined MSRs. */
199#define MSR_IA32_P5_MC_ADDR 0x00000000
200#define MSR_IA32_P5_MC_TYPE 0x00000001
201#define MSR_IA32_TSC 0x00000010
202#define MSR_IA32_PLATFORM_ID 0x00000017
203#define MSR_IA32_EBL_CR_POWERON 0x0000002a
204#define MSR_IA32_FEATURE_CONTROL 0x0000003a
205
206#define FEATURE_CONTROL_LOCKED (1<<0)
207#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
208#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
209
210#define MSR_IA32_APICBASE 0x0000001b
211#define MSR_IA32_APICBASE_BSP (1<<8)
212#define MSR_IA32_APICBASE_ENABLE (1<<11)
213#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
214
215#define MSR_IA32_UCODE_WRITE 0x00000079
216#define MSR_IA32_UCODE_REV 0x0000008b
217
218#define MSR_IA32_PERF_STATUS 0x00000198
219#define MSR_IA32_PERF_CTL 0x00000199
220
221#define MSR_IA32_MPERF 0x000000e7
222#define MSR_IA32_APERF 0x000000e8
223
224#define MSR_IA32_THERM_CONTROL 0x0000019a
225#define MSR_IA32_THERM_INTERRUPT 0x0000019b
226
227#define THERM_INT_LOW_ENABLE (1 << 0)
228#define THERM_INT_HIGH_ENABLE (1 << 1)
229
230#define MSR_IA32_THERM_STATUS 0x0000019c
231
232#define THERM_STATUS_PROCHOT (1 << 0)
233
234#define MSR_THERM2_CTL 0x0000019d
235
236#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
237
238#define MSR_IA32_MISC_ENABLE 0x000001a0
239
240#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
241
242/* MISC_ENABLE bits: architectural */
243#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0)
244#define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1)
245#define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7)
246#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11)
247#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12)
248#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16)
249#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
250#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22)
251#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23)
252#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34)
253
254/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
255#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2)
256#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3)
257#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4)
258#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6)
259#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8)
260#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9)
261#define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10)
262#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10)
263#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13)
264#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19)
265#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20)
266#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24)
267#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37)
268#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
269#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)
270
271/* P4/Xeon+ specific */
272#define MSR_IA32_MCG_EAX 0x00000180
273#define MSR_IA32_MCG_EBX 0x00000181
274#define MSR_IA32_MCG_ECX 0x00000182
275#define MSR_IA32_MCG_EDX 0x00000183
276#define MSR_IA32_MCG_ESI 0x00000184
277#define MSR_IA32_MCG_EDI 0x00000185
278#define MSR_IA32_MCG_EBP 0x00000186
279#define MSR_IA32_MCG_ESP 0x00000187
280#define MSR_IA32_MCG_EFLAGS 0x00000188
281#define MSR_IA32_MCG_EIP 0x00000189
282#define MSR_IA32_MCG_RESERVED 0x0000018a
283
284/* Pentium IV performance counter MSRs */
285#define MSR_P4_BPU_PERFCTR0 0x00000300
286#define MSR_P4_BPU_PERFCTR1 0x00000301
287#define MSR_P4_BPU_PERFCTR2 0x00000302
288#define MSR_P4_BPU_PERFCTR3 0x00000303
289#define MSR_P4_MS_PERFCTR0 0x00000304
290#define MSR_P4_MS_PERFCTR1 0x00000305
291#define MSR_P4_MS_PERFCTR2 0x00000306
292#define MSR_P4_MS_PERFCTR3 0x00000307
293#define MSR_P4_FLAME_PERFCTR0 0x00000308
294#define MSR_P4_FLAME_PERFCTR1 0x00000309
295#define MSR_P4_FLAME_PERFCTR2 0x0000030a
296#define MSR_P4_FLAME_PERFCTR3 0x0000030b
297#define MSR_P4_IQ_PERFCTR0 0x0000030c
298#define MSR_P4_IQ_PERFCTR1 0x0000030d
299#define MSR_P4_IQ_PERFCTR2 0x0000030e
300#define MSR_P4_IQ_PERFCTR3 0x0000030f
301#define MSR_P4_IQ_PERFCTR4 0x00000310
302#define MSR_P4_IQ_PERFCTR5 0x00000311
303#define MSR_P4_BPU_CCCR0 0x00000360
304#define MSR_P4_BPU_CCCR1 0x00000361
305#define MSR_P4_BPU_CCCR2 0x00000362
306#define MSR_P4_BPU_CCCR3 0x00000363
307#define MSR_P4_MS_CCCR0 0x00000364
308#define MSR_P4_MS_CCCR1 0x00000365
309#define MSR_P4_MS_CCCR2 0x00000366
310#define MSR_P4_MS_CCCR3 0x00000367
311#define MSR_P4_FLAME_CCCR0 0x00000368
312#define MSR_P4_FLAME_CCCR1 0x00000369
313#define MSR_P4_FLAME_CCCR2 0x0000036a
314#define MSR_P4_FLAME_CCCR3 0x0000036b
315#define MSR_P4_IQ_CCCR0 0x0000036c
316#define MSR_P4_IQ_CCCR1 0x0000036d
317#define MSR_P4_IQ_CCCR2 0x0000036e
318#define MSR_P4_IQ_CCCR3 0x0000036f
319#define MSR_P4_IQ_CCCR4 0x00000370
320#define MSR_P4_IQ_CCCR5 0x00000371
321#define MSR_P4_ALF_ESCR0 0x000003ca
322#define MSR_P4_ALF_ESCR1 0x000003cb
323#define MSR_P4_BPU_ESCR0 0x000003b2
324#define MSR_P4_BPU_ESCR1 0x000003b3
325#define MSR_P4_BSU_ESCR0 0x000003a0
326#define MSR_P4_BSU_ESCR1 0x000003a1
327#define MSR_P4_CRU_ESCR0 0x000003b8
328#define MSR_P4_CRU_ESCR1 0x000003b9
329#define MSR_P4_CRU_ESCR2 0x000003cc
330#define MSR_P4_CRU_ESCR3 0x000003cd
331#define MSR_P4_CRU_ESCR4 0x000003e0
332#define MSR_P4_CRU_ESCR5 0x000003e1
333#define MSR_P4_DAC_ESCR0 0x000003a8
334#define MSR_P4_DAC_ESCR1 0x000003a9
335#define MSR_P4_FIRM_ESCR0 0x000003a4
336#define MSR_P4_FIRM_ESCR1 0x000003a5
337#define MSR_P4_FLAME_ESCR0 0x000003a6
338#define MSR_P4_FLAME_ESCR1 0x000003a7
339#define MSR_P4_FSB_ESCR0 0x000003a2
340#define MSR_P4_FSB_ESCR1 0x000003a3
341#define MSR_P4_IQ_ESCR0 0x000003ba
342#define MSR_P4_IQ_ESCR1 0x000003bb
343#define MSR_P4_IS_ESCR0 0x000003b4
344#define MSR_P4_IS_ESCR1 0x000003b5
345#define MSR_P4_ITLB_ESCR0 0x000003b6
346#define MSR_P4_ITLB_ESCR1 0x000003b7
347#define MSR_P4_IX_ESCR0 0x000003c8
348#define MSR_P4_IX_ESCR1 0x000003c9
349#define MSR_P4_MOB_ESCR0 0x000003aa
350#define MSR_P4_MOB_ESCR1 0x000003ab
351#define MSR_P4_MS_ESCR0 0x000003c0
352#define MSR_P4_MS_ESCR1 0x000003c1
353#define MSR_P4_PMH_ESCR0 0x000003ac
354#define MSR_P4_PMH_ESCR1 0x000003ad
355#define MSR_P4_RAT_ESCR0 0x000003bc
356#define MSR_P4_RAT_ESCR1 0x000003bd
357#define MSR_P4_SAAT_ESCR0 0x000003ae
358#define MSR_P4_SAAT_ESCR1 0x000003af
359#define MSR_P4_SSU_ESCR0 0x000003be
360#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
361
362#define MSR_P4_TBPU_ESCR0 0x000003c2
363#define MSR_P4_TBPU_ESCR1 0x000003c3
364#define MSR_P4_TC_ESCR0 0x000003c4
365#define MSR_P4_TC_ESCR1 0x000003c5
366#define MSR_P4_U2L_ESCR0 0x000003b0
367#define MSR_P4_U2L_ESCR1 0x000003b1
368
369#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
370
371/* Intel Core-based CPU performance counters */
372#define MSR_CORE_PERF_FIXED_CTR0 0x00000309
373#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
374#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
375#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
376#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
377#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
378#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
379
380/* Geode defined MSRs */
381#define MSR_GEODE_BUSCONT_CONF0 0x00001900
382
383/* Intel VT MSRs */
384#define MSR_IA32_VMX_BASIC 0x00000480
385#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
386#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
387#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
388#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
389#define MSR_IA32_VMX_MISC 0x00000485
390#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
391#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
392#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
393#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
394#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
395#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
396#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
397
398/* AMD-V MSRs */
399
400#define MSR_VM_CR 0xc0010114
401#define MSR_VM_IGNNE 0xc0010115
402#define MSR_VM_HSAVE_PA 0xc0010117
403
404#endif /* _ASM_X86_MSR_INDEX_H */