/arch/x86/include/asm/visws/cobalt.h

  1#ifndef _ASM_X86_VISWS_COBALT_H
  2#define _ASM_X86_VISWS_COBALT_H
  3
  4#include <asm/fixmap.h>
  5
  6/*
  7 * Cobalt SGI Visual Workstation system ASIC
  8 */ 
  9
 10#define CO_CPU_NUM_PHYS 0x1e00
 11#define CO_CPU_TAB_PHYS (CO_CPU_NUM_PHYS + 2)
 12
 13#define CO_CPU_MAX 4
 14
 15#define	CO_CPU_PHYS		0xc2000000
 16#define	CO_APIC_PHYS		0xc4000000
 17
 18/* see set_fixmap() and asm/fixmap.h */
 19#define	CO_CPU_VADDR		(fix_to_virt(FIX_CO_CPU))
 20#define	CO_APIC_VADDR		(fix_to_virt(FIX_CO_APIC))
 21
 22/* Cobalt CPU registers -- relative to CO_CPU_VADDR, use co_cpu_*() */
 23#define	CO_CPU_REV		0x08
 24#define	CO_CPU_CTRL		0x10
 25#define	CO_CPU_STAT		0x20
 26#define	CO_CPU_TIMEVAL		0x30
 27
 28/* CO_CPU_CTRL bits */
 29#define	CO_CTRL_TIMERUN		0x04		/* 0 == disabled */
 30#define	CO_CTRL_TIMEMASK	0x08		/* 0 == unmasked */
 31
 32/* CO_CPU_STATUS bits */
 33#define	CO_STAT_TIMEINTR	0x02	/* (r) 1 == int pend, (w) 0 == clear */
 34
 35/* CO_CPU_TIMEVAL value */
 36#define	CO_TIME_HZ		100000000	/* Cobalt core rate */
 37
 38/* Cobalt APIC registers -- relative to CO_APIC_VADDR, use co_apic_*() */
 39#define	CO_APIC_HI(n)		(((n) * 0x10) + 4)
 40#define	CO_APIC_LO(n)		((n) * 0x10)
 41#define	CO_APIC_ID		0x0ffc
 42
 43/* CO_APIC_ID bits */
 44#define	CO_APIC_ENABLE		0x00000100
 45
 46/* CO_APIC_LO bits */
 47#define	CO_APIC_MASK		0x00010000	/* 0 = enabled */
 48#define	CO_APIC_LEVEL		0x00008000	/* 0 = edge */
 49
 50/*
 51 * Where things are physically wired to Cobalt
 52 * #defines with no board _<type>_<rev>_ are common to all (thus far)
 53 */
 54#define	CO_APIC_IDE0		4
 55#define CO_APIC_IDE1		2		/* Only on 320 */
 56
 57#define	CO_APIC_8259		12		/* serial, floppy, par-l-l */
 58
 59/* Lithium PCI Bridge A -- "the one with 82557 Ethernet" */
 60#define	CO_APIC_PCIA_BASE0	0 /* and 1 */	/* slot 0, line 0 */
 61#define	CO_APIC_PCIA_BASE123	5 /* and 6 */	/* slot 0, line 1 */
 62
 63#define	CO_APIC_PIIX4_USB	7		/* this one is weird */
 64
 65/* Lithium PCI Bridge B -- "the one with PIIX4" */
 66#define	CO_APIC_PCIB_BASE0	8 /* and 9-12 *//* slot 0, line 0 */
 67#define	CO_APIC_PCIB_BASE123	13 /* 14.15 */	/* slot 0, line 1 */
 68
 69#define	CO_APIC_VIDOUT0		16
 70#define	CO_APIC_VIDOUT1		17
 71#define	CO_APIC_VIDIN0		18
 72#define	CO_APIC_VIDIN1		19
 73
 74#define	CO_APIC_LI_AUDIO	22
 75
 76#define	CO_APIC_AS		24
 77#define	CO_APIC_RE		25
 78
 79#define CO_APIC_CPU		28		/* Timer and Cache interrupt */
 80#define	CO_APIC_NMI		29
 81#define	CO_APIC_LAST		CO_APIC_NMI
 82
 83/*
 84 * This is how irqs are assigned on the Visual Workstation.
 85 * Legacy devices get irq's 1-15 (system clock is 0 and is CO_APIC_CPU).
 86 * All other devices (including PCI) go to Cobalt and are irq's 16 on up.
 87 */
 88#define	CO_IRQ_APIC0	16			/* irq of apic entry 0 */
 89#define	IS_CO_APIC(irq)	((irq) >= CO_IRQ_APIC0)
 90#define	CO_IRQ(apic)	(CO_IRQ_APIC0 + (apic))	/* apic ent to irq */
 91#define	CO_APIC(irq)	((irq) - CO_IRQ_APIC0)	/* irq to apic ent */
 92#define CO_IRQ_IDE0	14			/* knowledge of... */
 93#define CO_IRQ_IDE1	15			/* ... ide driver defaults! */
 94#define	CO_IRQ_8259	CO_IRQ(CO_APIC_8259)
 95
 96#ifdef CONFIG_X86_VISWS_APIC
 97static inline void co_cpu_write(unsigned long reg, unsigned long v)
 98{
 99	*((volatile unsigned long *)(CO_CPU_VADDR+reg))=v;
100}
101
102static inline unsigned long co_cpu_read(unsigned long reg)
103{
104	return *((volatile unsigned long *)(CO_CPU_VADDR+reg));
105}            
106             
107static inline void co_apic_write(unsigned long reg, unsigned long v)
108{
109	*((volatile unsigned long *)(CO_APIC_VADDR+reg))=v;
110}            
111             
112static inline unsigned long co_apic_read(unsigned long reg)
113{
114	return *((volatile unsigned long *)(CO_APIC_VADDR+reg));
115}
116#endif
117
118extern char visws_board_type;
119
120#define	VISWS_320	0
121#define	VISWS_540	1
122
123extern char visws_board_rev;
124
125extern int pci_visws_init(void);
126
127#endif /* _ASM_X86_VISWS_COBALT_H */