/arch/sparc/kernel/sun4c_irq.c

  1/*  sun4c_irq.c
  2 *  arch/sparc/kernel/sun4c_irq.c:
  3 *
  4 *  djhr: Hacked out of irq.c into a CPU dependent version.
  5 *
  6 *  Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
  7 *  Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
  8 *  Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
  9 *  Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
 10 */
 11
 12#include <linux/errno.h>
 13#include <linux/linkage.h>
 14#include <linux/kernel_stat.h>
 15#include <linux/signal.h>
 16#include <linux/sched.h>
 17#include <linux/ptrace.h>
 18#include <linux/interrupt.h>
 19#include <linux/init.h>
 20#include <linux/of.h>
 21#include <linux/of_device.h>
 22#include "irq.h"
 23
 24#include <asm/ptrace.h>
 25#include <asm/processor.h>
 26#include <asm/system.h>
 27#include <asm/psr.h>
 28#include <asm/vaddrs.h>
 29#include <asm/timer.h>
 30#include <asm/openprom.h>
 31#include <asm/oplib.h>
 32#include <asm/traps.h>
 33#include <asm/irq.h>
 34#include <asm/io.h>
 35#include <asm/idprom.h>
 36#include <asm/machines.h>
 37
 38/*
 39 * Bit field defines for the interrupt registers on various
 40 * Sparc machines.
 41 */
 42
 43/* The sun4c interrupt register. */
 44#define SUN4C_INT_ENABLE  0x01     /* Allow interrupts. */
 45#define SUN4C_INT_E14     0x80     /* Enable level 14 IRQ. */
 46#define SUN4C_INT_E10     0x20     /* Enable level 10 IRQ. */
 47#define SUN4C_INT_E8      0x10     /* Enable level 8 IRQ. */
 48#define SUN4C_INT_E6      0x08     /* Enable level 6 IRQ. */
 49#define SUN4C_INT_E4      0x04     /* Enable level 4 IRQ. */
 50#define SUN4C_INT_E1      0x02     /* Enable level 1 IRQ. */
 51
 52/* Pointer to the interrupt enable byte
 53 *
 54 * Dave Redman (djhr@tadpole.co.uk)
 55 * What you may not be aware of is that entry.S requires this variable.
 56 *
 57 *  --- linux_trap_nmi_sun4c --
 58 *
 59 * so don't go making it static, like I tried. sigh.
 60 */
 61unsigned char __iomem *interrupt_enable = NULL;
 62
 63static void sun4c_disable_irq(unsigned int irq_nr)
 64{
 65	unsigned long flags;
 66	unsigned char current_mask, new_mask;
 67    
 68	local_irq_save(flags);
 69	irq_nr &= (NR_IRQS - 1);
 70	current_mask = sbus_readb(interrupt_enable);
 71	switch(irq_nr) {
 72	case 1:
 73		new_mask = ((current_mask) & (~(SUN4C_INT_E1)));
 74		break;
 75	case 8:
 76		new_mask = ((current_mask) & (~(SUN4C_INT_E8)));
 77		break;
 78	case 10:
 79		new_mask = ((current_mask) & (~(SUN4C_INT_E10)));
 80		break;
 81	case 14:
 82		new_mask = ((current_mask) & (~(SUN4C_INT_E14)));
 83		break;
 84	default:
 85		local_irq_restore(flags);
 86		return;
 87	}
 88	sbus_writeb(new_mask, interrupt_enable);
 89	local_irq_restore(flags);
 90}
 91
 92static void sun4c_enable_irq(unsigned int irq_nr)
 93{
 94	unsigned long flags;
 95	unsigned char current_mask, new_mask;
 96    
 97	local_irq_save(flags);
 98	irq_nr &= (NR_IRQS - 1);
 99	current_mask = sbus_readb(interrupt_enable);
100	switch(irq_nr) {
101	case 1:
102		new_mask = ((current_mask) | SUN4C_INT_E1);
103		break;
104	case 8:
105		new_mask = ((current_mask) | SUN4C_INT_E8);
106		break;
107	case 10:
108		new_mask = ((current_mask) | SUN4C_INT_E10);
109		break;
110	case 14:
111		new_mask = ((current_mask) | SUN4C_INT_E14);
112		break;
113	default:
114		local_irq_restore(flags);
115		return;
116	}
117	sbus_writeb(new_mask, interrupt_enable);
118	local_irq_restore(flags);
119}
120
121struct sun4c_timer_info {
122	u32		l10_count;
123	u32		l10_limit;
124	u32		l14_count;
125	u32		l14_limit;
126};
127
128static struct sun4c_timer_info __iomem *sun4c_timers;
129
130static void sun4c_clear_clock_irq(void)
131{
132	sbus_readl(&sun4c_timers->l10_limit);
133}
134
135static void sun4c_load_profile_irq(int cpu, unsigned int limit)
136{
137	/* Errm.. not sure how to do this.. */
138}
139
140static void __init sun4c_init_timers(irq_handler_t counter_fn)
141{
142	const struct linux_prom_irqs *irq;
143	struct device_node *dp;
144	const u32 *addr;
145	int err;
146
147	dp = of_find_node_by_name(NULL, "counter-timer");
148	if (!dp) {
149		prom_printf("sun4c_init_timers: Unable to find counter-timer\n");
150		prom_halt();
151	}
152
153	addr = of_get_property(dp, "address", NULL);
154	if (!addr) {
155		prom_printf("sun4c_init_timers: No address property\n");
156		prom_halt();
157	}
158
159	sun4c_timers = (void __iomem *) (unsigned long) addr[0];
160
161	irq = of_get_property(dp, "intr", NULL);
162	of_node_put(dp);
163	if (!irq) {
164		prom_printf("sun4c_init_timers: No intr property\n");
165		prom_halt();
166	}
167
168	/* Have the level 10 timer tick at 100HZ.  We don't touch the
169	 * level 14 timer limit since we are letting the prom handle
170	 * them until we have a real console driver so L1-A works.
171	 */
172	sbus_writel((((1000000/HZ) + 1) << 10), &sun4c_timers->l10_limit);
173
174	master_l10_counter = &sun4c_timers->l10_count;
175
176	err = request_irq(irq[0].pri, counter_fn,
177			  (IRQF_DISABLED | SA_STATIC_ALLOC),
178			  "timer", NULL);
179	if (err) {
180		prom_printf("sun4c_init_timers: request_irq() fails with %d\n", err);
181		prom_halt();
182	}
183    
184	sun4c_disable_irq(irq[1].pri);
185}
186
187#ifdef CONFIG_SMP
188static void sun4c_nop(void) {}
189#endif
190
191void __init sun4c_init_IRQ(void)
192{
193	struct device_node *dp;
194	const u32 *addr;
195
196	dp = of_find_node_by_name(NULL, "interrupt-enable");
197	if (!dp) {
198		prom_printf("sun4c_init_IRQ: Unable to find interrupt-enable\n");
199		prom_halt();
200	}
201
202	addr = of_get_property(dp, "address", NULL);
203	of_node_put(dp);
204	if (!addr) {
205		prom_printf("sun4c_init_IRQ: No address property\n");
206		prom_halt();
207	}
208
209	interrupt_enable = (void __iomem *) (unsigned long) addr[0];
210
211	BTFIXUPSET_CALL(enable_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
212	BTFIXUPSET_CALL(disable_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
213	BTFIXUPSET_CALL(enable_pil_irq, sun4c_enable_irq, BTFIXUPCALL_NORM);
214	BTFIXUPSET_CALL(disable_pil_irq, sun4c_disable_irq, BTFIXUPCALL_NORM);
215	BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM);
216	BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP);
217	sparc_init_timers = sun4c_init_timers;
218#ifdef CONFIG_SMP
219	BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
220	BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
221	BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP);
222#endif
223	sbus_writeb(SUN4C_INT_ENABLE, interrupt_enable);
224	/* Cannot enable interrupts until OBP ticker is disabled. */
225}