PageRenderTime 31ms CodeModel.GetById 18ms app.highlight 11ms RepoModel.GetById 1ms app.codeStats 0ms

/arch/sh/kernel/cpu/sh2a/clock-sh7201.c

https://bitbucket.org/cresqo/cm7-p500-kernel
C | 85 lines | 59 code | 12 blank | 14 comment | 4 complexity | a4c8f43401f93a1e781a01d670fa5a0b MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
 1/*
 2 * arch/sh/kernel/cpu/sh2a/clock-sh7201.c
 3 *
 4 * SH7201 support for the clock framework
 5 *
 6 *  Copyright (C) 2008 Peter Griffin  <pgriffin@mpc-data.co.uk>
 7 *
 8 * Based on clock-sh4.c
 9 *  Copyright (C) 2005  Paul Mundt
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License.  See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/init.h>
16#include <linux/kernel.h>
17#include <asm/clock.h>
18#include <asm/freq.h>
19#include <asm/io.h>
20
21static const int pll1rate[]={1,2,3,4,6,8};
22static const int pfc_divisors[]={1,2,3,4,6,8,12};
23#define ifc_divisors pfc_divisors
24
25#if (CONFIG_SH_CLK_MD == 0)
26#define PLL2 (4)
27#elif (CONFIG_SH_CLK_MD == 2)
28#define PLL2 (2)
29#elif (CONFIG_SH_CLK_MD == 3)
30#define PLL2 (1)
31#else
32#error "Illegal Clock Mode!"
33#endif
34
35static void master_clk_init(struct clk *clk)
36{
37	return 10000000 * PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
38}
39
40static struct clk_ops sh7201_master_clk_ops = {
41	.init		= master_clk_init,
42};
43
44static unsigned long module_clk_recalc(struct clk *clk)
45{
46	int idx = (__raw_readw(FREQCR) & 0x0007);
47	return clk->parent->rate / pfc_divisors[idx];
48}
49
50static struct clk_ops sh7201_module_clk_ops = {
51	.recalc		= module_clk_recalc,
52};
53
54static unsigned long bus_clk_recalc(struct clk *clk)
55{
56	int idx = (__raw_readw(FREQCR) & 0x0007);
57	return clk->parent->rate / pfc_divisors[idx];
58}
59
60static struct clk_ops sh7201_bus_clk_ops = {
61	.recalc		= bus_clk_recalc,
62};
63
64static unsigned long cpu_clk_recalc(struct clk *clk)
65{
66	int idx = ((__raw_readw(FREQCR) >> 4) & 0x0007);
67	return clk->parent->rate / ifc_divisors[idx];
68}
69
70static struct clk_ops sh7201_cpu_clk_ops = {
71	.recalc		= cpu_clk_recalc,
72};
73
74static struct clk_ops *sh7201_clk_ops[] = {
75	&sh7201_master_clk_ops,
76	&sh7201_module_clk_ops,
77	&sh7201_bus_clk_ops,
78	&sh7201_cpu_clk_ops,
79};
80
81void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
82{
83	if (idx < ARRAY_SIZE(sh7201_clk_ops))
84		*ops = sh7201_clk_ops[idx];
85}