/arch/powerpc/include/asm/sigcontext.h

 1#ifndef _ASM_POWERPC_SIGCONTEXT_H
 2#define _ASM_POWERPC_SIGCONTEXT_H
 3
 4/*
 5 * This program is free software; you can redistribute it and/or
 6 * modify it under the terms of the GNU General Public License
 7 * as published by the Free Software Foundation; either version
 8 * 2 of the License, or (at your option) any later version.
 9 */
10#include <linux/compiler.h>
11#include <asm/ptrace.h>
12#ifdef __powerpc64__
13#include <asm/elf.h>
14#endif
15
16struct sigcontext {
17	unsigned long	_unused[4];
18	int		signal;
19#ifdef __powerpc64__
20	int		_pad0;
21#endif
22	unsigned long	handler;
23	unsigned long	oldmask;
24	struct pt_regs	__user *regs;
25#ifdef __powerpc64__
26	elf_gregset_t	gp_regs;
27	elf_fpregset_t	fp_regs;
28/*
29 * To maintain compatibility with current implementations the sigcontext is
30 * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)
31 * followed by an unstructured (vmx_reserve) field of 69 doublewords.  This
32 * allows the array of vector registers to be quadword aligned independent of
33 * the alignment of the containing sigcontext or ucontext. It is the
34 * responsibility of the code setting the sigcontext to set this pointer to
35 * either NULL (if this processor does not support the VMX feature) or the
36 * address of the first quadword within the allocated (vmx_reserve) area.
37 *
38 * The pointer (v_regs) of vector type (elf_vrreg_t) is type compatible with
39 * an array of 34 quadword entries (elf_vrregset_t).  The entries with
40 * indexes 0-31 contain the corresponding vector registers.  The entry with
41 * index 32 contains the vscr as the last word (offset 12) within the
42 * quadword.  This allows the vscr to be stored as either a quadword (since
43 * it must be copied via a vector register to/from storage) or as a word.
44 * The entry with index 33 contains the vrsave as the first word (offset 0)
45 * within the quadword.
46 *
47 * Part of the VSX data is stored here also by extending vmx_restore
48 * by an additional 32 double words.  Architecturally the layout of
49 * the VSR registers and how they overlap on top of the legacy FPR and
50 * VR registers is shown below:
51 *
52 *                    VSR doubleword 0               VSR doubleword 1
53 *           ----------------------------------------------------------------
54 *   VSR[0]  |             FPR[0]            |                              |
55 *           ----------------------------------------------------------------
56 *   VSR[1]  |             FPR[1]            |                              |
57 *           ----------------------------------------------------------------
58 *           |              ...              |                              |
59 *           |              ...              |                              |
60 *           ----------------------------------------------------------------
61 *   VSR[30] |             FPR[30]           |                              |
62 *           ----------------------------------------------------------------
63 *   VSR[31] |             FPR[31]           |                              |
64 *           ----------------------------------------------------------------
65 *   VSR[32] |                             VR[0]                            |
66 *           ----------------------------------------------------------------
67 *   VSR[33] |                             VR[1]                            |
68 *           ----------------------------------------------------------------
69 *           |                              ...                             |
70 *           |                              ...                             |
71 *           ----------------------------------------------------------------
72 *   VSR[62] |                             VR[30]                           |
73 *           ----------------------------------------------------------------
74 *   VSR[63] |                             VR[31]                           |
75 *           ----------------------------------------------------------------
76 *
77 * FPR/VSR 0-31 doubleword 0 is stored in fp_regs, and VMX/VSR 32-63
78 * is stored at the start of vmx_reserve.  vmx_reserve is extended for
79 * backwards compatility to store VSR 0-31 doubleword 1 after the VMX
80 * registers and vscr/vrsave.
81 */
82	elf_vrreg_t	__user *v_regs;
83	long		vmx_reserve[ELF_NVRREG+ELF_NVRREG+32+1];
84#endif
85};
86
87#endif /* _ASM_POWERPC_SIGCONTEXT_H */