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/arch/mips/powertv/asic/asic-calliope.c

https://bitbucket.org/cresqo/cm7-p500-kernel
C | 101 lines | 68 code | 8 blank | 25 comment | 0 complexity | fe7f8cf5788c5f0c79ec6f4b1e5fe1df MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
  1. /*
  2. * Locations of devices in the Calliope ASIC.
  3. *
  4. * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. *
  20. * Author: Ken Eppinett
  21. * David Schleef <ds@schleef.org>
  22. *
  23. * Description: Defines the platform resources for the SA settop.
  24. */
  25. #include <linux/init.h>
  26. #include <asm/mach-powertv/asic.h>
  27. #define CALLIOPE_ADDR(x) (CALLIOPE_IO_BASE + (x))
  28. const struct register_map calliope_register_map __initdata = {
  29. .eic_slow0_strt_add = {.phys = CALLIOPE_ADDR(0x800000)},
  30. .eic_cfg_bits = {.phys = CALLIOPE_ADDR(0x800038)},
  31. .eic_ready_status = {.phys = CALLIOPE_ADDR(0x80004c)},
  32. .chipver3 = {.phys = CALLIOPE_ADDR(0xA00800)},
  33. .chipver2 = {.phys = CALLIOPE_ADDR(0xA00804)},
  34. .chipver1 = {.phys = CALLIOPE_ADDR(0xA00808)},
  35. .chipver0 = {.phys = CALLIOPE_ADDR(0xA0080c)},
  36. /* The registers of IRBlaster */
  37. .uart1_intstat = {.phys = CALLIOPE_ADDR(0xA01800)},
  38. .uart1_inten = {.phys = CALLIOPE_ADDR(0xA01804)},
  39. .uart1_config1 = {.phys = CALLIOPE_ADDR(0xA01808)},
  40. .uart1_config2 = {.phys = CALLIOPE_ADDR(0xA0180C)},
  41. .uart1_divisorhi = {.phys = CALLIOPE_ADDR(0xA01810)},
  42. .uart1_divisorlo = {.phys = CALLIOPE_ADDR(0xA01814)},
  43. .uart1_data = {.phys = CALLIOPE_ADDR(0xA01818)},
  44. .uart1_status = {.phys = CALLIOPE_ADDR(0xA0181C)},
  45. .int_stat_3 = {.phys = CALLIOPE_ADDR(0xA02800)},
  46. .int_stat_2 = {.phys = CALLIOPE_ADDR(0xA02804)},
  47. .int_stat_1 = {.phys = CALLIOPE_ADDR(0xA02808)},
  48. .int_stat_0 = {.phys = CALLIOPE_ADDR(0xA0280c)},
  49. .int_config = {.phys = CALLIOPE_ADDR(0xA02810)},
  50. .int_int_scan = {.phys = CALLIOPE_ADDR(0xA02818)},
  51. .ien_int_3 = {.phys = CALLIOPE_ADDR(0xA02830)},
  52. .ien_int_2 = {.phys = CALLIOPE_ADDR(0xA02834)},
  53. .ien_int_1 = {.phys = CALLIOPE_ADDR(0xA02838)},
  54. .ien_int_0 = {.phys = CALLIOPE_ADDR(0xA0283c)},
  55. .int_level_3_3 = {.phys = CALLIOPE_ADDR(0xA02880)},
  56. .int_level_3_2 = {.phys = CALLIOPE_ADDR(0xA02884)},
  57. .int_level_3_1 = {.phys = CALLIOPE_ADDR(0xA02888)},
  58. .int_level_3_0 = {.phys = CALLIOPE_ADDR(0xA0288c)},
  59. .int_level_2_3 = {.phys = CALLIOPE_ADDR(0xA02890)},
  60. .int_level_2_2 = {.phys = CALLIOPE_ADDR(0xA02894)},
  61. .int_level_2_1 = {.phys = CALLIOPE_ADDR(0xA02898)},
  62. .int_level_2_0 = {.phys = CALLIOPE_ADDR(0xA0289c)},
  63. .int_level_1_3 = {.phys = CALLIOPE_ADDR(0xA028a0)},
  64. .int_level_1_2 = {.phys = CALLIOPE_ADDR(0xA028a4)},
  65. .int_level_1_1 = {.phys = CALLIOPE_ADDR(0xA028a8)},
  66. .int_level_1_0 = {.phys = CALLIOPE_ADDR(0xA028ac)},
  67. .int_level_0_3 = {.phys = CALLIOPE_ADDR(0xA028b0)},
  68. .int_level_0_2 = {.phys = CALLIOPE_ADDR(0xA028b4)},
  69. .int_level_0_1 = {.phys = CALLIOPE_ADDR(0xA028b8)},
  70. .int_level_0_0 = {.phys = CALLIOPE_ADDR(0xA028bc)},
  71. .int_docsis_en = {.phys = CALLIOPE_ADDR(0xA028F4)},
  72. .mips_pll_setup = {.phys = CALLIOPE_ADDR(0x980000)},
  73. .usb_fs = {.phys = CALLIOPE_ADDR(0x980030)},
  74. .test_bus = {.phys = CALLIOPE_ADDR(0x9800CC)},
  75. .crt_spare = {.phys = CALLIOPE_ADDR(0x9800d4)},
  76. .usb2_ohci_int_mask = {.phys = CALLIOPE_ADDR(0x9A000c)},
  77. .usb2_strap = {.phys = CALLIOPE_ADDR(0x9A0014)},
  78. .ehci_hcapbase = {.phys = CALLIOPE_ADDR(0x9BFE00)},
  79. .ohci_hc_revision = {.phys = CALLIOPE_ADDR(0x9BFC00)},
  80. .bcm1_bs_lmi_steer = {.phys = CALLIOPE_ADDR(0x9E0004)},
  81. .usb2_control = {.phys = CALLIOPE_ADDR(0x9E0054)},
  82. .usb2_stbus_obc = {.phys = CALLIOPE_ADDR(0x9BFF00)},
  83. .usb2_stbus_mess_size = {.phys = CALLIOPE_ADDR(0x9BFF04)},
  84. .usb2_stbus_chunk_size = {.phys = CALLIOPE_ADDR(0x9BFF08)},
  85. .pcie_regs = {.phys = 0x000000}, /* -doesn't exist- */
  86. .tim_ch = {.phys = CALLIOPE_ADDR(0xA02C10)},
  87. .tim_cl = {.phys = CALLIOPE_ADDR(0xA02C14)},
  88. .gpio_dout = {.phys = CALLIOPE_ADDR(0xA02c20)},
  89. .gpio_din = {.phys = CALLIOPE_ADDR(0xA02c24)},
  90. .gpio_dir = {.phys = CALLIOPE_ADDR(0xA02c2C)},
  91. .watchdog = {.phys = CALLIOPE_ADDR(0xA02c30)},
  92. .front_panel = {.phys = 0x000000}, /* -not used- */
  93. };