/arch/mips/kernel/cevt-sb1250.c

  1/*
  2 * Copyright (C) 2000, 2001 Broadcom Corporation
  3 *
  4 * This program is free software; you can redistribute it and/or
  5 * modify it under the terms of the GNU General Public License
  6 * as published by the Free Software Foundation; either version 2
  7 * of the License, or (at your option) any later version.
  8 *
  9 * This program is distributed in the hope that it will be useful,
 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 12 * GNU General Public License for more details.
 13 *
 14 * You should have received a copy of the GNU General Public License
 15 * along with this program; if not, write to the Free Software
 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 17 */
 18#include <linux/clockchips.h>
 19#include <linux/interrupt.h>
 20#include <linux/percpu.h>
 21#include <linux/smp.h>
 22
 23#include <asm/addrspace.h>
 24#include <asm/io.h>
 25#include <asm/time.h>
 26
 27#include <asm/sibyte/sb1250.h>
 28#include <asm/sibyte/sb1250_regs.h>
 29#include <asm/sibyte/sb1250_int.h>
 30#include <asm/sibyte/sb1250_scd.h>
 31
 32#define IMR_IP2_VAL	K_INT_MAP_I0
 33#define IMR_IP3_VAL	K_INT_MAP_I1
 34#define IMR_IP4_VAL	K_INT_MAP_I2
 35
 36/*
 37 * The general purpose timer ticks at 1MHz independent if
 38 * the rest of the system
 39 */
 40static void sibyte_set_mode(enum clock_event_mode mode,
 41                           struct clock_event_device *evt)
 42{
 43	unsigned int cpu = smp_processor_id();
 44	void __iomem *cfg, *init;
 45
 46	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
 47	init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
 48
 49	switch (mode) {
 50	case CLOCK_EVT_MODE_PERIODIC:
 51		__raw_writeq(0, cfg);
 52		__raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init);
 53		__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
 54			     cfg);
 55		break;
 56
 57	case CLOCK_EVT_MODE_ONESHOT:
 58		/* Stop the timer until we actually program a shot */
 59	case CLOCK_EVT_MODE_SHUTDOWN:
 60		__raw_writeq(0, cfg);
 61		break;
 62
 63	case CLOCK_EVT_MODE_UNUSED:	/* shuddup gcc */
 64	case CLOCK_EVT_MODE_RESUME:
 65		;
 66	}
 67}
 68
 69static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
 70{
 71	unsigned int cpu = smp_processor_id();
 72	void __iomem *cfg, *init;
 73
 74	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
 75	init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
 76
 77	__raw_writeq(0, cfg);
 78	__raw_writeq(delta - 1, init);
 79	__raw_writeq(M_SCD_TIMER_ENABLE, cfg);
 80
 81	return 0;
 82}
 83
 84static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
 85{
 86	unsigned int cpu = smp_processor_id();
 87	struct clock_event_device *cd = dev_id;
 88	void __iomem *cfg;
 89	unsigned long tmode;
 90
 91	if (cd->mode == CLOCK_EVT_MODE_PERIODIC)
 92		tmode = M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS;
 93	else
 94		tmode = 0;
 95
 96	/* ACK interrupt */
 97	cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
 98	____raw_writeq(tmode, cfg);
 99
100	cd->event_handler(cd);
101
102	return IRQ_HANDLED;
103}
104
105static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
106static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
107static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
108
109void __cpuinit sb1250_clockevent_init(void)
110{
111	unsigned int cpu = smp_processor_id();
112	unsigned int irq = K_INT_TIMER_0 + cpu;
113	struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu);
114	struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
115	unsigned char *name = per_cpu(sibyte_hpt_name, cpu);
116
117	/* Only have 4 general purpose timers, and we use last one as hpt */
118	BUG_ON(cpu > 2);
119
120	sprintf(name, "sb1250-counter-%d", cpu);
121	cd->name		= name;
122	cd->features		= CLOCK_EVT_FEAT_PERIODIC |
123				  CLOCK_EVT_FEAT_ONESHOT;
124	clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
125	cd->max_delta_ns	= clockevent_delta2ns(0x7fffff, cd);
126	cd->min_delta_ns	= clockevent_delta2ns(2, cd);
127	cd->rating		= 200;
128	cd->irq			= irq;
129	cd->cpumask		= cpumask_of(cpu);
130	cd->set_next_event	= sibyte_next_event;
131	cd->set_mode		= sibyte_set_mode;
132	clockevents_register_device(cd);
133
134	sb1250_mask_irq(cpu, irq);
135
136	/*
137	 * Map the timer interrupt to IP[4] of this cpu
138	 */
139	__raw_writeq(IMR_IP4_VAL,
140		     IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
141			    (irq << 3)));
142
143	sb1250_unmask_irq(cpu, irq);
144
145	action->handler	= sibyte_counter_handler;
146	action->flags	= IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER;
147	action->name	= name;
148	action->dev_id	= cd;
149
150	irq_set_affinity(irq, cpumask_of(cpu));
151	setup_irq(irq, action);
152}