/arch/mips/include/asm/cevt-r4k.h

 1/*
 2 * This file is subject to the terms and conditions of the GNU General Public
 3 * License.  See the file "COPYING" in the main directory of this archive
 4 * for more details.
 5 *
 6 * Copyright (C) 2008 Kevin D. Kissell
 7 */
 8
 9/*
10 * Definitions used for common event timer implementation
11 * for MIPS 4K-type processors and their MIPS MT variants.
12 * Avoids unsightly extern declarations in C files.
13 */
14#ifndef __ASM_CEVT_R4K_H
15#define __ASM_CEVT_R4K_H
16
17DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
18
19void mips_event_handler(struct clock_event_device *dev);
20int c0_compare_int_usable(void);
21void mips_set_clock_mode(enum clock_event_mode, struct clock_event_device *);
22irqreturn_t c0_compare_interrupt(int, void *);
23
24extern struct irqaction c0_compare_irqaction;
25extern int cp0_timer_irq_installed;
26
27/*
28 * Possibly handle a performance counter interrupt.
29 * Return true if the timer interrupt should not be checked
30 */
31
32static inline int handle_perf_irq(int r2)
33{
34	/*
35	 * The performance counter overflow interrupt may be shared with the
36	 * timer interrupt (cp0_perfcount_irq < 0). If it is and a
37	 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
38	 * and we can't reliably determine if a counter interrupt has also
39	 * happened (!r2) then don't check for a timer interrupt.
40	 */
41	return (cp0_perfcount_irq < 0) &&
42		perf_irq() == IRQ_HANDLED &&
43		!r2;
44}
45
46#endif /* __ASM_CEVT_R4K_H */