/arch/mips/include/asm/octeon/cvmx-pexp-defs.h

  1/***********************license start***************
  2 * Author: Cavium Networks
  3 *
  4 * Contact: support@caviumnetworks.com
  5 * This file is part of the OCTEON SDK
  6 *
  7 * Copyright (c) 2003-2008 Cavium Networks
  8 *
  9 * This file is free software; you can redistribute it and/or modify
 10 * it under the terms of the GNU General Public License, Version 2, as
 11 * published by the Free Software Foundation.
 12 *
 13 * This file is distributed in the hope that it will be useful, but
 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
 16 * NONINFRINGEMENT.  See the GNU General Public License for more
 17 * details.
 18 *
 19 * You should have received a copy of the GNU General Public License
 20 * along with this file; if not, write to the Free Software
 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 22 * or visit http://www.gnu.org/licenses/.
 23 *
 24 * This file may also be available under a different license from Cavium.
 25 * Contact Cavium Networks for more information
 26 ***********************license end**************************************/
 27
 28/**
 29 * cvmx-pexp-defs.h
 30 *
 31 * Configuration and status register (CSR) definitions for
 32 * OCTEON PEXP.
 33 *
 34 */
 35#ifndef __CVMX_PEXP_DEFS_H__
 36#define __CVMX_PEXP_DEFS_H__
 37
 38#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) \
 39	 CVMX_ADD_IO_SEG(0x00011F0000008000ull + (((offset) & 31) * 16))
 40#define CVMX_PEXP_NPEI_BIST_STATUS \
 41	 CVMX_ADD_IO_SEG(0x00011F0000008580ull)
 42#define CVMX_PEXP_NPEI_BIST_STATUS2 \
 43	 CVMX_ADD_IO_SEG(0x00011F0000008680ull)
 44#define CVMX_PEXP_NPEI_CTL_PORT0 \
 45	 CVMX_ADD_IO_SEG(0x00011F0000008250ull)
 46#define CVMX_PEXP_NPEI_CTL_PORT1 \
 47	 CVMX_ADD_IO_SEG(0x00011F0000008260ull)
 48#define CVMX_PEXP_NPEI_CTL_STATUS \
 49	 CVMX_ADD_IO_SEG(0x00011F0000008570ull)
 50#define CVMX_PEXP_NPEI_CTL_STATUS2 \
 51	 CVMX_ADD_IO_SEG(0x00011F000000BC00ull)
 52#define CVMX_PEXP_NPEI_DATA_OUT_CNT \
 53	 CVMX_ADD_IO_SEG(0x00011F00000085F0ull)
 54#define CVMX_PEXP_NPEI_DBG_DATA \
 55	 CVMX_ADD_IO_SEG(0x00011F0000008510ull)
 56#define CVMX_PEXP_NPEI_DBG_SELECT \
 57	 CVMX_ADD_IO_SEG(0x00011F0000008500ull)
 58#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL \
 59	 CVMX_ADD_IO_SEG(0x00011F00000085C0ull)
 60#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL \
 61	 CVMX_ADD_IO_SEG(0x00011F00000085D0ull)
 62#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) \
 63	 CVMX_ADD_IO_SEG(0x00011F0000008450ull + (((offset) & 7) * 16))
 64#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) \
 65	 CVMX_ADD_IO_SEG(0x00011F00000083B0ull + (((offset) & 7) * 16))
 66#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) \
 67	 CVMX_ADD_IO_SEG(0x00011F0000008400ull + (((offset) & 7) * 16))
 68#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) \
 69	 CVMX_ADD_IO_SEG(0x00011F00000084A0ull + (((offset) & 7) * 16))
 70#define CVMX_PEXP_NPEI_DMA_CNTS \
 71	 CVMX_ADD_IO_SEG(0x00011F00000085E0ull)
 72#define CVMX_PEXP_NPEI_DMA_CONTROL \
 73	 CVMX_ADD_IO_SEG(0x00011F00000083A0ull)
 74#define CVMX_PEXP_NPEI_INT_A_ENB \
 75	 CVMX_ADD_IO_SEG(0x00011F0000008560ull)
 76#define CVMX_PEXP_NPEI_INT_A_ENB2 \
 77	 CVMX_ADD_IO_SEG(0x00011F000000BCE0ull)
 78#define CVMX_PEXP_NPEI_INT_A_SUM \
 79	 CVMX_ADD_IO_SEG(0x00011F0000008550ull)
 80#define CVMX_PEXP_NPEI_INT_ENB \
 81	 CVMX_ADD_IO_SEG(0x00011F0000008540ull)
 82#define CVMX_PEXP_NPEI_INT_ENB2 \
 83	 CVMX_ADD_IO_SEG(0x00011F000000BCD0ull)
 84#define CVMX_PEXP_NPEI_INT_INFO \
 85	 CVMX_ADD_IO_SEG(0x00011F0000008590ull)
 86#define CVMX_PEXP_NPEI_INT_SUM \
 87	 CVMX_ADD_IO_SEG(0x00011F0000008530ull)
 88#define CVMX_PEXP_NPEI_INT_SUM2 \
 89	 CVMX_ADD_IO_SEG(0x00011F000000BCC0ull)
 90#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 \
 91	 CVMX_ADD_IO_SEG(0x00011F0000008600ull)
 92#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 \
 93	 CVMX_ADD_IO_SEG(0x00011F0000008610ull)
 94#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL \
 95	 CVMX_ADD_IO_SEG(0x00011F00000084F0ull)
 96#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) \
 97	 CVMX_ADD_IO_SEG(0x00011F0000008280ull + (((offset) & 31) * 16) - 16 * 12)
 98#define CVMX_PEXP_NPEI_MSI_ENB0 \
 99	 CVMX_ADD_IO_SEG(0x00011F000000BC50ull)
100#define CVMX_PEXP_NPEI_MSI_ENB1 \
101	 CVMX_ADD_IO_SEG(0x00011F000000BC60ull)
102#define CVMX_PEXP_NPEI_MSI_ENB2 \
103	 CVMX_ADD_IO_SEG(0x00011F000000BC70ull)
104#define CVMX_PEXP_NPEI_MSI_ENB3 \
105	 CVMX_ADD_IO_SEG(0x00011F000000BC80ull)
106#define CVMX_PEXP_NPEI_MSI_RCV0 \
107	 CVMX_ADD_IO_SEG(0x00011F000000BC10ull)
108#define CVMX_PEXP_NPEI_MSI_RCV1 \
109	 CVMX_ADD_IO_SEG(0x00011F000000BC20ull)
110#define CVMX_PEXP_NPEI_MSI_RCV2 \
111	 CVMX_ADD_IO_SEG(0x00011F000000BC30ull)
112#define CVMX_PEXP_NPEI_MSI_RCV3 \
113	 CVMX_ADD_IO_SEG(0x00011F000000BC40ull)
114#define CVMX_PEXP_NPEI_MSI_RD_MAP \
115	 CVMX_ADD_IO_SEG(0x00011F000000BCA0ull)
116#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 \
117	 CVMX_ADD_IO_SEG(0x00011F000000BCF0ull)
118#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 \
119	 CVMX_ADD_IO_SEG(0x00011F000000BD00ull)
120#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 \
121	 CVMX_ADD_IO_SEG(0x00011F000000BD10ull)
122#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 \
123	 CVMX_ADD_IO_SEG(0x00011F000000BD20ull)
124#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 \
125	 CVMX_ADD_IO_SEG(0x00011F000000BD30ull)
126#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 \
127	 CVMX_ADD_IO_SEG(0x00011F000000BD40ull)
128#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 \
129	 CVMX_ADD_IO_SEG(0x00011F000000BD50ull)
130#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 \
131	 CVMX_ADD_IO_SEG(0x00011F000000BD60ull)
132#define CVMX_PEXP_NPEI_MSI_WR_MAP \
133	 CVMX_ADD_IO_SEG(0x00011F000000BC90ull)
134#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT \
135	 CVMX_ADD_IO_SEG(0x00011F000000BD70ull)
136#define CVMX_PEXP_NPEI_PCIE_MSI_RCV \
137	 CVMX_ADD_IO_SEG(0x00011F000000BCB0ull)
138#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 \
139	 CVMX_ADD_IO_SEG(0x00011F0000008650ull)
140#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 \
141	 CVMX_ADD_IO_SEG(0x00011F0000008660ull)
142#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 \
143	 CVMX_ADD_IO_SEG(0x00011F0000008670ull)
144#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) \
145	 CVMX_ADD_IO_SEG(0x00011F000000A400ull + (((offset) & 31) * 16))
146#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) \
147	 CVMX_ADD_IO_SEG(0x00011F000000A800ull + (((offset) & 31) * 16))
148#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
149	 CVMX_ADD_IO_SEG(0x00011F000000AC00ull + (((offset) & 31) * 16))
150#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
151	 CVMX_ADD_IO_SEG(0x00011F000000B000ull + (((offset) & 31) * 16))
152#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) \
153	 CVMX_ADD_IO_SEG(0x00011F000000B400ull + (((offset) & 31) * 16))
154#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) \
155	 CVMX_ADD_IO_SEG(0x00011F000000B800ull + (((offset) & 31) * 16))
156#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) \
157	 CVMX_ADD_IO_SEG(0x00011F0000009400ull + (((offset) & 31) * 16))
158#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
159	 CVMX_ADD_IO_SEG(0x00011F0000009800ull + (((offset) & 31) * 16))
160#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
161	 CVMX_ADD_IO_SEG(0x00011F0000009C00ull + (((offset) & 31) * 16))
162#define CVMX_PEXP_NPEI_PKT_CNT_INT \
163	 CVMX_ADD_IO_SEG(0x00011F0000009110ull)
164#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB \
165	 CVMX_ADD_IO_SEG(0x00011F0000009130ull)
166#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES \
167	 CVMX_ADD_IO_SEG(0x00011F00000090B0ull)
168#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS \
169	 CVMX_ADD_IO_SEG(0x00011F00000090A0ull)
170#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR \
171	 CVMX_ADD_IO_SEG(0x00011F0000009090ull)
172#define CVMX_PEXP_NPEI_PKT_DPADDR \
173	 CVMX_ADD_IO_SEG(0x00011F0000009080ull)
174#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL \
175	 CVMX_ADD_IO_SEG(0x00011F0000009150ull)
176#define CVMX_PEXP_NPEI_PKT_INSTR_ENB \
177	 CVMX_ADD_IO_SEG(0x00011F0000009000ull)
178#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE \
179	 CVMX_ADD_IO_SEG(0x00011F0000009190ull)
180#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE \
181	 CVMX_ADD_IO_SEG(0x00011F0000009020ull)
182#define CVMX_PEXP_NPEI_PKT_INT_LEVELS \
183	 CVMX_ADD_IO_SEG(0x00011F0000009100ull)
184#define CVMX_PEXP_NPEI_PKT_IN_BP \
185	 CVMX_ADD_IO_SEG(0x00011F00000086B0ull)
186#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) \
187	 CVMX_ADD_IO_SEG(0x00011F000000A000ull + (((offset) & 31) * 16))
188#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS \
189	 CVMX_ADD_IO_SEG(0x00011F00000086A0ull)
190#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT \
191	 CVMX_ADD_IO_SEG(0x00011F00000091A0ull)
192#define CVMX_PEXP_NPEI_PKT_IPTR \
193	 CVMX_ADD_IO_SEG(0x00011F0000009070ull)
194#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK \
195	 CVMX_ADD_IO_SEG(0x00011F0000009160ull)
196#define CVMX_PEXP_NPEI_PKT_OUT_BMODE \
197	 CVMX_ADD_IO_SEG(0x00011F00000090D0ull)
198#define CVMX_PEXP_NPEI_PKT_OUT_ENB \
199	 CVMX_ADD_IO_SEG(0x00011F0000009010ull)
200#define CVMX_PEXP_NPEI_PKT_PCIE_PORT \
201	 CVMX_ADD_IO_SEG(0x00011F00000090E0ull)
202#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST \
203	 CVMX_ADD_IO_SEG(0x00011F0000008690ull)
204#define CVMX_PEXP_NPEI_PKT_SLIST_ES \
205	 CVMX_ADD_IO_SEG(0x00011F0000009050ull)
206#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE \
207	 CVMX_ADD_IO_SEG(0x00011F0000009180ull)
208#define CVMX_PEXP_NPEI_PKT_SLIST_NS \
209	 CVMX_ADD_IO_SEG(0x00011F0000009040ull)
210#define CVMX_PEXP_NPEI_PKT_SLIST_ROR \
211	 CVMX_ADD_IO_SEG(0x00011F0000009030ull)
212#define CVMX_PEXP_NPEI_PKT_TIME_INT \
213	 CVMX_ADD_IO_SEG(0x00011F0000009120ull)
214#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB \
215	 CVMX_ADD_IO_SEG(0x00011F0000009140ull)
216#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS \
217	 CVMX_ADD_IO_SEG(0x00011F0000008520ull)
218#define CVMX_PEXP_NPEI_SCRATCH_1 \
219	 CVMX_ADD_IO_SEG(0x00011F0000008270ull)
220#define CVMX_PEXP_NPEI_STATE1 \
221	 CVMX_ADD_IO_SEG(0x00011F0000008620ull)
222#define CVMX_PEXP_NPEI_STATE2 \
223	 CVMX_ADD_IO_SEG(0x00011F0000008630ull)
224#define CVMX_PEXP_NPEI_STATE3 \
225	 CVMX_ADD_IO_SEG(0x00011F0000008640ull)
226#define CVMX_PEXP_NPEI_WINDOW_CTL \
227	 CVMX_ADD_IO_SEG(0x00011F0000008380ull)
228
229#endif