/arch/mips/include/asm/octeon/cvmx-ciu-defs.h

https://bitbucket.org/cresqo/cm7-p500-kernel · C Header · 1616 lines · 1552 code · 38 blank · 26 comment · 0 complexity · 5a7dc1fab2b8d8ae540a7db2f85bc7e3 MD5 · raw file 

    

  1. /***********************license start***************
    2. 

  2.  * Author: Cavium Networks
    3. 

  3.  *
    4. 

  4.  * Contact: support@caviumnetworks.com
    5. 

  5.  * This file is part of the OCTEON SDK
    6. 

  6.  *
    7. 

  7.  * Copyright (c) 2003-2008 Cavium Networks
    8. 

  8.  *
    9. 

  9.  * This file is free software; you can redistribute it and/or modify
    10. 

  10.  * it under the terms of the GNU General Public License, Version 2, as
    11. 

  11.  * published by the Free Software Foundation.
    12. 

  12.  *
    13. 

  13.  * This file is distributed in the hope that it will be useful, but
    14. 

  14.  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
    15. 

  15.  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
    16. 

  16.  * NONINFRINGEMENT.  See the GNU General Public License for more
    17. 

  17.  * details.
    18. 

  18.  *
    19. 

  19.  * You should have received a copy of the GNU General Public License
    20. 

  20.  * along with this file; if not, write to the Free Software
    21. 

  21.  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
    22. 

  22.  * or visit http://www.gnu.org/licenses/.
    23. 

  23.  *
    24. 

  24.  * This file may also be available under a different license from Cavium.
    25. 

  25.  * Contact Cavium Networks for more information
    26. 

  26.  ***********************license end**************************************/
    27. 

  27. 

  28. #ifndef __CVMX_CIU_DEFS_H__
    29. 

  29. #define __CVMX_CIU_DEFS_H__
    30. 

  30. 

  31. #define CVMX_CIU_BIST \
    32. 

  32. 	 CVMX_ADD_IO_SEG(0x0001070000000730ull)
    33. 

  33. #define CVMX_CIU_DINT \
    34. 

  34. 	 CVMX_ADD_IO_SEG(0x0001070000000720ull)
    35. 

  35. #define CVMX_CIU_FUSE \
    36. 

  36. 	 CVMX_ADD_IO_SEG(0x0001070000000728ull)
    37. 

  37. #define CVMX_CIU_GSTOP \
    38. 

  38. 	 CVMX_ADD_IO_SEG(0x0001070000000710ull)
    39. 

  39. #define CVMX_CIU_INTX_EN0(offset) \
    40. 

  40. 	 CVMX_ADD_IO_SEG(0x0001070000000200ull + (((offset) & 63) * 16))
    41. 

  41. #define CVMX_CIU_INTX_EN0_W1C(offset) \
    42. 

  42. 	 CVMX_ADD_IO_SEG(0x0001070000002200ull + (((offset) & 63) * 16))
    43. 

  43. #define CVMX_CIU_INTX_EN0_W1S(offset) \
    44. 

  44. 	 CVMX_ADD_IO_SEG(0x0001070000006200ull + (((offset) & 63) * 16))
    45. 

  45. #define CVMX_CIU_INTX_EN1(offset) \
    46. 

  46. 	 CVMX_ADD_IO_SEG(0x0001070000000208ull + (((offset) & 63) * 16))
    47. 

  47. #define CVMX_CIU_INTX_EN1_W1C(offset) \
    48. 

  48. 	 CVMX_ADD_IO_SEG(0x0001070000002208ull + (((offset) & 63) * 16))
    49. 

  49. #define CVMX_CIU_INTX_EN1_W1S(offset) \
    50. 

  50. 	 CVMX_ADD_IO_SEG(0x0001070000006208ull + (((offset) & 63) * 16))
    51. 

  51. #define CVMX_CIU_INTX_EN4_0(offset) \
    52. 

  52. 	 CVMX_ADD_IO_SEG(0x0001070000000C80ull + (((offset) & 15) * 16))
    53. 

  53. #define CVMX_CIU_INTX_EN4_0_W1C(offset) \
    54. 

  54. 	 CVMX_ADD_IO_SEG(0x0001070000002C80ull + (((offset) & 15) * 16))
    55. 

  55. #define CVMX_CIU_INTX_EN4_0_W1S(offset) \
    56. 

  56. 	 CVMX_ADD_IO_SEG(0x0001070000006C80ull + (((offset) & 15) * 16))
    57. 

  57. #define CVMX_CIU_INTX_EN4_1(offset) \
    58. 

  58. 	 CVMX_ADD_IO_SEG(0x0001070000000C88ull + (((offset) & 15) * 16))
    59. 

  59. #define CVMX_CIU_INTX_EN4_1_W1C(offset) \
    60. 

  60. 	 CVMX_ADD_IO_SEG(0x0001070000002C88ull + (((offset) & 15) * 16))
    61. 

  61. #define CVMX_CIU_INTX_EN4_1_W1S(offset) \
    62. 

  62. 	 CVMX_ADD_IO_SEG(0x0001070000006C88ull + (((offset) & 15) * 16))
    63. 

  63. #define CVMX_CIU_INTX_SUM0(offset) \
    64. 

  64. 	 CVMX_ADD_IO_SEG(0x0001070000000000ull + (((offset) & 63) * 8))
    65. 

  65. #define CVMX_CIU_INTX_SUM4(offset) \
    66. 

  66. 	 CVMX_ADD_IO_SEG(0x0001070000000C00ull + (((offset) & 15) * 8))
    67. 

  67. #define CVMX_CIU_INT_SUM1 \
    68. 

  68. 	 CVMX_ADD_IO_SEG(0x0001070000000108ull)
    69. 

  69. #define CVMX_CIU_MBOX_CLRX(offset) \
    70. 

  70. 	 CVMX_ADD_IO_SEG(0x0001070000000680ull + (((offset) & 15) * 8))
    71. 

  71. #define CVMX_CIU_MBOX_SETX(offset) \
    72. 

  72. 	 CVMX_ADD_IO_SEG(0x0001070000000600ull + (((offset) & 15) * 8))
    73. 

  73. #define CVMX_CIU_NMI \
    74. 

  74. 	 CVMX_ADD_IO_SEG(0x0001070000000718ull)
    75. 

  75. #define CVMX_CIU_PCI_INTA \
    76. 

  76. 	 CVMX_ADD_IO_SEG(0x0001070000000750ull)
    77. 

  77. #define CVMX_CIU_PP_DBG \
    78. 

  78. 	 CVMX_ADD_IO_SEG(0x0001070000000708ull)
    79. 

  79. #define CVMX_CIU_PP_POKEX(offset) \
    80. 

  80. 	 CVMX_ADD_IO_SEG(0x0001070000000580ull + (((offset) & 15) * 8))
    81. 

  81. #define CVMX_CIU_PP_RST \
    82. 

  82. 	 CVMX_ADD_IO_SEG(0x0001070000000700ull)
    83. 

  83. #define CVMX_CIU_QLM_DCOK \
    84. 

  84. 	 CVMX_ADD_IO_SEG(0x0001070000000760ull)
    85. 

  85. #define CVMX_CIU_QLM_JTGC \
    86. 

  86. 	 CVMX_ADD_IO_SEG(0x0001070000000768ull)
    87. 

  87. #define CVMX_CIU_QLM_JTGD \
    88. 

  88. 	 CVMX_ADD_IO_SEG(0x0001070000000770ull)
    89. 

  89. #define CVMX_CIU_SOFT_BIST \
    90. 

  90. 	 CVMX_ADD_IO_SEG(0x0001070000000738ull)
    91. 

  91. #define CVMX_CIU_SOFT_PRST \
    92. 

  92. 	 CVMX_ADD_IO_SEG(0x0001070000000748ull)
    93. 

  93. #define CVMX_CIU_SOFT_PRST1 \
    94. 

  94. 	 CVMX_ADD_IO_SEG(0x0001070000000758ull)
    95. 

  95. #define CVMX_CIU_SOFT_RST \
    96. 

  96. 	 CVMX_ADD_IO_SEG(0x0001070000000740ull)
    97. 

  97. #define CVMX_CIU_TIMX(offset) \
    98. 

  98. 	 CVMX_ADD_IO_SEG(0x0001070000000480ull + (((offset) & 3) * 8))
    99. 

  99. #define CVMX_CIU_WDOGX(offset) \
    100. 

  100. 	 CVMX_ADD_IO_SEG(0x0001070000000500ull + (((offset) & 15) * 8))
    101. 

  101. 

  102. union cvmx_ciu_bist {
    103. 

  103. 	uint64_t u64;
    104. 

  104. 	struct cvmx_ciu_bist_s {
    105. 

  105. 		uint64_t reserved_4_63:60;
    106. 

  106. 		uint64_t bist:4;
    107. 

  107. 	} s;
    108. 

  108. 	struct cvmx_ciu_bist_s cn30xx;
    109. 

  109. 	struct cvmx_ciu_bist_s cn31xx;
    110. 

  110. 	struct cvmx_ciu_bist_s cn38xx;
    111. 

  111. 	struct cvmx_ciu_bist_s cn38xxp2;
    112. 

  112. 	struct cvmx_ciu_bist_cn50xx {
    113. 

  113. 		uint64_t reserved_2_63:62;
    114. 

  114. 		uint64_t bist:2;
    115. 

  115. 	} cn50xx;
    116. 

  116. 	struct cvmx_ciu_bist_cn52xx {
    117. 

  117. 		uint64_t reserved_3_63:61;
    118. 

  118. 		uint64_t bist:3;
    119. 

  119. 	} cn52xx;
    120. 

  120. 	struct cvmx_ciu_bist_cn52xx cn52xxp1;
    121. 

  121. 	struct cvmx_ciu_bist_s cn56xx;
    122. 

  122. 	struct cvmx_ciu_bist_s cn56xxp1;
    123. 

  123. 	struct cvmx_ciu_bist_s cn58xx;
    124. 

  124. 	struct cvmx_ciu_bist_s cn58xxp1;
    125. 

  125. };
    126. 

  126. 

  127. union cvmx_ciu_dint {
    128. 

  128. 	uint64_t u64;
    129. 

  129. 	struct cvmx_ciu_dint_s {
    130. 

  130. 		uint64_t reserved_16_63:48;
    131. 

  131. 		uint64_t dint:16;
    132. 

  132. 	} s;
    133. 

  133. 	struct cvmx_ciu_dint_cn30xx {
    134. 

  134. 		uint64_t reserved_1_63:63;
    135. 

  135. 		uint64_t dint:1;
    136. 

  136. 	} cn30xx;
    137. 

  137. 	struct cvmx_ciu_dint_cn31xx {
    138. 

  138. 		uint64_t reserved_2_63:62;
    139. 

  139. 		uint64_t dint:2;
    140. 

  140. 	} cn31xx;
    141. 

  141. 	struct cvmx_ciu_dint_s cn38xx;
    142. 

  142. 	struct cvmx_ciu_dint_s cn38xxp2;
    143. 

  143. 	struct cvmx_ciu_dint_cn31xx cn50xx;
    144. 

  144. 	struct cvmx_ciu_dint_cn52xx {
    145. 

  145. 		uint64_t reserved_4_63:60;
    146. 

  146. 		uint64_t dint:4;
    147. 

  147. 	} cn52xx;
    148. 

  148. 	struct cvmx_ciu_dint_cn52xx cn52xxp1;
    149. 

  149. 	struct cvmx_ciu_dint_cn56xx {
    150. 

  150. 		uint64_t reserved_12_63:52;
    151. 

  151. 		uint64_t dint:12;
    152. 

  152. 	} cn56xx;
    153. 

  153. 	struct cvmx_ciu_dint_cn56xx cn56xxp1;
    154. 

  154. 	struct cvmx_ciu_dint_s cn58xx;
    155. 

  155. 	struct cvmx_ciu_dint_s cn58xxp1;
    156. 

  156. };
    157. 

  157. 

  158. union cvmx_ciu_fuse {
    159. 

  159. 	uint64_t u64;
    160. 

  160. 	struct cvmx_ciu_fuse_s {
    161. 

  161. 		uint64_t reserved_16_63:48;
    162. 

  162. 		uint64_t fuse:16;
    163. 

  163. 	} s;
    164. 

  164. 	struct cvmx_ciu_fuse_cn30xx {
    165. 

  165. 		uint64_t reserved_1_63:63;
    166. 

  166. 		uint64_t fuse:1;
    167. 

  167. 	} cn30xx;
    168. 

  168. 	struct cvmx_ciu_fuse_cn31xx {
    169. 

  169. 		uint64_t reserved_2_63:62;
    170. 

  170. 		uint64_t fuse:2;
    171. 

  171. 	} cn31xx;
    172. 

  172. 	struct cvmx_ciu_fuse_s cn38xx;
    173. 

  173. 	struct cvmx_ciu_fuse_s cn38xxp2;
    174. 

  174. 	struct cvmx_ciu_fuse_cn31xx cn50xx;
    175. 

  175. 	struct cvmx_ciu_fuse_cn52xx {
    176. 

  176. 		uint64_t reserved_4_63:60;
    177. 

  177. 		uint64_t fuse:4;
    178. 

  178. 	} cn52xx;
    179. 

  179. 	struct cvmx_ciu_fuse_cn52xx cn52xxp1;
    180. 

  180. 	struct cvmx_ciu_fuse_cn56xx {
    181. 

  181. 		uint64_t reserved_12_63:52;
    182. 

  182. 		uint64_t fuse:12;
    183. 

  183. 	} cn56xx;
    184. 

  184. 	struct cvmx_ciu_fuse_cn56xx cn56xxp1;
    185. 

  185. 	struct cvmx_ciu_fuse_s cn58xx;
    186. 

  186. 	struct cvmx_ciu_fuse_s cn58xxp1;
    187. 

  187. };
    188. 

  188. 

  189. union cvmx_ciu_gstop {
    190. 

  190. 	uint64_t u64;
    191. 

  191. 	struct cvmx_ciu_gstop_s {
    192. 

  192. 		uint64_t reserved_1_63:63;
    193. 

  193. 		uint64_t gstop:1;
    194. 

  194. 	} s;
    195. 

  195. 	struct cvmx_ciu_gstop_s cn30xx;
    196. 

  196. 	struct cvmx_ciu_gstop_s cn31xx;
    197. 

  197. 	struct cvmx_ciu_gstop_s cn38xx;
    198. 

  198. 	struct cvmx_ciu_gstop_s cn38xxp2;
    199. 

  199. 	struct cvmx_ciu_gstop_s cn50xx;
    200. 

  200. 	struct cvmx_ciu_gstop_s cn52xx;
    201. 

  201. 	struct cvmx_ciu_gstop_s cn52xxp1;
    202. 

  202. 	struct cvmx_ciu_gstop_s cn56xx;
    203. 

  203. 	struct cvmx_ciu_gstop_s cn56xxp1;
    204. 

  204. 	struct cvmx_ciu_gstop_s cn58xx;
    205. 

  205. 	struct cvmx_ciu_gstop_s cn58xxp1;
    206. 

  206. };
    207. 

  207. 

  208. union cvmx_ciu_intx_en0 {
    209. 

  209. 	uint64_t u64;
    210. 

  210. 	struct cvmx_ciu_intx_en0_s {
    211. 

  211. 		uint64_t bootdma:1;
    212. 

  212. 		uint64_t mii:1;
    213. 

  213. 		uint64_t ipdppthr:1;
    214. 

  214. 		uint64_t powiq:1;
    215. 

  215. 		uint64_t twsi2:1;
    216. 

  216. 		uint64_t mpi:1;
    217. 

  217. 		uint64_t pcm:1;
    218. 

  218. 		uint64_t usb:1;
    219. 

  219. 		uint64_t timer:4;
    220. 

  220. 		uint64_t key_zero:1;
    221. 

  221. 		uint64_t ipd_drp:1;
    222. 

  222. 		uint64_t gmx_drp:2;
    223. 

  223. 		uint64_t trace:1;
    224. 

  224. 		uint64_t rml:1;
    225. 

  225. 		uint64_t twsi:1;
    226. 

  226. 		uint64_t reserved_44_44:1;
    227. 

  227. 		uint64_t pci_msi:4;
    228. 

  228. 		uint64_t pci_int:4;
    229. 

  229. 		uint64_t uart:2;
    230. 

  230. 		uint64_t mbox:2;
    231. 

  231. 		uint64_t gpio:16;
    232. 

  232. 		uint64_t workq:16;
    233. 

  233. 	} s;
    234. 

  234. 	struct cvmx_ciu_intx_en0_cn30xx {
    235. 

  235. 		uint64_t reserved_59_63:5;
    236. 

  236. 		uint64_t mpi:1;
    237. 

  237. 		uint64_t pcm:1;
    238. 

  238. 		uint64_t usb:1;
    239. 

  239. 		uint64_t timer:4;
    240. 

  240. 		uint64_t reserved_51_51:1;
    241. 

  241. 		uint64_t ipd_drp:1;
    242. 

  242. 		uint64_t reserved_49_49:1;
    243. 

  243. 		uint64_t gmx_drp:1;
    244. 

  244. 		uint64_t reserved_47_47:1;
    245. 

  245. 		uint64_t rml:1;
    246. 

  246. 		uint64_t twsi:1;
    247. 

  247. 		uint64_t reserved_44_44:1;
    248. 

  248. 		uint64_t pci_msi:4;
    249. 

  249. 		uint64_t pci_int:4;
    250. 

  250. 		uint64_t uart:2;
    251. 

  251. 		uint64_t mbox:2;
    252. 

  252. 		uint64_t gpio:16;
    253. 

  253. 		uint64_t workq:16;
    254. 

  254. 	} cn30xx;
    255. 

  255. 	struct cvmx_ciu_intx_en0_cn31xx {
    256. 

  256. 		uint64_t reserved_59_63:5;
    257. 

  257. 		uint64_t mpi:1;
    258. 

  258. 		uint64_t pcm:1;
    259. 

  259. 		uint64_t usb:1;
    260. 

  260. 		uint64_t timer:4;
    261. 

  261. 		uint64_t reserved_51_51:1;
    262. 

  262. 		uint64_t ipd_drp:1;
    263. 

  263. 		uint64_t reserved_49_49:1;
    264. 

  264. 		uint64_t gmx_drp:1;
    265. 

  265. 		uint64_t trace:1;
    266. 

  266. 		uint64_t rml:1;
    267. 

  267. 		uint64_t twsi:1;
    268. 

  268. 		uint64_t reserved_44_44:1;
    269. 

  269. 		uint64_t pci_msi:4;
    270. 

  270. 		uint64_t pci_int:4;
    271. 

  271. 		uint64_t uart:2;
    272. 

  272. 		uint64_t mbox:2;
    273. 

  273. 		uint64_t gpio:16;
    274. 

  274. 		uint64_t workq:16;
    275. 

  275. 	} cn31xx;
    276. 

  276. 	struct cvmx_ciu_intx_en0_cn38xx {
    277. 

  277. 		uint64_t reserved_56_63:8;
    278. 

  278. 		uint64_t timer:4;
    279. 

  279. 		uint64_t key_zero:1;
    280. 

  280. 		uint64_t ipd_drp:1;
    281. 

  281. 		uint64_t gmx_drp:2;
    282. 

  282. 		uint64_t trace:1;
    283. 

  283. 		uint64_t rml:1;
    284. 

  284. 		uint64_t twsi:1;
    285. 

  285. 		uint64_t reserved_44_44:1;
    286. 

  286. 		uint64_t pci_msi:4;
    287. 

  287. 		uint64_t pci_int:4;
    288. 

  288. 		uint64_t uart:2;
    289. 

  289. 		uint64_t mbox:2;
    290. 

  290. 		uint64_t gpio:16;
    291. 

  291. 		uint64_t workq:16;
    292. 

  292. 	} cn38xx;
    293. 

  293. 	struct cvmx_ciu_intx_en0_cn38xx cn38xxp2;
    294. 

  294. 	struct cvmx_ciu_intx_en0_cn30xx cn50xx;
    295. 

  295. 	struct cvmx_ciu_intx_en0_cn52xx {
    296. 

  296. 		uint64_t bootdma:1;
    297. 

  297. 		uint64_t mii:1;
    298. 

  298. 		uint64_t ipdppthr:1;
    299. 

  299. 		uint64_t powiq:1;
    300. 

  300. 		uint64_t twsi2:1;
    301. 

  301. 		uint64_t reserved_57_58:2;
    302. 

  302. 		uint64_t usb:1;
    303. 

  303. 		uint64_t timer:4;
    304. 

  304. 		uint64_t reserved_51_51:1;
    305. 

  305. 		uint64_t ipd_drp:1;
    306. 

  306. 		uint64_t reserved_49_49:1;
    307. 

  307. 		uint64_t gmx_drp:1;
    308. 

  308. 		uint64_t trace:1;
    309. 

  309. 		uint64_t rml:1;
    310. 

  310. 		uint64_t twsi:1;
    311. 

  311. 		uint64_t reserved_44_44:1;
    312. 

  312. 		uint64_t pci_msi:4;
    313. 

  313. 		uint64_t pci_int:4;
    314. 

  314. 		uint64_t uart:2;
    315. 

  315. 		uint64_t mbox:2;
    316. 

  316. 		uint64_t gpio:16;
    317. 

  317. 		uint64_t workq:16;
    318. 

  318. 	} cn52xx;
    319. 

  319. 	struct cvmx_ciu_intx_en0_cn52xx cn52xxp1;
    320. 

  320. 	struct cvmx_ciu_intx_en0_cn56xx {
    321. 

  321. 		uint64_t bootdma:1;
    322. 

  322. 		uint64_t mii:1;
    323. 

  323. 		uint64_t ipdppthr:1;
    324. 

  324. 		uint64_t powiq:1;
    325. 

  325. 		uint64_t twsi2:1;
    326. 

  326. 		uint64_t reserved_57_58:2;
    327. 

  327. 		uint64_t usb:1;
    328. 

  328. 		uint64_t timer:4;
    329. 

  329. 		uint64_t key_zero:1;
    330. 

  330. 		uint64_t ipd_drp:1;
    331. 

  331. 		uint64_t gmx_drp:2;
    332. 

  332. 		uint64_t trace:1;
    333. 

  333. 		uint64_t rml:1;
    334. 

  334. 		uint64_t twsi:1;
    335. 

  335. 		uint64_t reserved_44_44:1;
    336. 

  336. 		uint64_t pci_msi:4;
    337. 

  337. 		uint64_t pci_int:4;
    338. 

  338. 		uint64_t uart:2;
    339. 

  339. 		uint64_t mbox:2;
    340. 

  340. 		uint64_t gpio:16;
    341. 

  341. 		uint64_t workq:16;
    342. 

  342. 	} cn56xx;
    343. 

  343. 	struct cvmx_ciu_intx_en0_cn56xx cn56xxp1;
    344. 

  344. 	struct cvmx_ciu_intx_en0_cn38xx cn58xx;
    345. 

  345. 	struct cvmx_ciu_intx_en0_cn38xx cn58xxp1;
    346. 

  346. };
    347. 

  347. 

  348. union cvmx_ciu_intx_en0_w1c {
    349. 

  349. 	uint64_t u64;
    350. 

  350. 	struct cvmx_ciu_intx_en0_w1c_s {
    351. 

  351. 		uint64_t bootdma:1;
    352. 

  352. 		uint64_t mii:1;
    353. 

  353. 		uint64_t ipdppthr:1;
    354. 

  354. 		uint64_t powiq:1;
    355. 

  355. 		uint64_t twsi2:1;
    356. 

  356. 		uint64_t reserved_57_58:2;
    357. 

  357. 		uint64_t usb:1;
    358. 

  358. 		uint64_t timer:4;
    359. 

  359. 		uint64_t key_zero:1;
    360. 

  360. 		uint64_t ipd_drp:1;
    361. 

  361. 		uint64_t gmx_drp:2;
    362. 

  362. 		uint64_t trace:1;
    363. 

  363. 		uint64_t rml:1;
    364. 

  364. 		uint64_t twsi:1;
    365. 

  365. 		uint64_t reserved_44_44:1;
    366. 

  366. 		uint64_t pci_msi:4;
    367. 

  367. 		uint64_t pci_int:4;
    368. 

  368. 		uint64_t uart:2;
    369. 

  369. 		uint64_t mbox:2;
    370. 

  370. 		uint64_t gpio:16;
    371. 

  371. 		uint64_t workq:16;
    372. 

  372. 	} s;
    373. 

  373. 	struct cvmx_ciu_intx_en0_w1c_cn52xx {
    374. 

  374. 		uint64_t bootdma:1;
    375. 

  375. 		uint64_t mii:1;
    376. 

  376. 		uint64_t ipdppthr:1;
    377. 

  377. 		uint64_t powiq:1;
    378. 

  378. 		uint64_t twsi2:1;
    379. 

  379. 		uint64_t reserved_57_58:2;
    380. 

  380. 		uint64_t usb:1;
    381. 

  381. 		uint64_t timer:4;
    382. 

  382. 		uint64_t reserved_51_51:1;
    383. 

  383. 		uint64_t ipd_drp:1;
    384. 

  384. 		uint64_t reserved_49_49:1;
    385. 

  385. 		uint64_t gmx_drp:1;
    386. 

  386. 		uint64_t trace:1;
    387. 

  387. 		uint64_t rml:1;
    388. 

  388. 		uint64_t twsi:1;
    389. 

  389. 		uint64_t reserved_44_44:1;
    390. 

  390. 		uint64_t pci_msi:4;
    391. 

  391. 		uint64_t pci_int:4;
    392. 

  392. 		uint64_t uart:2;
    393. 

  393. 		uint64_t mbox:2;
    394. 

  394. 		uint64_t gpio:16;
    395. 

  395. 		uint64_t workq:16;
    396. 

  396. 	} cn52xx;
    397. 

  397. 	struct cvmx_ciu_intx_en0_w1c_s cn56xx;
    398. 

  398. 	struct cvmx_ciu_intx_en0_w1c_cn58xx {
    399. 

  399. 		uint64_t reserved_56_63:8;
    400. 

  400. 		uint64_t timer:4;
    401. 

  401. 		uint64_t key_zero:1;
    402. 

  402. 		uint64_t ipd_drp:1;
    403. 

  403. 		uint64_t gmx_drp:2;
    404. 

  404. 		uint64_t trace:1;
    405. 

  405. 		uint64_t rml:1;
    406. 

  406. 		uint64_t twsi:1;
    407. 

  407. 		uint64_t reserved_44_44:1;
    408. 

  408. 		uint64_t pci_msi:4;
    409. 

  409. 		uint64_t pci_int:4;
    410. 

  410. 		uint64_t uart:2;
    411. 

  411. 		uint64_t mbox:2;
    412. 

  412. 		uint64_t gpio:16;
    413. 

  413. 		uint64_t workq:16;
    414. 

  414. 	} cn58xx;
    415. 

  415. };
    416. 

  416. 

  417. union cvmx_ciu_intx_en0_w1s {
    418. 

  418. 	uint64_t u64;
    419. 

  419. 	struct cvmx_ciu_intx_en0_w1s_s {
    420. 

  420. 		uint64_t bootdma:1;
    421. 

  421. 		uint64_t mii:1;
    422. 

  422. 		uint64_t ipdppthr:1;
    423. 

  423. 		uint64_t powiq:1;
    424. 

  424. 		uint64_t twsi2:1;
    425. 

  425. 		uint64_t reserved_57_58:2;
    426. 

  426. 		uint64_t usb:1;
    427. 

  427. 		uint64_t timer:4;
    428. 

  428. 		uint64_t key_zero:1;
    429. 

  429. 		uint64_t ipd_drp:1;
    430. 

  430. 		uint64_t gmx_drp:2;
    431. 

  431. 		uint64_t trace:1;
    432. 

  432. 		uint64_t rml:1;
    433. 

  433. 		uint64_t twsi:1;
    434. 

  434. 		uint64_t reserved_44_44:1;
    435. 

  435. 		uint64_t pci_msi:4;
    436. 

  436. 		uint64_t pci_int:4;
    437. 

  437. 		uint64_t uart:2;
    438. 

  438. 		uint64_t mbox:2;
    439. 

  439. 		uint64_t gpio:16;
    440. 

  440. 		uint64_t workq:16;
    441. 

  441. 	} s;
    442. 

  442. 	struct cvmx_ciu_intx_en0_w1s_cn52xx {
    443. 

  443. 		uint64_t bootdma:1;
    444. 

  444. 		uint64_t mii:1;
    445. 

  445. 		uint64_t ipdppthr:1;
    446. 

  446. 		uint64_t powiq:1;
    447. 

  447. 		uint64_t twsi2:1;
    448. 

  448. 		uint64_t reserved_57_58:2;
    449. 

  449. 		uint64_t usb:1;
    450. 

  450. 		uint64_t timer:4;
    451. 

  451. 		uint64_t reserved_51_51:1;
    452. 

  452. 		uint64_t ipd_drp:1;
    453. 

  453. 		uint64_t reserved_49_49:1;
    454. 

  454. 		uint64_t gmx_drp:1;
    455. 

  455. 		uint64_t trace:1;
    456. 

  456. 		uint64_t rml:1;
    457. 

  457. 		uint64_t twsi:1;
    458. 

  458. 		uint64_t reserved_44_44:1;
    459. 

  459. 		uint64_t pci_msi:4;
    460. 

  460. 		uint64_t pci_int:4;
    461. 

  461. 		uint64_t uart:2;
    462. 

  462. 		uint64_t mbox:2;
    463. 

  463. 		uint64_t gpio:16;
    464. 

  464. 		uint64_t workq:16;
    465. 

  465. 	} cn52xx;
    466. 

  466. 	struct cvmx_ciu_intx_en0_w1s_s cn56xx;
    467. 

  467. 	struct cvmx_ciu_intx_en0_w1s_cn58xx {
    468. 

  468. 		uint64_t reserved_56_63:8;
    469. 

  469. 		uint64_t timer:4;
    470. 

  470. 		uint64_t key_zero:1;
    471. 

  471. 		uint64_t ipd_drp:1;
    472. 

  472. 		uint64_t gmx_drp:2;
    473. 

  473. 		uint64_t trace:1;
    474. 

  474. 		uint64_t rml:1;
    475. 

  475. 		uint64_t twsi:1;
    476. 

  476. 		uint64_t reserved_44_44:1;
    477. 

  477. 		uint64_t pci_msi:4;
    478. 

  478. 		uint64_t pci_int:4;
    479. 

  479. 		uint64_t uart:2;
    480. 

  480. 		uint64_t mbox:2;
    481. 

  481. 		uint64_t gpio:16;
    482. 

  482. 		uint64_t workq:16;
    483. 

  483. 	} cn58xx;
    484. 

  484. };
    485. 

  485. 

  486. union cvmx_ciu_intx_en1 {
    487. 

  487. 	uint64_t u64;
    488. 

  488. 	struct cvmx_ciu_intx_en1_s {
    489. 

  489. 		uint64_t reserved_20_63:44;
    490. 

  490. 		uint64_t nand:1;
    491. 

  491. 		uint64_t mii1:1;
    492. 

  492. 		uint64_t usb1:1;
    493. 

  493. 		uint64_t uart2:1;
    494. 

  494. 		uint64_t wdog:16;
    495. 

  495. 	} s;
    496. 

  496. 	struct cvmx_ciu_intx_en1_cn30xx {
    497. 

  497. 		uint64_t reserved_1_63:63;
    498. 

  498. 		uint64_t wdog:1;
    499. 

  499. 	} cn30xx;
    500. 

  500. 	struct cvmx_ciu_intx_en1_cn31xx {
    501. 

  501. 		uint64_t reserved_2_63:62;
    502. 

  502. 		uint64_t wdog:2;
    503. 

  503. 	} cn31xx;
    504. 

  504. 	struct cvmx_ciu_intx_en1_cn38xx {
    505. 

  505. 		uint64_t reserved_16_63:48;
    506. 

  506. 		uint64_t wdog:16;
    507. 

  507. 	} cn38xx;
    508. 

  508. 	struct cvmx_ciu_intx_en1_cn38xx cn38xxp2;
    509. 

  509. 	struct cvmx_ciu_intx_en1_cn31xx cn50xx;
    510. 

  510. 	struct cvmx_ciu_intx_en1_cn52xx {
    511. 

  511. 		uint64_t reserved_20_63:44;
    512. 

  512. 		uint64_t nand:1;
    513. 

  513. 		uint64_t mii1:1;
    514. 

  514. 		uint64_t usb1:1;
    515. 

  515. 		uint64_t uart2:1;
    516. 

  516. 		uint64_t reserved_4_15:12;
    517. 

  517. 		uint64_t wdog:4;
    518. 

  518. 	} cn52xx;
    519. 

  519. 	struct cvmx_ciu_intx_en1_cn52xxp1 {
    520. 

  520. 		uint64_t reserved_19_63:45;
    521. 

  521. 		uint64_t mii1:1;
    522. 

  522. 		uint64_t usb1:1;
    523. 

  523. 		uint64_t uart2:1;
    524. 

  524. 		uint64_t reserved_4_15:12;
    525. 

  525. 		uint64_t wdog:4;
    526. 

  526. 	} cn52xxp1;
    527. 

  527. 	struct cvmx_ciu_intx_en1_cn56xx {
    528. 

  528. 		uint64_t reserved_12_63:52;
    529. 

  529. 		uint64_t wdog:12;
    530. 

  530. 	} cn56xx;
    531. 

  531. 	struct cvmx_ciu_intx_en1_cn56xx cn56xxp1;
    532. 

  532. 	struct cvmx_ciu_intx_en1_cn38xx cn58xx;
    533. 

  533. 	struct cvmx_ciu_intx_en1_cn38xx cn58xxp1;
    534. 

  534. };
    535. 

  535. 

  536. union cvmx_ciu_intx_en1_w1c {
    537. 

  537. 	uint64_t u64;
    538. 

  538. 	struct cvmx_ciu_intx_en1_w1c_s {
    539. 

  539. 		uint64_t reserved_20_63:44;
    540. 

  540. 		uint64_t nand:1;
    541. 

  541. 		uint64_t mii1:1;
    542. 

  542. 		uint64_t usb1:1;
    543. 

  543. 		uint64_t uart2:1;
    544. 

  544. 		uint64_t wdog:16;
    545. 

  545. 	} s;
    546. 

  546. 	struct cvmx_ciu_intx_en1_w1c_cn52xx {
    547. 

  547. 		uint64_t reserved_20_63:44;
    548. 

  548. 		uint64_t nand:1;
    549. 

  549. 		uint64_t mii1:1;
    550. 

  550. 		uint64_t usb1:1;
    551. 

  551. 		uint64_t uart2:1;
    552. 

  552. 		uint64_t reserved_4_15:12;
    553. 

  553. 		uint64_t wdog:4;
    554. 

  554. 	} cn52xx;
    555. 

  555. 	struct cvmx_ciu_intx_en1_w1c_cn56xx {
    556. 

  556. 		uint64_t reserved_12_63:52;
    557. 

  557. 		uint64_t wdog:12;
    558. 

  558. 	} cn56xx;
    559. 

  559. 	struct cvmx_ciu_intx_en1_w1c_cn58xx {
    560. 

  560. 		uint64_t reserved_16_63:48;
    561. 

  561. 		uint64_t wdog:16;
    562. 

  562. 	} cn58xx;
    563. 

  563. };
    564. 

  564. 

  565. union cvmx_ciu_intx_en1_w1s {
    566. 

  566. 	uint64_t u64;
    567. 

  567. 	struct cvmx_ciu_intx_en1_w1s_s {
    568. 

  568. 		uint64_t reserved_20_63:44;
    569. 

  569. 		uint64_t nand:1;
    570. 

  570. 		uint64_t mii1:1;
    571. 

  571. 		uint64_t usb1:1;
    572. 

  572. 		uint64_t uart2:1;
    573. 

  573. 		uint64_t wdog:16;
    574. 

  574. 	} s;
    575. 

  575. 	struct cvmx_ciu_intx_en1_w1s_cn52xx {
    576. 

  576. 		uint64_t reserved_20_63:44;
    577. 

  577. 		uint64_t nand:1;
    578. 

  578. 		uint64_t mii1:1;
    579. 

  579. 		uint64_t usb1:1;
    580. 

  580. 		uint64_t uart2:1;
    581. 

  581. 		uint64_t reserved_4_15:12;
    582. 

  582. 		uint64_t wdog:4;
    583. 

  583. 	} cn52xx;
    584. 

  584. 	struct cvmx_ciu_intx_en1_w1s_cn56xx {
    585. 

  585. 		uint64_t reserved_12_63:52;
    586. 

  586. 		uint64_t wdog:12;
    587. 

  587. 	} cn56xx;
    588. 

  588. 	struct cvmx_ciu_intx_en1_w1s_cn58xx {
    589. 

  589. 		uint64_t reserved_16_63:48;
    590. 

  590. 		uint64_t wdog:16;
    591. 

  591. 	} cn58xx;
    592. 

  592. };
    593. 

  593. 

  594. union cvmx_ciu_intx_en4_0 {
    595. 

  595. 	uint64_t u64;
    596. 

  596. 	struct cvmx_ciu_intx_en4_0_s {
    597. 

  597. 		uint64_t bootdma:1;
    598. 

  598. 		uint64_t mii:1;
    599. 

  599. 		uint64_t ipdppthr:1;
    600. 

  600. 		uint64_t powiq:1;
    601. 

  601. 		uint64_t twsi2:1;
    602. 

  602. 		uint64_t mpi:1;
    603. 

  603. 		uint64_t pcm:1;
    604. 

  604. 		uint64_t usb:1;
    605. 

  605. 		uint64_t timer:4;
    606. 

  606. 		uint64_t key_zero:1;
    607. 

  607. 		uint64_t ipd_drp:1;
    608. 

  608. 		uint64_t gmx_drp:2;
    609. 

  609. 		uint64_t trace:1;
    610. 

  610. 		uint64_t rml:1;
    611. 

  611. 		uint64_t twsi:1;
    612. 

  612. 		uint64_t reserved_44_44:1;
    613. 

  613. 		uint64_t pci_msi:4;
    614. 

  614. 		uint64_t pci_int:4;
    615. 

  615. 		uint64_t uart:2;
    616. 

  616. 		uint64_t mbox:2;
    617. 

  617. 		uint64_t gpio:16;
    618. 

  618. 		uint64_t workq:16;
    619. 

  619. 	} s;
    620. 

  620. 	struct cvmx_ciu_intx_en4_0_cn50xx {
    621. 

  621. 		uint64_t reserved_59_63:5;
    622. 

  622. 		uint64_t mpi:1;
    623. 

  623. 		uint64_t pcm:1;
    624. 

  624. 		uint64_t usb:1;
    625. 

  625. 		uint64_t timer:4;
    626. 

  626. 		uint64_t reserved_51_51:1;
    627. 

  627. 		uint64_t ipd_drp:1;
    628. 

  628. 		uint64_t reserved_49_49:1;
    629. 

  629. 		uint64_t gmx_drp:1;
    630. 

  630. 		uint64_t reserved_47_47:1;
    631. 

  631. 		uint64_t rml:1;
    632. 

  632. 		uint64_t twsi:1;
    633. 

  633. 		uint64_t reserved_44_44:1;
    634. 

  634. 		uint64_t pci_msi:4;
    635. 

  635. 		uint64_t pci_int:4;
    636. 

  636. 		uint64_t uart:2;
    637. 

  637. 		uint64_t mbox:2;
    638. 

  638. 		uint64_t gpio:16;
    639. 

  639. 		uint64_t workq:16;
    640. 

  640. 	} cn50xx;
    641. 

  641. 	struct cvmx_ciu_intx_en4_0_cn52xx {
    642. 

  642. 		uint64_t bootdma:1;
    643. 

  643. 		uint64_t mii:1;
    644. 

  644. 		uint64_t ipdppthr:1;
    645. 

  645. 		uint64_t powiq:1;
    646. 

  646. 		uint64_t twsi2:1;
    647. 

  647. 		uint64_t reserved_57_58:2;
    648. 

  648. 		uint64_t usb:1;
    649. 

  649. 		uint64_t timer:4;
    650. 

  650. 		uint64_t reserved_51_51:1;
    651. 

  651. 		uint64_t ipd_drp:1;
    652. 

  652. 		uint64_t reserved_49_49:1;
    653. 

  653. 		uint64_t gmx_drp:1;
    654. 

  654. 		uint64_t trace:1;
    655. 

  655. 		uint64_t rml:1;
    656. 

  656. 		uint64_t twsi:1;
    657. 

  657. 		uint64_t reserved_44_44:1;
    658. 

  658. 		uint64_t pci_msi:4;
    659. 

  659. 		uint64_t pci_int:4;
    660. 

  660. 		uint64_t uart:2;
    661. 

  661. 		uint64_t mbox:2;
    662. 

  662. 		uint64_t gpio:16;
    663. 

  663. 		uint64_t workq:16;
    664. 

  664. 	} cn52xx;
    665. 

  665. 	struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1;
    666. 

  666. 	struct cvmx_ciu_intx_en4_0_cn56xx {
    667. 

  667. 		uint64_t bootdma:1;
    668. 

  668. 		uint64_t mii:1;
    669. 

  669. 		uint64_t ipdppthr:1;
    670. 

  670. 		uint64_t powiq:1;
    671. 

  671. 		uint64_t twsi2:1;
    672. 

  672. 		uint64_t reserved_57_58:2;
    673. 

  673. 		uint64_t usb:1;
    674. 

  674. 		uint64_t timer:4;
    675. 

  675. 		uint64_t key_zero:1;
    676. 

  676. 		uint64_t ipd_drp:1;
    677. 

  677. 		uint64_t gmx_drp:2;
    678. 

  678. 		uint64_t trace:1;
    679. 

  679. 		uint64_t rml:1;
    680. 

  680. 		uint64_t twsi:1;
    681. 

  681. 		uint64_t reserved_44_44:1;
    682. 

  682. 		uint64_t pci_msi:4;
    683. 

  683. 		uint64_t pci_int:4;
    684. 

  684. 		uint64_t uart:2;
    685. 

  685. 		uint64_t mbox:2;
    686. 

  686. 		uint64_t gpio:16;
    687. 

  687. 		uint64_t workq:16;
    688. 

  688. 	} cn56xx;
    689. 

  689. 	struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1;
    690. 

  690. 	struct cvmx_ciu_intx_en4_0_cn58xx {
    691. 

  691. 		uint64_t reserved_56_63:8;
    692. 

  692. 		uint64_t timer:4;
    693. 

  693. 		uint64_t key_zero:1;
    694. 

  694. 		uint64_t ipd_drp:1;
    695. 

  695. 		uint64_t gmx_drp:2;
    696. 

  696. 		uint64_t trace:1;
    697. 

  697. 		uint64_t rml:1;
    698. 

  698. 		uint64_t twsi:1;
    699. 

  699. 		uint64_t reserved_44_44:1;
    700. 

  700. 		uint64_t pci_msi:4;
    701. 

  701. 		uint64_t pci_int:4;
    702. 

  702. 		uint64_t uart:2;
    703. 

  703. 		uint64_t mbox:2;
    704. 

  704. 		uint64_t gpio:16;
    705. 

  705. 		uint64_t workq:16;
    706. 

  706. 	} cn58xx;
    707. 

  707. 	struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1;
    708. 

  708. };
    709. 

  709. 

  710. union cvmx_ciu_intx_en4_0_w1c {
    711. 

  711. 	uint64_t u64;
    712. 

  712. 	struct cvmx_ciu_intx_en4_0_w1c_s {
    713. 

  713. 		uint64_t bootdma:1;
    714. 

  714. 		uint64_t mii:1;
    715. 

  715. 		uint64_t ipdppthr:1;
    716. 

  716. 		uint64_t powiq:1;
    717. 

  717. 		uint64_t twsi2:1;
    718. 

  718. 		uint64_t reserved_57_58:2;
    719. 

  719. 		uint64_t usb:1;
    720. 

  720. 		uint64_t timer:4;
    721. 

  721. 		uint64_t key_zero:1;
    722. 

  722. 		uint64_t ipd_drp:1;
    723. 

  723. 		uint64_t gmx_drp:2;
    724. 

  724. 		uint64_t trace:1;
    725. 

  725. 		uint64_t rml:1;
    726. 

  726. 		uint64_t twsi:1;
    727. 

  727. 		uint64_t reserved_44_44:1;
    728. 

  728. 		uint64_t pci_msi:4;
    729. 

  729. 		uint64_t pci_int:4;
    730. 

  730. 		uint64_t uart:2;
    731. 

  731. 		uint64_t mbox:2;
    732. 

  732. 		uint64_t gpio:16;
    733. 

  733. 		uint64_t workq:16;
    734. 

  734. 	} s;
    735. 

  735. 	struct cvmx_ciu_intx_en4_0_w1c_cn52xx {
    736. 

  736. 		uint64_t bootdma:1;
    737. 

  737. 		uint64_t mii:1;
    738. 

  738. 		uint64_t ipdppthr:1;
    739. 

  739. 		uint64_t powiq:1;
    740. 

  740. 		uint64_t twsi2:1;
    741. 

  741. 		uint64_t reserved_57_58:2;
    742. 

  742. 		uint64_t usb:1;
    743. 

  743. 		uint64_t timer:4;
    744. 

  744. 		uint64_t reserved_51_51:1;
    745. 

  745. 		uint64_t ipd_drp:1;
    746. 

  746. 		uint64_t reserved_49_49:1;
    747. 

  747. 		uint64_t gmx_drp:1;
    748. 

  748. 		uint64_t trace:1;
    749. 

  749. 		uint64_t rml:1;
    750. 

  750. 		uint64_t twsi:1;
    751. 

  751. 		uint64_t reserved_44_44:1;
    752. 

  752. 		uint64_t pci_msi:4;
    753. 

  753. 		uint64_t pci_int:4;
    754. 

  754. 		uint64_t uart:2;
    755. 

  755. 		uint64_t mbox:2;
    756. 

  756. 		uint64_t gpio:16;
    757. 

  757. 		uint64_t workq:16;
    758. 

  758. 	} cn52xx;
    759. 

  759. 	struct cvmx_ciu_intx_en4_0_w1c_s cn56xx;
    760. 

  760. 	struct cvmx_ciu_intx_en4_0_w1c_cn58xx {
    761. 

  761. 		uint64_t reserved_56_63:8;
    762. 

  762. 		uint64_t timer:4;
    763. 

  763. 		uint64_t key_zero:1;
    764. 

  764. 		uint64_t ipd_drp:1;
    765. 

  765. 		uint64_t gmx_drp:2;
    766. 

  766. 		uint64_t trace:1;
    767. 

  767. 		uint64_t rml:1;
    768. 

  768. 		uint64_t twsi:1;
    769. 

  769. 		uint64_t reserved_44_44:1;
    770. 

  770. 		uint64_t pci_msi:4;
    771. 

  771. 		uint64_t pci_int:4;
    772. 

  772. 		uint64_t uart:2;
    773. 

  773. 		uint64_t mbox:2;
    774. 

  774. 		uint64_t gpio:16;
    775. 

  775. 		uint64_t workq:16;
    776. 

  776. 	} cn58xx;
    777. 

  777. };
    778. 

  778. 

  779. union cvmx_ciu_intx_en4_0_w1s {
    780. 

  780. 	uint64_t u64;
    781. 

  781. 	struct cvmx_ciu_intx_en4_0_w1s_s {
    782. 

  782. 		uint64_t bootdma:1;
    783. 

  783. 		uint64_t mii:1;
    784. 

  784. 		uint64_t ipdppthr:1;
    785. 

  785. 		uint64_t powiq:1;
    786. 

  786. 		uint64_t twsi2:1;
    787. 

  787. 		uint64_t reserved_57_58:2;
    788. 

  788. 		uint64_t usb:1;
    789. 

  789. 		uint64_t timer:4;
    790. 

  790. 		uint64_t key_zero:1;
    791. 

  791. 		uint64_t ipd_drp:1;
    792. 

  792. 		uint64_t gmx_drp:2;
    793. 

  793. 		uint64_t trace:1;
    794. 

  794. 		uint64_t rml:1;
    795. 

  795. 		uint64_t twsi:1;
    796. 

  796. 		uint64_t reserved_44_44:1;
    797. 

  797. 		uint64_t pci_msi:4;
    798. 

  798. 		uint64_t pci_int:4;
    799. 

  799. 		uint64_t uart:2;
    800. 

  800. 		uint64_t mbox:2;
    801. 

  801. 		uint64_t gpio:16;
    802. 

  802. 		uint64_t workq:16;
    803. 

  803. 	} s;
    804. 

  804. 	struct cvmx_ciu_intx_en4_0_w1s_cn52xx {
    805. 

  805. 		uint64_t bootdma:1;
    806. 

  806. 		uint64_t mii:1;
    807. 

  807. 		uint64_t ipdppthr:1;
    808. 

  808. 		uint64_t powiq:1;
    809. 

  809. 		uint64_t twsi2:1;
    810. 

  810. 		uint64_t reserved_57_58:2;
    811. 

  811. 		uint64_t usb:1;
    812. 

  812. 		uint64_t timer:4;
    813. 

  813. 		uint64_t reserved_51_51:1;
    814. 

  814. 		uint64_t ipd_drp:1;
    815. 

  815. 		uint64_t reserved_49_49:1;
    816. 

  816. 		uint64_t gmx_drp:1;
    817. 

  817. 		uint64_t trace:1;
    818. 

  818. 		uint64_t rml:1;
    819. 

  819. 		uint64_t twsi:1;
    820. 

  820. 		uint64_t reserved_44_44:1;
    821. 

  821. 		uint64_t pci_msi:4;
    822. 

  822. 		uint64_t pci_int:4;
    823. 

  823. 		uint64_t uart:2;
    824. 

  824. 		uint64_t mbox:2;
    825. 

  825. 		uint64_t gpio:16;
    826. 

  826. 		uint64_t workq:16;
    827. 

  827. 	} cn52xx;
    828. 

  828. 	struct cvmx_ciu_intx_en4_0_w1s_s cn56xx;
    829. 

  829. 	struct cvmx_ciu_intx_en4_0_w1s_cn58xx {
    830. 

  830. 		uint64_t reserved_56_63:8;
    831. 

  831. 		uint64_t timer:4;
    832. 

  832. 		uint64_t key_zero:1;
    833. 

  833. 		uint64_t ipd_drp:1;
    834. 

  834. 		uint64_t gmx_drp:2;
    835. 

  835. 		uint64_t trace:1;
    836. 

  836. 		uint64_t rml:1;
    837. 

  837. 		uint64_t twsi:1;
    838. 

  838. 		uint64_t reserved_44_44:1;
    839. 

  839. 		uint64_t pci_msi:4;
    840. 

  840. 		uint64_t pci_int:4;
    841. 

  841. 		uint64_t uart:2;
    842. 

  842. 		uint64_t mbox:2;
    843. 

  843. 		uint64_t gpio:16;
    844. 

  844. 		uint64_t workq:16;
    845. 

  845. 	} cn58xx;
    846. 

  846. };
    847. 

  847. 

  848. union cvmx_ciu_intx_en4_1 {
    849. 

  849. 	uint64_t u64;
    850. 

  850. 	struct cvmx_ciu_intx_en4_1_s {
    851. 

  851. 		uint64_t reserved_20_63:44;
    852. 

  852. 		uint64_t nand:1;
    853. 

  853. 		uint64_t mii1:1;
    854. 

  854. 		uint64_t usb1:1;
    855. 

  855. 		uint64_t uart2:1;
    856. 

  856. 		uint64_t wdog:16;
    857. 

  857. 	} s;
    858. 

  858. 	struct cvmx_ciu_intx_en4_1_cn50xx {
    859. 

  859. 		uint64_t reserved_2_63:62;
    860. 

  860. 		uint64_t wdog:2;
    861. 

  861. 	} cn50xx;
    862. 

  862. 	struct cvmx_ciu_intx_en4_1_cn52xx {
    863. 

  863. 		uint64_t reserved_20_63:44;
    864. 

  864. 		uint64_t nand:1;
    865. 

  865. 		uint64_t mii1:1;
    866. 

  866. 		uint64_t usb1:1;
    867. 

  867. 		uint64_t uart2:1;
    868. 

  868. 		uint64_t reserved_4_15:12;
    869. 

  869. 		uint64_t wdog:4;
    870. 

  870. 	} cn52xx;
    871. 

  871. 	struct cvmx_ciu_intx_en4_1_cn52xxp1 {
    872. 

  872. 		uint64_t reserved_19_63:45;
    873. 

  873. 		uint64_t mii1:1;
    874. 

  874. 		uint64_t usb1:1;
    875. 

  875. 		uint64_t uart2:1;
    876. 

  876. 		uint64_t reserved_4_15:12;
    877. 

  877. 		uint64_t wdog:4;
    878. 

  878. 	} cn52xxp1;
    879. 

  879. 	struct cvmx_ciu_intx_en4_1_cn56xx {
    880. 

  880. 		uint64_t reserved_12_63:52;
    881. 

  881. 		uint64_t wdog:12;
    882. 

  882. 	} cn56xx;
    883. 

  883. 	struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1;
    884. 

  884. 	struct cvmx_ciu_intx_en4_1_cn58xx {
    885. 

  885. 		uint64_t reserved_16_63:48;
    886. 

  886. 		uint64_t wdog:16;
    887. 

  887. 	} cn58xx;
    888. 

  888. 	struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1;
    889. 

  889. };
    890. 

  890. 

  891. union cvmx_ciu_intx_en4_1_w1c {
    892. 

  892. 	uint64_t u64;
    893. 

  893. 	struct cvmx_ciu_intx_en4_1_w1c_s {
    894. 

  894. 		uint64_t reserved_20_63:44;
    895. 

  895. 		uint64_t nand:1;
    896. 

  896. 		uint64_t mii1:1;
    897. 

  897. 		uint64_t usb1:1;
    898. 

  898. 		uint64_t uart2:1;
    899. 

  899. 		uint64_t wdog:16;
    900. 

  900. 	} s;
    901. 

  901. 	struct cvmx_ciu_intx_en4_1_w1c_cn52xx {
    902. 

  902. 		uint64_t reserved_20_63:44;
    903. 

  903. 		uint64_t nand:1;
    904. 

  904. 		uint64_t mii1:1;
    905. 

  905. 		uint64_t usb1:1;
    906. 

  906. 		uint64_t uart2:1;
    907. 

  907. 		uint64_t reserved_4_15:12;
    908. 

  908. 		uint64_t wdog:4;
    909. 

  909. 	} cn52xx;
    910. 

  910. 	struct cvmx_ciu_intx_en4_1_w1c_cn56xx {
    911. 

  911. 		uint64_t reserved_12_63:52;
    912. 

  912. 		uint64_t wdog:12;
    913. 

  913. 	} cn56xx;
    914. 

  914. 	struct cvmx_ciu_intx_en4_1_w1c_cn58xx {
    915. 

  915. 		uint64_t reserved_16_63:48;
    916. 

  916. 		uint64_t wdog:16;
    917. 

  917. 	} cn58xx;
    918. 

  918. };
    919. 

  919. 

  920. union cvmx_ciu_intx_en4_1_w1s {
    921. 

  921. 	uint64_t u64;
    922. 

  922. 	struct cvmx_ciu_intx_en4_1_w1s_s {
    923. 

  923. 		uint64_t reserved_20_63:44;
    924. 

  924. 		uint64_t nand:1;
    925. 

  925. 		uint64_t mii1:1;
    926. 

  926. 		uint64_t usb1:1;
    927. 

  927. 		uint64_t uart2:1;
    928. 

  928. 		uint64_t wdog:16;
    929. 

  929. 	} s;
    930. 

  930. 	struct cvmx_ciu_intx_en4_1_w1s_cn52xx {
    931. 

  931. 		uint64_t reserved_20_63:44;
    932. 

  932. 		uint64_t nand:1;
    933. 

  933. 		uint64_t mii1:1;
    934. 

  934. 		uint64_t usb1:1;
    935. 

  935. 		uint64_t uart2:1;
    936. 

  936. 		uint64_t reserved_4_15:12;
    937. 

  937. 		uint64_t wdog:4;
    938. 

  938. 	} cn52xx;
    939. 

  939. 	struct cvmx_ciu_intx_en4_1_w1s_cn56xx {
    940. 

  940. 		uint64_t reserved_12_63:52;
    941. 

  941. 		uint64_t wdog:12;
    942. 

  942. 	} cn56xx;
    943. 

  943. 	struct cvmx_ciu_intx_en4_1_w1s_cn58xx {
    944. 

  944. 		uint64_t reserved_16_63:48;
    945. 

  945. 		uint64_t wdog:16;
    946. 

  946. 	} cn58xx;
    947. 

  947. };
    948. 

  948. 

  949. union cvmx_ciu_intx_sum0 {
    950. 

  950. 	uint64_t u64;
    951. 

  951. 	struct cvmx_ciu_intx_sum0_s {
    952. 

  952. 		uint64_t bootdma:1;
    953. 

  953. 		uint64_t mii:1;
    954. 

  954. 		uint64_t ipdppthr:1;
    955. 

  955. 		uint64_t powiq:1;
    956. 

  956. 		uint64_t twsi2:1;
    957. 

  957. 		uint64_t mpi:1;
    958. 

  958. 		uint64_t pcm:1;
    959. 

  959. 		uint64_t usb:1;
    960. 

  960. 		uint64_t timer:4;
    961. 

  961. 		uint64_t key_zero:1;
    962. 

  962. 		uint64_t ipd_drp:1;
    963. 

  963. 		uint64_t gmx_drp:2;
    964. 

  964. 		uint64_t trace:1;
    965. 

  965. 		uint64_t rml:1;
    966. 

  966. 		uint64_t twsi:1;
    967. 

  967. 		uint64_t wdog_sum:1;
    968. 

  968. 		uint64_t pci_msi:4;
    969. 

  969. 		uint64_t pci_int:4;
    970. 

  970. 		uint64_t uart:2;
    971. 

  971. 		uint64_t mbox:2;
    972. 

  972. 		uint64_t gpio:16;
    973. 

  973. 		uint64_t workq:16;
    974. 

  974. 	} s;
    975. 

  975. 	struct cvmx_ciu_intx_sum0_cn30xx {
    976. 

  976. 		uint64_t reserved_59_63:5;
    977. 

  977. 		uint64_t mpi:1;
    978. 

  978. 		uint64_t pcm:1;
    979. 

  979. 		uint64_t usb:1;
    980. 

  980. 		uint64_t timer:4;
    981. 

  981. 		uint64_t reserved_51_51:1;
    982. 

  982. 		uint64_t ipd_drp:1;
    983. 

  983. 		uint64_t reserved_49_49:1;
    984. 

  984. 		uint64_t gmx_drp:1;
    985. 

  985. 		uint64_t reserved_47_47:1;
    986. 

  986. 		uint64_t rml:1;
    987. 

  987. 		uint64_t twsi:1;
    988. 

  988. 		uint64_t wdog_sum:1;
    989. 

  989. 		uint64_t pci_msi:4;
    990. 

  990. 		uint64_t pci_int:4;
    991. 

  991. 		uint64_t uart:2;
    992. 

  992. 		uint64_t mbox:2;
    993. 

  993. 		uint64_t gpio:16;
    994. 

  994. 		uint64_t workq:16;
    995. 

  995. 	} cn30xx;
    996. 

  996. 	struct cvmx_ciu_intx_sum0_cn31xx {
    997. 

  997. 		uint64_t reserved_59_63:5;
    998. 

  998. 		uint64_t mpi:1;
    999. 

  999. 		uint64_t pcm:1;
    1000. 

  1000. 		uint64_t usb:1;
    1001. 

  1001. 		uint64_t timer:4;
    1002. 

  1002. 		uint64_t reserved_51_51:1;
    1003. 

  1003. 		uint64_t ipd_drp:1;
    1004. 

  1004. 		uint64_t reserved_49_49:1;
    1005. 

  1005. 		uint64_t gmx_drp:1;
    1006. 

  1006. 		uint64_t trace:1;
    1007. 

  1007. 		uint64_t rml:1;
    1008. 

  1008. 		uint64_t twsi:1;
    1009. 

  1009. 		uint64_t wdog_sum:1;
    1010. 

  1010. 		uint64_t pci_msi:4;
    1011. 

  1011. 		uint64_t pci_int:4;
    1012. 

  1012. 		uint64_t uart:2;
    1013. 

  1013. 		uint64_t mbox:2;
    1014. 

  1014. 		uint64_t gpio:16;
    1015. 

  1015. 		uint64_t workq:16;
    1016. 

  1016. 	} cn31xx;
    1017. 

  1017. 	struct cvmx_ciu_intx_sum0_cn38xx {
    1018. 

  1018. 		uint64_t reserved_56_63:8;
    1019. 

  1019. 		uint64_t timer:4;
    1020. 

  1020. 		uint64_t key_zero:1;
    1021. 

  1021. 		uint64_t ipd_drp:1;
    1022. 

  1022. 		uint64_t gmx_drp:2;
    1023. 

  1023. 		uint64_t trace:1;
    1024. 

  1024. 		uint64_t rml:1;
    1025. 

  1025. 		uint64_t twsi:1;
    1026. 

  1026. 		uint64_t wdog_sum:1;
    1027. 

  1027. 		uint64_t pci_msi:4;
    1028. 

  1028. 		uint64_t pci_int:4;
    1029. 

  1029. 		uint64_t uart:2;
    1030. 

  1030. 		uint64_t mbox:2;
    1031. 

  1031. 		uint64_t gpio:16;
    1032. 

  1032. 		uint64_t workq:16;
    1033. 

  1033. 	} cn38xx;
    1034. 

  1034. 	struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2;
    1035. 

  1035. 	struct cvmx_ciu_intx_sum0_cn30xx cn50xx;
    1036. 

  1036. 	struct cvmx_ciu_intx_sum0_cn52xx {
    1037. 

  1037. 		uint64_t bootdma:1;
    1038. 

  1038. 		uint64_t mii:1;
    1039. 

  1039. 		uint64_t ipdppthr:1;
    1040. 

  1040. 		uint64_t powiq:1;
    1041. 

  1041. 		uint64_t twsi2:1;
    1042. 

  1042. 		uint64_t reserved_57_58:2;
    1043. 

  1043. 		uint64_t usb:1;
    1044. 

  1044. 		uint64_t timer:4;
    1045. 

  1045. 		uint64_t reserved_51_51:1;
    1046. 

  1046. 		uint64_t ipd_drp:1;
    1047. 

  1047. 		uint64_t reserved_49_49:1;
    1048. 

  1048. 		uint64_t gmx_drp:1;
    1049. 

  1049. 		uint64_t trace:1;
    1050. 

  1050. 		uint64_t rml:1;
    1051. 

  1051. 		uint64_t twsi:1;
    1052. 

  1052. 		uint64_t wdog_sum:1;
    1053. 

  1053. 		uint64_t pci_msi:4;
    1054. 

  1054. 		uint64_t pci_int:4;
    1055. 

  1055. 		uint64_t uart:2;
    1056. 

  1056. 		uint64_t mbox:2;
    1057. 

  1057. 		uint64_t gpio:16;
    1058. 

  1058. 		uint64_t workq:16;
    1059. 

  1059. 	} cn52xx;
    1060. 

  1060. 	struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1;
    1061. 

  1061. 	struct cvmx_ciu_intx_sum0_cn56xx {
    1062. 

  1062. 		uint64_t bootdma:1;
    1063. 

  1063. 		uint64_t mii:1;
    1064. 

  1064. 		uint64_t ipdppthr:1;
    1065. 

  1065. 		uint64_t powiq:1;
    1066. 

  1066. 		uint64_t twsi2:1;
    1067. 

  1067. 		uint64_t reserved_57_58:2;
    1068. 

  1068. 		uint64_t usb:1;
    1069. 

  1069. 		uint64_t timer:4;
    1070. 

  1070. 		uint64_t key_zero:1;
    1071. 

  1071. 		uint64_t ipd_drp:1;
    1072. 

  1072. 		uint64_t gmx_drp:2;
    1073. 

  1073. 		uint64_t trace:1;
    1074. 

  1074. 		uint64_t rml:1;
    1075. 

  1075. 		uint64_t twsi:1;
    1076. 

  1076. 		uint64_t wdog_sum:1;
    1077. 

  1077. 		uint64_t pci_msi:4;
    1078. 

  1078. 		uint64_t pci_int:4;
    1079. 

  1079. 		uint64_t uart:2;
    1080. 

  1080. 		uint64_t mbox:2;
    1081. 

  1081. 		uint64_t gpio:16;
    1082. 

  1082. 		uint64_t workq:16;
    1083. 

  1083. 	} cn56xx;
    1084. 

  1084. 	struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1;
    1085. 

  1085. 	struct cvmx_ciu_intx_sum0_cn38xx cn58xx;
    1086. 

  1086. 	struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1;
    1087. 

  1087. };
    1088. 

  1088. 

  1089. union cvmx_ciu_intx_sum4 {
    1090. 

  1090. 	uint64_t u64;
    1091. 

  1091. 	struct cvmx_ciu_intx_sum4_s {
    1092. 

  1092. 		uint64_t bootdma:1;
    1093. 

  1093. 		uint64_t mii:1;
    1094. 

  1094. 		uint64_t ipdppthr:1;
    1095. 

  1095. 		uint64_t powiq:1;
    1096. 

  1096. 		uint64_t twsi2:1;
    1097. 

  1097. 		uint64_t mpi:1;
    1098. 

  1098. 		uint64_t pcm:1;
    1099. 

  1099. 		uint64_t usb:1;
    1100. 

  1100. 		uint64_t timer:4;
    1101. 

  1101. 		uint64_t key_zero:1;
    1102. 

  1102. 		uint64_t ipd_drp:1;
    1103. 

  1103. 		uint64_t gmx_drp:2;
    1104. 

  1104. 		uint64_t trace:1;
    1105. 

  1105. 		uint64_t rml:1;
    1106. 

  1106. 		uint64_t twsi:1;
    1107. 

  1107. 		uint64_t wdog_sum:1;
    1108. 

  1108. 		uint64_t pci_msi:4;
    1109. 

  1109. 		uint64_t pci_int:4;
    1110. 

  1110. 		uint64_t uart:2;
    1111. 

  1111. 		uint64_t mbox:2;
    1112. 

  1112. 		uint64_t gpio:16;
    1113. 

  1113. 		uint64_t workq:16;
    1114. 

  1114. 	} s;
    1115. 

  1115. 	struct cvmx_ciu_intx_sum4_cn50xx {
    1116. 

  1116. 		uint64_t reserved_59_63:5;
    1117. 

  1117. 		uint64_t mpi:1;
    1118. 

  1118. 		uint64_t pcm:1;
    1119. 

  1119. 		uint64_t usb:1;
    1120. 

  1120. 		uint64_t timer:4;
    1121. 

  1121. 		uint64_t reserved_51_51:1;
    1122. 

  1122. 		uint64_t ipd_drp:1;
    1123. 

  1123. 		uint64_t reserved_49_49:1;
    1124. 

  1124. 		uint64_t gmx_drp:1;
    1125. 

  1125. 		uint64_t reserved_47_47:1;
    1126. 

  1126. 		uint64_t rml:1;
    1127. 

  1127. 		uint64_t twsi:1;
    1128. 

  1128. 		uint64_t wdog_sum:1;
    1129. 

  1129. 		uint64_t pci_msi:4;
    1130. 

  1130. 		uint64_t pci_int:4;
    1131. 

  1131. 		uint64_t uart:2;
    1132. 

  1132. 		uint64_t mbox:2;
    1133. 

  1133. 		uint64_t gpio:16;
    1134. 

  1134. 		uint64_t workq:16;
    1135. 

  1135. 	} cn50xx;
    1136. 

  1136. 	struct cvmx_ciu_intx_sum4_cn52xx {
    1137. 

  1137. 		uint64_t bootdma:1;
    1138. 

  1138. 		uint64_t mii:1;
    1139. 

  1139. 		uint64_t ipdppthr:1;
    1140. 

  1140. 		uint64_t powiq:1;
    1141. 

  1141. 		uint64_t twsi2:1;
    1142. 

  1142. 		uint64_t reserved_57_58:2;
    1143. 

  1143. 		uint64_t usb:1;
    1144. 

  1144. 		uint64_t timer:4;
    1145. 

  1145. 		uint64_t reserved_51_51:1;
    1146. 

  1146. 		uint64_t ipd_drp:1;
    1147. 

  1147. 		uint64_t reserved_49_49:1;
    1148. 

  1148. 		uint64_t gmx_drp:1;
    1149. 

  1149. 		uint64_t trace:1;
    1150. 

  1150. 		uint64_t rml:1;
    1151. 

  1151. 		uint64_t twsi:1;
    1152. 

  1152. 		uint64_t wdog_sum:1;
    1153. 

  1153. 		uint64_t pci_msi:4;
    1154. 

  1154. 		uint64_t pci_int:4;
    1155. 

  1155. 		uint64_t uart:2;
    1156. 

  1156. 		uint64_t mbox:2;
    1157. 

  1157. 		uint64_t gpio:16;
    1158. 

  1158. 		uint64_t workq:16;
    1159. 

  1159. 	} cn52xx;
    1160. 

  1160. 	struct cvmx_ciu_intx_sum4_cn52xx cn52xxp1;
    1161. 

  1161. 	struct cvmx_ciu_intx_sum4_cn56xx {
    1162. 

  1162. 		uint64_t bootdma:1;
    1163. 

  1163. 		uint64_t mii:1;
    1164. 

  1164. 		uint64_t ipdppthr:1;
    1165. 

  1165. 		uint64_t powiq:1;
    1166. 

  1166. 		uint64_t twsi2:1;
    1167. 

  1167. 		uint64_t reserved_57_58:2;
    1168. 

  1168. 		uint64_t usb:1;
    1169. 

  1169. 		uint64_t timer:4;
    1170. 

  1170. 		uint64_t key_zero:1;
    1171. 

  1171. 		uint64_t ipd_drp:1;
    1172. 

  1172. 		uint64_t gmx_drp:2;
    1173. 

  1173. 		uint64_t trace:1;
    1174. 

  1174. 		uint64_t rml:1;
    1175. 

  1175. 		uint64_t twsi:1;
    1176. 

  1176. 		uint64_t wdog_sum:1;
    1177. 

  1177. 		uint64_t pci_msi:4;
    1178. 

  1178. 		uint64_t pci_int:4;
    1179. 

  1179. 		uint64_t uart:2;
    1180. 

  1180. 		uint64_t mbox:2;
    1181. 

  1181. 		uint64_t gpio:16;
    1182. 

  1182. 		uint64_t workq:16;
    1183. 

  1183. 	} cn56xx;
    1184. 

  1184. 	struct cvmx_ciu_intx_sum4_cn56xx cn56xxp1;
    1185. 

  1185. 	struct cvmx_ciu_intx_sum4_cn58xx {
    1186. 

  1186. 		uint64_t reserved_56_63:8;
    1187. 

  1187. 		uint64_t timer:4;
    1188. 

  1188. 		uint64_t key_zero:1;
    1189. 

  1189. 		uint64_t ipd_drp:1;
    1190. 

  1190. 		uint64_t gmx_drp:2;
    1191. 

  1191. 		uint64_t trace:1;
    1192. 

  1192. 		uint64_t rml:1;
    1193. 

  1193. 		uint64_t twsi:1;
    1194. 

  1194. 		uint64_t wdog_sum:1;
    1195. 

  1195. 		uint64_t pci_msi:4;
    1196. 

  1196. 		uint64_t pci_int:4;
    1197. 

  1197. 		uint64_t uart:2;
    1198. 

  1198. 		uint64_t mbox:2;
    1199. 

  1199. 		uint64_t gpio:16;
    1200. 

  1200. 		uint64_t workq:16;
    1201. 

  1201. 	} cn58xx;
    1202. 

  1202. 	struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1;
    1203. 

  1203. };
    1204. 

  1204. 

  1205. union cvmx_ciu_int_sum1 {
    1206. 

  1206. 	uint64_t u64;
    1207. 

  1207. 	struct cvmx_ciu_int_sum1_s {
    1208. 

  1208. 		uint64_t reserved_20_63:44;
    1209. 

  1209. 		uint64_t nand:1;
    1210. 

  1210. 		uint64_t mii1:1;
    1211. 

  1211. 		uint64_t usb1:1;
    1212. 

  1212. 		uint64_t uart2:1;
    1213. 

  1213. 		uint64_t wdog:16;
    1214. 

  1214. 	} s;
    1215. 

  1215. 	struct cvmx_ciu_int_sum1_cn30xx {
    1216. 

  1216. 		uint64_t reserved_1_63:63;
    1217. 

  1217. 		uint64_t wdog:1;
    1218. 

  1218. 	} cn30xx;
    1219. 

  1219. 	struct cvmx_ciu_int_sum1_cn31xx {
    1220. 

  1220. 		uint64_t reserved_2_63:62;
    1221. 

  1221. 		uint64_t wdog:2;
    1222. 

  1222. 	} cn31xx;
    1223. 

  1223. 	struct cvmx_ciu_int_sum1_cn38xx {
    1224. 

  1224. 		uint64_t reserved_16_63:48;
    1225. 

  1225. 		uint64_t wdog:16;
    1226. 

  1226. 	} cn38xx;
    1227. 

  1227. 	struct cvmx_ciu_int_sum1_cn38xx cn38xxp2;
    1228. 

  1228. 	struct cvmx_ciu_int_sum1_cn31xx cn50xx;
    1229. 

  1229. 	struct cvmx_ciu_int_sum1_cn52xx {
    1230. 

  1230. 		uint64_t reserved_20_63:44;
    1231. 

  1231. 		uint64_t nand:1;
    1232. 

  1232. 		uint64_t mii1:1;
    1233. 

  1233. 		uint64_t usb1:1;
    1234. 

  1234. 		uint64_t uart2:1;
    1235. 

  1235. 		uint64_t reserved_4_15:12;
    1236. 

  1236. 		uint64_t wdog:4;
    1237. 

  1237. 	} cn52xx;
    1238. 

  1238. 	struct cvmx_ciu_int_sum1_cn52xxp1 {
    1239. 

  1239. 		uint64_t reserved_19_63:45;
    1240. 

  1240. 		uint64_t mii1:1;
    1241. 

  1241. 		uint64_t usb1:1;
    1242. 

  1242. 		uint64_t uart2:1;
    1243. 

  1243. 		uint64_t reserved_4_15:12;
    1244. 

  1244. 		uint64_t wdog:4;
    1245. 

  1245. 	} cn52xxp1;
    1246. 

  1246. 	struct cvmx_ciu_int_sum1_cn56xx {
    1247. 

  1247. 		uint64_t reserved_12_63:52;
    1248. 

  1248. 		uint64_t wdog:12;
    1249. 

  1249. 	} cn56xx;
    1250. 

  1250. 	struct cvmx_ciu_int_sum1_cn56xx cn56xxp1;
    1251. 

  1251. 	struct cvmx_ciu_int_sum1_cn38xx cn58xx;
    1252. 

  1252. 	struct cvmx_ciu_int_sum1_cn38xx cn58xxp1;
    1253. 

  1253. };
    1254. 

  1254. 

  1255. union cvmx_ciu_mbox_clrx {
    1256. 

  1256. 	uint64_t u64;
    1257. 

  1257. 	struct cvmx_ciu_mbox_clrx_s {
    1258. 

  1258. 		uint64_t reserved_32_63:32;
    1259. 

  1259. 		uint64_t bits:32;
    1260. 

  1260. 	} s;
    1261. 

  1261. 	struct cvmx_ciu_mbox_clrx_s cn30xx;
    1262. 

  1262. 	struct cvmx_ciu_mbox_clrx_s cn31xx;
    1263. 

  1263. 	struct cvmx_ciu_mbox_clrx_s cn38xx;
    1264. 

  1264. 	struct cvmx_ciu_mbox_clrx_s cn38xxp2;
    1265. 

  1265. 	struct cvmx_ciu_mbox_clrx_s cn50xx;
    1266. 

  1266. 	struct cvmx_ciu_mbox_clrx_s cn52xx;
    1267. 

  1267. 	struct cvmx_ciu_mbox_clrx_s cn52xxp1;
    1268. 

  1268. 	struct cvmx_ciu_mbox_clrx_s cn56xx;
    1269. 

  1269. 	struct cvmx_ciu_mbox_clrx_s cn56xxp1;
    1270. 

  1270. 	struct cvmx_ciu_mbox_clrx_s cn58xx;
    1271. 

  1271. 	struct cvmx_ciu_mbox_clrx_s cn58xxp1;
    1272. 

  1272. };
    1273. 

  1273. 

  1274. union cvmx_ciu_mbox_setx {
    1275. 

  1275. 	uint64_t u64;
    1276. 

  1276. 	struct cvmx_ciu_mbox_setx_s {
    1277. 

  1277. 		uint64_t reserved_32_63:32;
    1278. 

  1278. 		uint64_t bits:32;
    1279. 

  1279. 	} s;
    1280. 

  1280. 	struct cvmx_ciu_mbox_setx_s cn30xx;
    1281. 

  1281. 	struct cvmx_ciu_mbox_setx_s cn31xx;
    1282. 

  1282. 	struct cvmx_ciu_mbox_setx_s cn38xx;
    1283. 

  1283. 	struct cvmx_ciu_mbox_setx_s cn38xxp2;
    1284. 

  1284. 	struct cvmx_ciu_mbox_setx_s cn50xx;
    1285. 

  1285. 	struct cvmx_ciu_mbox_setx_s cn52xx;
    1286. 

  1286. 	struct cvmx_ciu_mbox_setx_s cn52xxp1;
    1287. 

  1287. 	struct cvmx_ciu_mbox_setx_s cn56xx;
    1288. 

  1288. 	struct cvmx_ciu_mbox_setx_s cn56xxp1;
    1289. 

  1289. 	struct cvmx_ciu_mbox_setx_s cn58xx;
    1290. 

  1290. 	struct cvmx_ciu_mbox_setx_s cn58xxp1;
    1291. 

  1291. };
    1292. 

  1292. 

  1293. union cvmx_ciu_nmi {
    1294. 

  1294. 	uint64_t u64;
    1295. 

  1295. 	struct cvmx_ciu_nmi_s {
    1296. 

  1296. 		uint64_t reserved_16_63:48;
    1297. 

  1297. 		uint64_t nmi:16;
    1298. 

  1298. 	} s;
    1299. 

  1299. 	struct cvmx_ciu_nmi_cn30xx {
    1300. 

  1300. 		uint64_t reserved_1_63:63;
    1301. 

  1301. 		uint64_t nmi:1;
    1302. 

  1302. 	} cn30xx;
    1303. 

  1303. 	struct cvmx_ciu_nmi_cn31xx {
    1304. 

  1304. 		uint64_t reserved_2_63:62;
    1305. 

  1305. 		uint64_t nmi:2;
    1306. 

  1306. 	} cn31xx;
    1307. 

  1307. 	struct cvmx_ciu_nmi_s cn38xx;
    1308. 

  1308. 	struct cvmx_ciu_nmi_s cn38xxp2;
    1309. 

  1309. 	struct cvmx_ciu_nmi_cn31xx cn50xx;
    1310. 

  1310. 	struct cvmx_ciu_nmi_cn52xx {
    1311. 

  1311. 		uint64_t reserved_4_63:60;
    1312. 

  1312. 		uint64_t nmi:4;
    1313. 

  1313. 	} cn52xx;
    1314. 

  1314. 	struct cvmx_ciu_nmi_cn52xx cn52xxp1;
    1315. 

  1315. 	struct cvmx_ciu_nmi_cn56xx {
    1316. 

  1316. 		uint64_t reserved_12_63:52;
    1317. 

  1317. 		uint64_t nmi:12;
    1318. 

  1318. 	} cn56xx;
    1319. 

  1319. 	struct cvmx_ciu_nmi_cn56xx cn56xxp1;
    1320. 

  1320. 	struct cvmx_ciu_nmi_s cn58xx;
    1321. 

  1321. 	struct cvmx_ciu_nmi_s cn58xxp1;
    1322. 

  1322. };
    1323. 

  1323. 

  1324. union cvmx_ciu_pci_inta {
    1325. 

  1325. 	uint64_t u64;
    1326. 

  1326. 	struct cvmx_ciu_pci_inta_s {
    1327. 

  1327. 		uint64_t reserved_2_63:62;
    1328. 

  1328. 		uint64_t intr:2;
    1329. 

  1329. 	} s;
    1330. 

  1330. 	struct cvmx_ciu_pci_inta_s cn30xx;
    1331. 

  1331. 	struct cvmx_ciu_pci_inta_s cn31xx;
    1332. 

  1332. 	struct cvmx_ciu_pci_inta_s cn38xx;
    1333. 

  1333. 	struct cvmx_ciu_pci_inta_s cn38xxp2;
    1334. 

  1334. 	struct cvmx_ciu_pci_inta_s cn50xx;
    1335. 

  1335. 	struct cvmx_ciu_pci_inta_s cn52xx;
    1336. 

  1336. 	struct cvmx_ciu_pci_inta_s cn52xxp1;
    1337. 

  1337. 	struct cvmx_ciu_pci_inta_s cn56xx;
    1338. 

  1338. 	struct cvmx_ciu_pci_inta_s cn56xxp1;
    1339. 

  1339. 	struct cvmx_ciu_pci_inta_s cn58xx;
    1340. 

  1340. 	struct cvmx_ciu_pci_inta_s cn58xxp1;
    1341. 

  1341. };
    1342. 

  1342. 

  1343. union cvmx_ciu_pp_dbg {
    1344. 

  1344. 	uint64_t u64;
    1345. 

  1345. 	struct cvmx_ciu_pp_dbg_s {
    1346. 

  1346. 		uint64_t reserved_16_63:48;
    1347. 

  1347. 		uint64_t ppdbg:16;
    1348. 

  1348. 	} s;
    1349. 

  1349. 	struct cvmx_ciu_pp_dbg_cn30xx {
    1350. 

  1350. 		uint64_t reserved_1_63:63;
    1351. 

  1351. 		uint64_t ppdbg:1;
    1352. 

  1352. 	} cn30xx;
    1353. 

  1353. 	struct cvmx_ciu_pp_dbg_cn31xx {
    1354. 

  1354. 		uint64_t reserved_2_63:62;
    1355. 

  1355. 		uint64_t ppdbg:2;
    1356. 

  1356. 	} cn31xx;
    1357. 

  1357. 	struct cvmx_ciu_pp_dbg_s cn38xx;
    1358. 

  1358. 	struct cvmx_ciu_pp_dbg_s cn38xxp2;
    1359. 

  1359. 	struct cvmx_ciu_pp_dbg_cn31xx cn50xx;
    1360. 

  1360. 	struct cvmx_ciu_pp_dbg_cn52xx {
    1361. 

  1361. 		uint64_t reserved_4_63:60;
    1362. 

  1362. 		uint64_t ppdbg:4;
    1363. 

  1363. 	} cn52xx;
    1364. 

  1364. 	struct cvmx_ciu_pp_dbg_cn52xx cn52xxp1;
    1365. 

  1365. 	struct cvmx_ciu_pp_dbg_cn56xx {
    1366. 

  1366. 		uint64_t reserved_12_63:52;
    1367. 

  1367. 		uint64_t ppdbg:12;
    1368. 

  1368. 	} cn56xx;
    1369. 

  1369. 	struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1;
    1370. 

  1370. 	struct cvmx_ciu_pp_dbg_s cn58xx;
    1371. 

  1371. 	struct cvmx_ciu_pp_dbg_s cn58xxp1;
    1372. 

  1372. };
    1373. 

  1373. 

  1374. union cvmx_ciu_pp_pokex {
    1375. 

  1375. 	uint64_t u64;
    1376. 

  1376. 	struct cvmx_ciu_pp_pokex_s {
    1377. 

  1377. 		uint64_t reserved_0_63:64;
    1378. 

  1378. 	} s;
    1379. 

  1379. 	struct cvmx_ciu_pp_pokex_s cn30xx;
    1380. 

  1380. 	struct cvmx_ciu_pp_pokex_s cn31xx;
    1381. 

  1381. 	struct cvmx_ciu_pp_pokex_s cn38xx;
    1382. 

  1382. 	struct cvmx_ciu_pp_pokex_s cn38xxp2;
    1383. 

  1383. 	struct cvmx_ciu_pp_pokex_s cn50xx;
    1384. 

  1384. 	struct cvmx_ciu_pp_pokex_s cn52xx;
    1385. 

  1385. 	struct cvmx_ciu_pp_pokex_s cn52xxp1;
    1386. 

  1386. 	struct cvmx_ciu_pp_pokex_s cn56xx;
    1387. 

  1387. 	struct cvmx_ciu_pp_pokex_s cn56xxp1;
    1388. 

  1388. 	struct cvmx_ciu_pp_pokex_s cn58xx;
    1389. 

  1389. 	struct cvmx_ciu_pp_pokex_s cn58xxp1;
    1390. 

  1390. };
    1391. 

  1391. 

  1392. union cvmx_ciu_pp_rst {
    1393. 

  1393. 	uint64_t u64;
    1394. 

  1394. 	struct cvmx_ciu_pp_rst_s {
    1395. 

  1395. 		uint64_t reserved_16_63:48;
    1396. 

  1396. 		uint64_t rst:15;
    1397. 

  1397. 		uint64_t rst0:1;
    1398. 

  1398. 	} s;
    1399. 

  1399. 	struct cvmx_ciu_pp_rst_cn30xx {
    1400. 

  1400. 		uint64_t reserved_1_63:63;
    1401. 

  1401. 		uint64_t rst0:1;
    1402. 

  1402. 	} cn30xx;
    1403. 

  1403. 	struct cvmx_ciu_pp_rst_cn31xx {
    1404. 

  1404. 		uint64_t reserved_2_63:62;
    1405. 

  1405. 		uint64_t rst:1;
    1406. 

  1406. 		uint64_t rst0:1;
    1407. 

  1407. 	} cn31xx;
    1408. 

  1408. 	struct cvmx_ciu_pp_rst_s cn38xx;
    1409. 

  1409. 	struct cvmx_ciu_pp_rst_s cn38xxp2;
    1410. 

  1410. 	struct cvmx_ciu_pp_rst_cn31xx cn50xx;
    1411. 

  1411. 	struct cvmx_ciu_pp_rst_cn52xx {
    1412. 

  1412. 		uint64_t reserved_4_63:60;
    1413. 

  1413. 		uint64_t rst:3;
    1414. 

  1414. 		uint64_t rst0:1;
    1415. 

  1415. 	} cn52xx;
    1416. 

  1416. 	struct cvmx_ciu_pp_rst_cn52xx cn52xxp1;
    1417. 

  1417. 	struct cvmx_ciu_pp_rst_cn56xx {
    1418. 

  1418. 		uint64_t reserved_12_63:52;
    1419. 

  1419. 		uint64_t rst:11;
    1420. 

  1420. 		uint64_t rst0:1;
    1421. 

  1421. 	} cn56xx;
    1422. 

  1422. 	struct cvmx_ciu_pp_rst_cn56xx cn56xxp1;
    1423. 

  1423. 	struct cvmx_ciu_pp_rst_s cn58xx;
    1424. 

  1424. 	struct cvmx_ciu_pp_rst_s cn58xxp1;
    1425. 

  1425. };
    1426. 

  1426. 

  1427. union cvmx_ciu_qlm_dcok {
    1428. 

  1428. 	uint64_t u64;
    1429. 

  1429. 	struct cvmx_ciu_qlm_dcok_s {
    1430. 

  1430. 		uint64_t reserved_4_63:60;
    1431. 

  1431. 		uint64_t qlm_dcok:4;
    1432. 

  1432. 	} s;
    1433. 

  1433. 	struct cvmx_ciu_qlm_dcok_cn52xx {
    1434. 

  1434. 		uint64_t reserved_2_63:62;
    1435. 

  1435. 		uint64_t qlm_dcok:2;
    1436. 

  1436. 	} cn52xx;
    1437. 

  1437. 	struct cvmx_ciu_qlm_dcok_cn52xx cn52xxp1;
    1438. 

  1438. 	struct cvmx_ciu_qlm_dcok_s cn56xx;
    1439. 

  1439. 	struct cvmx_ciu_qlm_dcok_s cn56xxp1;
    1440. 

  1440. };
    1441. 

  1441. 

  1442. union cvmx_ciu_qlm_jtgc {
    1443. 

  1443. 	uint64_t u64;
    1444. 

  1444. 	struct cvmx_ciu_qlm_jtgc_s {
    1445. 

  1445. 		uint64_t reserved_11_63:53;
    1446. 

  1446. 		uint64_t clk_div:3;
    1447. 

  1447. 		uint64_t reserved_6_7:2;
    1448. 

  1448. 		uint64_t mux_sel:2;
    1449. 

  1449. 		uint64_t bypass:4;
    1450. 

  1450. 	} s;
    1451. 

  1451. 	struct cvmx_ciu_qlm_jtgc_cn52xx {
    1452. 

  1452. 		uint64_t reserved_11_63:53;
    1453. 

  1453. 		uint64_t clk_div:3;
    1454. 

  1454. 		uint64_t reserved_5_7:3;
    1455. 

  1455. 		uint64_t mux_sel:1;
    1456. 

  1456. 		uint64_t reserved_2_3:2;
    1457. 

  1457. 		uint64_t bypass:2;
    1458. 

  1458. 	} cn52xx;
    1459. 

  1459. 	struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1;
    1460. 

  1460. 	struct cvmx_ciu_qlm_jtgc_s cn56xx;
    1461. 

  1461. 	struct cvmx_ciu_qlm_jtgc_s cn56xxp1;
    1462. 

  1462. };
    1463. 

  1463. 

  1464. union cvmx_ciu_qlm_jtgd {
    1465. 

  1465. 	uint64_t u64;
    1466. 

  1466. 	struct cvmx_ciu_qlm_jtgd_s {
    1467. 

  1467. 		uint64_t capture:1;
    1468. 

  1468. 		uint64_t shift:1;
    1469. 

  1469. 		uint64_t update:1;
    1470. 

  1470. 		uint64_t reserved_44_60:17;
    1471. 

  1471. 		uint64_t select:4;
    1472. 

  1472. 		uint64_t reserved_37_39:3;
    1473. 

  1473. 		uint64_t shft_cnt:5;
    1474. 

  1474. 		uint64_t shft_reg:32;
    1475. 

  1475. 	} s;
    1476. 

  1476. 	struct cvmx_ciu_qlm_jtgd_cn52xx {
    1477. 

  1477. 		uint64_t capture:1;
    1478. 

  1478. 		uint64_t shift:1;
    1479. 

  1479. 		uint64_t update:1;
    1480. 

  1480. 		uint64_t reserved_42_60:19;
    1481. 

  1481. 		uint64_t select:2;
    1482. 

  1482. 		uint64_t reserved_37_39:3;
    1483. 

  1483. 		uint64_t shft_cnt:5;
    1484. 

  1484. 		uint64_t shft_reg:32;
    1485. 

  1485. 	} cn52xx;
    1486. 

  1486. 	struct cvmx_ciu_qlm_jtgd_cn52xx cn52xxp1;
    1487. 

  1487. 	struct cvmx_ciu_qlm_jtgd_s cn56xx;
    1488. 

  1488. 	struct cvmx_ciu_qlm_jtgd_cn56xxp1 {
    1489. 

  1489. 		uint64_t capture:1;
    1490. 

  1490. 		uint64_t shift:1;
    1491. 

  1491. 		uint64_t update:1;
    1492. 

  1492. 		uint64_t reserved_37_60:24;
    1493. 

  1493. 		uint64_t shft_cnt:5;
    1494. 

  1494. 		uint64_t shft_reg:32;
    1495. 

  1495. 	} cn56xxp1;
    1496. 

  1496. };
    1497. 

  1497. 

  1498. union cvmx_ciu_soft_bist {
    1499. 

  1499. 	uint64_t u64;
    1500. 

  1500. 	struct cvmx_ciu_soft_bist_s {
    1501. 

  1501. 		uint64_t reserved_1_63:63;
    1502. 

  1502. 		uint64_t soft_bist:1;
    1503. 

  1503. 	} s;
    1504. 

  1504. 	struct cvmx_ciu_soft_bist_s cn30xx;
    1505. 

  1505. 	struct cvmx_ciu_soft_bist_s cn31xx;
    1506. 

  1506. 	struct cvmx_ciu_soft_bist_s cn38xx;
    1507. 

  1507. 	struct cvmx_ciu_soft_bist_s cn38xxp2;
    1508. 

  1508. 	struct cvmx_ciu_soft_bist_s cn50xx;
    1509. 

  1509. 	struct cvmx_ciu_soft_bist_s cn52xx;
    1510. 

  1510. 	struct cvmx_ciu_soft_bist_s cn52xxp1;
    1511. 

  1511. 	struct cvmx_ciu_soft_bist_s cn56xx;
    1512. 

  1512. 	struct cvmx_ciu_soft_bist_s cn56xxp1;
    1513. 

  1513. 	struct cvmx_ciu_soft_bist_s cn58xx;
    1514. 

  1514. 	struct cvmx_ciu_soft_bist_s cn58xxp1;
    1515. 

  1515. };
    1516. 

  1516. 

  1517. union cvmx_ciu_soft_prst {
    1518. 

  1518. 	uint64_t u64;
    1519. 

  1519. 	struct cvmx_ciu_soft_prst_s {
    1520. 

  1520. 		uint64_t reserved_3_63:61;
    1521. 

  1521. 		uint64_t host64:1;
    1522. 

  1522. 		uint64_t npi:1;
    1523. 

  1523. 		uint64_t soft_prst:1;
    1524. 

  1524. 	} s;
    1525. 

  1525. 	struct cvmx_ciu_soft_prst_s cn30xx;
    1526. 

  1526. 	struct cvmx_ciu_soft_prst_s cn31xx;
    1527. 

  1527. 	struct cvmx_ciu_soft_prst_s cn38xx;
    1528. 

  1528. 	struct cvmx_ciu_soft_prst_s cn38xxp2;
    1529. 

  1529. 	struct cvmx_ciu_soft_prst_s cn50xx;
    1530. 

  1530. 	struct cvmx_ciu_soft_prst_cn52xx {
    1531. 

  1531. 		uint64_t reserved_1_63:63;
    1532. 

  1532. 		uint64_t soft_prst:1;
    1533. 

  1533. 	} cn52xx;
    1534. 

  1534. 	struct cvmx_ciu_soft_prst_cn52xx cn52xxp1;
    1535. 

  1535. 	struct cvmx_ciu_soft_prst_cn52xx cn56xx;
    1536. 

  1536. 	struct cvmx_ciu_soft_prst_cn52xx cn56xxp1;
    1537. 

  1537. 	struct cvmx_ciu_soft_prst_s cn58xx;
    1538. 

  1538. 	struct cvmx_ciu_soft_prst_s cn58xxp1;
    1539. 

  1539. };
    1540. 

  1540. 

  1541. union cvmx_ciu_soft_prst1 {
    1542. 

  1542. 	uint64_t u64;
    1543. 

  1543. 	struct cvmx_ciu_soft_prst1_s {
    1544. 

  1544. 		uint64_t reserved_1_63:63;
    1545. 

  1545. 		uint64_t soft_prst:1;
    1546. 

  1546. 	} s;
    1547. 

  1547. 	struct cvmx_ciu_soft_prst1_s cn52xx;
    1548. 

  1548. 	struct cvmx_ciu_soft_prst1_s cn52xxp1;
    1549. 

  1549. 	struct cvmx_ciu_soft_prst1_s cn56xx;
    1550. 

  1550. 	struct cvmx_ciu_soft_prst1_s cn56xxp1;
    1551. 

  1551. };
    1552. 

  1552. 

  1553. union cvmx_ciu_soft_rst {
    1554. 

  1554. 	uint64_t u64;
    1555. 

  1555. 	struct cvmx_ciu_soft_rst_s {
    1556. 

  1556. 		uint64_t reserved_1_63:63;
    1557. 

  1557. 		uint64_t soft_rst:1;
    1558. 

  1558. 	} s;
    1559. 

  1559. 	struct cvmx_ciu_soft_rst_s cn30xx;
    1560. 

  1560. 	struct cvmx_ciu_soft_rst_s cn31xx;
    1561. 

  1561. 	struct cvmx_ciu_soft_rst_s cn38xx;
    1562. 

  1562. 	struct cvmx_ciu_soft_rst_s cn38xxp2;
    1563. 

  1563. 	struct cvmx_ciu_soft_rst_s cn50xx;
    1564. 

  1564. 	struct cvmx_ciu_soft_rst_s cn52xx;
    1565. 

  1565. 	struct cvmx_ciu_soft_rst_s cn52xxp1;
    1566. 

  1566. 	struct cvmx_ciu_soft_rst_s cn56xx;
    1567. 

  1567. 	struct cvmx_ciu_soft_rst_s cn56xxp1;
    1568. 

  1568. 	struct cvmx_ciu_soft_rst_s cn58xx;
    1569. 

  1569. 	struct cvmx_ciu_soft_rst_s cn58xxp1;
    1570. 

  1570. };
    1571. 

  1571. 

  1572. union cvmx_ciu_timx {
    1573. 

  1573. 	uint64_t u64;
    1574. 

  1574. 	struct cvmx_ciu_timx_s {
    1575. 

  1575. 		uint64_t reserved_37_63:27;
    1576. 

  1576. 		uint64_t one_shot:1;
    1577. 

  1577. 		uint64_t len:36;
    1578. 

  1578. 	} s;
    1579. 

  1579. 	struct cvmx_ciu_timx_s cn30xx;
    1580. 

  1580. 	struct cvmx_ciu_timx_s cn31xx;
    1581. 

  1581. 	struct cvmx_ciu_timx_s cn38xx;
    1582. 

  1582. 	struct cvmx_ciu_timx_s cn38xxp2;
    1583. 

  1583. 	struct cvmx_ciu_timx_s cn50xx;
    1584. 

  1584. 	struct cvmx_ciu_timx_s cn52xx;
    1585. 

  1585. 	struct cvmx_ciu_timx_s cn52xxp1;
    1586. 

  1586. 	struct cvmx_ciu_timx_s cn56xx;
    1587. 

  1587. 	struct cvmx_ciu_timx_s cn56xxp1;
    1588. 

  1588. 	struct cvmx_ciu_timx_s cn58xx;
    1589. 

  1589. 	struct cvmx_ciu_timx_s cn58xxp1;
    1590. 

  1590. };
    1591. 

  1591. 

  1592. union cvmx_ciu_wdogx {
    1593. 

  1593. 	uint64_t u64;
    1594. 

  1594. 	struct cvmx_ciu_wdogx_s {
    1595. 

  1595. 		uint64_t reserved_46_63:18;
    1596. 

  1596. 		uint64_t gstopen:1;
    1597. 

  1597. 		uint64_t dstop:1;
    1598. 

  1598. 		uint64_t cnt:24;
    1599. 

  1599. 		uint64_t len:16;
    1600. 

  1600. 		uint64_t state:2;
    1601. 

  1601. 		uint64_t mode:2;
    1602. 

  1602. 	} s;
    1603. 

  1603. 	struct cvmx_ciu_wdogx_s cn30xx;
    1604. 

  1604. 	struct cvmx_ciu_wdogx_s cn31xx;
    1605. 

  1605. 	struct cvmx_ciu_wdogx_s cn38xx;
    1606. 

  1606. 	struct cvmx_ciu_wdogx_s cn38xxp2;
    1607. 

  1607. 	struct cvmx_ciu_wdogx_s cn50xx;
    1608. 

  1608. 	struct cvmx_ciu_wdogx_s cn52xx;
    1609. 

  1609. 	struct cvmx_ciu_wdogx_s cn52xxp1;
    1610. 

  1610. 	struct cvmx_ciu_wdogx_s cn56xx;
    1611. 

  1611. 	struct cvmx_ciu_wdogx_s cn56xxp1;
    1612. 

  1612. 	struct cvmx_ciu_wdogx_s cn58xx;
    1613. 

  1613. 	struct cvmx_ciu_wdogx_s cn58xxp1;
    1614. 

  1614. };
    1615. 

  1615. 

  1616. #endif
    1617.