/arch/mips/alchemy/devboards/pb1000/board_setup.c

https://bitbucket.org/cresqo/cm7-p500-kernel · C · 207 lines · 113 code · 36 blank · 58 comment · 4 complexity · 136e67800b05291817c3a01dbdbe1a54 MD5 · raw file

  1. /*
  2. * Copyright 2000, 2008 MontaVista Software Inc.
  3. * Author: MontaVista Software, Inc. <source@mvista.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the
  7. * Free Software Foundation; either version 2 of the License, or (at your
  8. * option) any later version.
  9. *
  10. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  11. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  12. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  13. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  14. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  15. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  16. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  17. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  18. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  19. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  20. *
  21. * You should have received a copy of the GNU General Public License along
  22. * with this program; if not, write to the Free Software Foundation, Inc.,
  23. * 675 Mass Ave, Cambridge, MA 02139, USA.
  24. */
  25. #include <linux/delay.h>
  26. #include <linux/gpio.h>
  27. #include <linux/init.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/pm.h>
  30. #include <asm/mach-au1x00/au1000.h>
  31. #include <asm/mach-pb1x00/pb1000.h>
  32. #include <asm/reboot.h>
  33. #include <prom.h>
  34. #include "../platform.h"
  35. const char *get_system_type(void)
  36. {
  37. return "Alchemy Pb1000";
  38. }
  39. static void board_reset(char *c)
  40. {
  41. asm volatile ("jr %0" : : "r" (0xbfc00000));
  42. }
  43. static void board_power_off(void)
  44. {
  45. printk(KERN_ALERT "It's now safe to remove power\n");
  46. while (1)
  47. asm volatile (".set mips3 ; wait ; .set mips1");
  48. }
  49. void __init board_setup(void)
  50. {
  51. u32 pin_func, static_cfg0;
  52. u32 sys_freqctrl, sys_clksrc;
  53. u32 prid = read_c0_prid();
  54. sys_freqctrl = 0;
  55. sys_clksrc = 0;
  56. /* Set AUX clock to 12 MHz * 8 = 96 MHz */
  57. au_writel(8, SYS_AUXPLL);
  58. au_writel(0, SYS_PINSTATERD);
  59. udelay(100);
  60. #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  61. /* Zero and disable FREQ2 */
  62. sys_freqctrl = au_readl(SYS_FREQCTRL0);
  63. sys_freqctrl &= ~0xFFF00000;
  64. au_writel(sys_freqctrl, SYS_FREQCTRL0);
  65. /* Zero and disable USBH/USBD clocks */
  66. sys_clksrc = au_readl(SYS_CLKSRC);
  67. sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
  68. SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
  69. au_writel(sys_clksrc, SYS_CLKSRC);
  70. sys_freqctrl = au_readl(SYS_FREQCTRL0);
  71. sys_freqctrl &= ~0xFFF00000;
  72. sys_clksrc = au_readl(SYS_CLKSRC);
  73. sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
  74. SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
  75. switch (prid & 0x000000FF) {
  76. case 0x00: /* DA */
  77. case 0x01: /* HA */
  78. case 0x02: /* HB */
  79. /* CPU core freq to 48 MHz to slow it way down... */
  80. au_writel(4, SYS_CPUPLL);
  81. /*
  82. * Setup 48 MHz FREQ2 from CPUPLL for USB Host
  83. * FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz
  84. */
  85. sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2;
  86. au_writel(sys_freqctrl, SYS_FREQCTRL0);
  87. /* CPU core freq to 384 MHz */
  88. au_writel(0x20, SYS_CPUPLL);
  89. printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n");
  90. break;
  91. default: /* HC and newer */
  92. /* FREQ2 = aux / 2 = 48 MHz */
  93. sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
  94. SYS_FC_FE2 | SYS_FC_FS2;
  95. au_writel(sys_freqctrl, SYS_FREQCTRL0);
  96. break;
  97. }
  98. /*
  99. * Route 48 MHz FREQ2 into USB Host and/or Device
  100. */
  101. sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
  102. au_writel(sys_clksrc, SYS_CLKSRC);
  103. /* Configure pins GPIO[14:9] as GPIO */
  104. pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB);
  105. /* 2nd USB port is USB host */
  106. pin_func |= SYS_PF_USB;
  107. au_writel(pin_func, SYS_PINFUNC);
  108. alchemy_gpio_direction_input(11);
  109. alchemy_gpio_direction_input(13);
  110. alchemy_gpio_direction_output(4, 0);
  111. alchemy_gpio_direction_output(5, 0);
  112. #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
  113. /* Make GPIO 15 an input (for interrupt line) */
  114. pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF;
  115. /* We don't need I2S, so make it available for GPIO[31:29] */
  116. pin_func |= SYS_PF_I2S;
  117. au_writel(pin_func, SYS_PINFUNC);
  118. alchemy_gpio_direction_input(15);
  119. static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
  120. au_writel(static_cfg0, MEM_STCFG0);
  121. /* configure RCE2* for LCD */
  122. au_writel(0x00000004, MEM_STCFG2);
  123. /* MEM_STTIME2 */
  124. au_writel(0x09000000, MEM_STTIME2);
  125. /* Set 32-bit base address decoding for RCE2* */
  126. au_writel(0x10003ff0, MEM_STADDR2);
  127. /*
  128. * PCI CPLD setup
  129. * Expand CE0 to cover PCI
  130. */
  131. au_writel(0x11803e40, MEM_STADDR1);
  132. /* Burst visibility on */
  133. au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
  134. au_writel(0x83, MEM_STCFG1); /* ewait enabled, flash timing */
  135. au_writel(0x33030a10, MEM_STTIME1); /* slower timing for FPGA */
  136. /* Setup the static bus controller */
  137. au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
  138. au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
  139. au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
  140. /*
  141. * Enable Au1000 BCLK switching - note: sed1356 must not use
  142. * its BCLK (Au1000 LCLK) for any timings
  143. */
  144. switch (prid & 0x000000FF) {
  145. case 0x00: /* DA */
  146. case 0x01: /* HA */
  147. case 0x02: /* HB */
  148. break;
  149. default: /* HC and newer */
  150. /*
  151. * Enable sys bus clock divider when IDLE state or no bus
  152. * activity.
  153. */
  154. au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
  155. break;
  156. }
  157. pm_power_off = board_power_off;
  158. _machine_halt = board_power_off;
  159. _machine_restart = board_reset;
  160. }
  161. static int __init pb1000_init_irq(void)
  162. {
  163. set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
  164. return 0;
  165. }
  166. arch_initcall(pb1000_init_irq);
  167. static int __init pb1000_device_init(void)
  168. {
  169. return db1x_register_norflash(8 * 1024 * 1024, 4, 0);
  170. }
  171. device_initcall(pb1000_device_init);