/arch/m32r/include/asm/cachectl.h

https://bitbucket.org/cresqo/cm7-p500-kernel · C Header · 26 lines · 8 code · 3 blank · 15 comment · 0 complexity · 94c668db9769058aaf4e0bf3d2ffbb1f MD5 · raw file 

    

  1. /*
    2. 

  2.  * cachectl.h -- defines for M32R cache control system calls
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2003 by Kazuhiro Inaoka
    5. 

  5.  */
    6. 

  6. #ifndef	__ASM_M32R_CACHECTL
    7. 

  7. #define	__ASM_M32R_CACHECTL
    8. 

  8. 

  9. /*
    10. 

  10.  * Options for cacheflush system call
    11. 

  11.  *
    12. 

  12.  * cacheflush() is currently fluch_cache_all().
    13. 

  13.  */
    14. 

  14. #define	ICACHE	(1<<0)		/* flush instruction cache        */
    15. 

  15. #define	DCACHE	(1<<1)		/* writeback and flush data cache */
    16. 

  16. #define	BCACHE	(ICACHE|DCACHE)	/* flush both caches              */
    17. 

  17. 

  18. /*
    19. 

  19.  * Caching modes for the cachectl(2) call
    20. 

  20.  *
    21. 

  21.  * cachectl(2) is currently not supported and returns ENOSYS.
    22. 

  22.  */
    23. 

  23. #define CACHEABLE	0	/* make pages cacheable */
    24. 

  24. #define UNCACHEABLE	1	/* make pages uncacheable */
    25. 

  25. 

  26. #endif	/* __ASM_M32R_CACHECTL */
    27.