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/arch/arm/mach-omap2/devices.c

https://bitbucket.org/sammyz/iscream_thunderc-2.6.35-rebase
C | 915 lines | 773 code | 101 blank | 41 comment | 91 complexity | c33bb628045f1419d8d4e55a6ba5e779 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * linux/arch/arm/mach-omap2/devices.c
  3. *
  4. * OMAP2 platform device setup/initialization
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/init.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/io.h>
  16. #include <linux/clk.h>
  17. #include <mach/hardware.h>
  18. #include <mach/irqs.h>
  19. #include <asm/mach-types.h>
  20. #include <asm/mach/map.h>
  21. #include <asm/pmu.h>
  22. #include <plat/control.h>
  23. #include <plat/tc.h>
  24. #include <plat/board.h>
  25. #include <plat/mux.h>
  26. #include <mach/gpio.h>
  27. #include <plat/mmc.h>
  28. #include <plat/dma.h>
  29. #include "mux.h"
  30. #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
  31. static struct resource cam_resources[] = {
  32. {
  33. .start = OMAP24XX_CAMERA_BASE,
  34. .end = OMAP24XX_CAMERA_BASE + 0xfff,
  35. .flags = IORESOURCE_MEM,
  36. },
  37. {
  38. .start = INT_24XX_CAM_IRQ,
  39. .flags = IORESOURCE_IRQ,
  40. }
  41. };
  42. static struct platform_device omap_cam_device = {
  43. .name = "omap24xxcam",
  44. .id = -1,
  45. .num_resources = ARRAY_SIZE(cam_resources),
  46. .resource = cam_resources,
  47. };
  48. static inline void omap_init_camera(void)
  49. {
  50. platform_device_register(&omap_cam_device);
  51. }
  52. #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
  53. static struct resource omap3isp_resources[] = {
  54. {
  55. .start = OMAP3430_ISP_BASE,
  56. .end = OMAP3430_ISP_END,
  57. .flags = IORESOURCE_MEM,
  58. },
  59. {
  60. .start = OMAP3430_ISP_CBUFF_BASE,
  61. .end = OMAP3430_ISP_CBUFF_END,
  62. .flags = IORESOURCE_MEM,
  63. },
  64. {
  65. .start = OMAP3430_ISP_CCP2_BASE,
  66. .end = OMAP3430_ISP_CCP2_END,
  67. .flags = IORESOURCE_MEM,
  68. },
  69. {
  70. .start = OMAP3430_ISP_CCDC_BASE,
  71. .end = OMAP3430_ISP_CCDC_END,
  72. .flags = IORESOURCE_MEM,
  73. },
  74. {
  75. .start = OMAP3430_ISP_HIST_BASE,
  76. .end = OMAP3430_ISP_HIST_END,
  77. .flags = IORESOURCE_MEM,
  78. },
  79. {
  80. .start = OMAP3430_ISP_H3A_BASE,
  81. .end = OMAP3430_ISP_H3A_END,
  82. .flags = IORESOURCE_MEM,
  83. },
  84. {
  85. .start = OMAP3430_ISP_PREV_BASE,
  86. .end = OMAP3430_ISP_PREV_END,
  87. .flags = IORESOURCE_MEM,
  88. },
  89. {
  90. .start = OMAP3430_ISP_RESZ_BASE,
  91. .end = OMAP3430_ISP_RESZ_END,
  92. .flags = IORESOURCE_MEM,
  93. },
  94. {
  95. .start = OMAP3430_ISP_SBL_BASE,
  96. .end = OMAP3430_ISP_SBL_END,
  97. .flags = IORESOURCE_MEM,
  98. },
  99. {
  100. .start = OMAP3430_ISP_CSI2A_BASE,
  101. .end = OMAP3430_ISP_CSI2A_END,
  102. .flags = IORESOURCE_MEM,
  103. },
  104. {
  105. .start = OMAP3430_ISP_CSI2PHY_BASE,
  106. .end = OMAP3430_ISP_CSI2PHY_END,
  107. .flags = IORESOURCE_MEM,
  108. },
  109. {
  110. .start = INT_34XX_CAM_IRQ,
  111. .flags = IORESOURCE_IRQ,
  112. }
  113. };
  114. static struct platform_device omap3isp_device = {
  115. .name = "omap3isp",
  116. .id = -1,
  117. .num_resources = ARRAY_SIZE(omap3isp_resources),
  118. .resource = omap3isp_resources,
  119. };
  120. static inline void omap_init_camera(void)
  121. {
  122. platform_device_register(&omap3isp_device);
  123. }
  124. #else
  125. static inline void omap_init_camera(void)
  126. {
  127. }
  128. #endif
  129. #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
  130. #define MBOX_REG_SIZE 0x120
  131. #ifdef CONFIG_ARCH_OMAP2
  132. static struct resource omap2_mbox_resources[] = {
  133. {
  134. .start = OMAP24XX_MAILBOX_BASE,
  135. .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
  136. .flags = IORESOURCE_MEM,
  137. },
  138. {
  139. .start = INT_24XX_MAIL_U0_MPU,
  140. .flags = IORESOURCE_IRQ,
  141. },
  142. {
  143. .start = INT_24XX_MAIL_U3_MPU,
  144. .flags = IORESOURCE_IRQ,
  145. },
  146. };
  147. static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
  148. #else
  149. #define omap2_mbox_resources NULL
  150. #define omap2_mbox_resources_sz 0
  151. #endif
  152. #ifdef CONFIG_ARCH_OMAP3
  153. static struct resource omap3_mbox_resources[] = {
  154. {
  155. .start = OMAP34XX_MAILBOX_BASE,
  156. .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
  157. .flags = IORESOURCE_MEM,
  158. },
  159. {
  160. .start = INT_24XX_MAIL_U0_MPU,
  161. .flags = IORESOURCE_IRQ,
  162. },
  163. };
  164. static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
  165. #else
  166. #define omap3_mbox_resources NULL
  167. #define omap3_mbox_resources_sz 0
  168. #endif
  169. #ifdef CONFIG_ARCH_OMAP4
  170. #define OMAP4_MBOX_REG_SIZE 0x130
  171. static struct resource omap4_mbox_resources[] = {
  172. {
  173. .start = OMAP44XX_MAILBOX_BASE,
  174. .end = OMAP44XX_MAILBOX_BASE +
  175. OMAP4_MBOX_REG_SIZE - 1,
  176. .flags = IORESOURCE_MEM,
  177. },
  178. {
  179. .start = OMAP44XX_IRQ_MAIL_U0,
  180. .flags = IORESOURCE_IRQ,
  181. },
  182. };
  183. static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
  184. #else
  185. #define omap4_mbox_resources NULL
  186. #define omap4_mbox_resources_sz 0
  187. #endif
  188. static struct platform_device mbox_device = {
  189. .name = "omap2-mailbox",
  190. .id = -1,
  191. };
  192. static inline void omap_init_mbox(void)
  193. {
  194. if (cpu_is_omap24xx()) {
  195. mbox_device.resource = omap2_mbox_resources;
  196. mbox_device.num_resources = omap2_mbox_resources_sz;
  197. } else if (cpu_is_omap34xx()) {
  198. mbox_device.resource = omap3_mbox_resources;
  199. mbox_device.num_resources = omap3_mbox_resources_sz;
  200. } else if (cpu_is_omap44xx()) {
  201. mbox_device.resource = omap4_mbox_resources;
  202. mbox_device.num_resources = omap4_mbox_resources_sz;
  203. } else {
  204. pr_err("%s: platform not supported\n", __func__);
  205. return;
  206. }
  207. platform_device_register(&mbox_device);
  208. }
  209. #else
  210. static inline void omap_init_mbox(void) { }
  211. #endif /* CONFIG_OMAP_MBOX_FWK */
  212. #if defined(CONFIG_OMAP_STI)
  213. #if defined(CONFIG_ARCH_OMAP2)
  214. #define OMAP2_STI_BASE 0x48068000
  215. #define OMAP2_STI_CHANNEL_BASE 0x54000000
  216. #define OMAP2_STI_IRQ 4
  217. static struct resource sti_resources[] = {
  218. {
  219. .start = OMAP2_STI_BASE,
  220. .end = OMAP2_STI_BASE + 0x7ff,
  221. .flags = IORESOURCE_MEM,
  222. },
  223. {
  224. .start = OMAP2_STI_CHANNEL_BASE,
  225. .end = OMAP2_STI_CHANNEL_BASE + SZ_64K - 1,
  226. .flags = IORESOURCE_MEM,
  227. },
  228. {
  229. .start = OMAP2_STI_IRQ,
  230. .flags = IORESOURCE_IRQ,
  231. }
  232. };
  233. #elif defined(CONFIG_ARCH_OMAP3)
  234. #define OMAP3_SDTI_BASE 0x54500000
  235. #define OMAP3_SDTI_CHANNEL_BASE 0x54600000
  236. static struct resource sti_resources[] = {
  237. {
  238. .start = OMAP3_SDTI_BASE,
  239. .end = OMAP3_SDTI_BASE + 0xFFF,
  240. .flags = IORESOURCE_MEM,
  241. },
  242. {
  243. .start = OMAP3_SDTI_CHANNEL_BASE,
  244. .end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
  245. .flags = IORESOURCE_MEM,
  246. }
  247. };
  248. #endif
  249. static struct platform_device sti_device = {
  250. .name = "sti",
  251. .id = -1,
  252. .num_resources = ARRAY_SIZE(sti_resources),
  253. .resource = sti_resources,
  254. };
  255. static inline void omap_init_sti(void)
  256. {
  257. platform_device_register(&sti_device);
  258. }
  259. #else
  260. static inline void omap_init_sti(void) {}
  261. #endif
  262. #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
  263. #include <plat/mcspi.h>
  264. #define OMAP2_MCSPI1_BASE 0x48098000
  265. #define OMAP2_MCSPI2_BASE 0x4809a000
  266. #define OMAP2_MCSPI3_BASE 0x480b8000
  267. #define OMAP2_MCSPI4_BASE 0x480ba000
  268. #define OMAP4_MCSPI1_BASE 0x48098100
  269. #define OMAP4_MCSPI2_BASE 0x4809a100
  270. #define OMAP4_MCSPI3_BASE 0x480b8100
  271. #define OMAP4_MCSPI4_BASE 0x480ba100
  272. static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
  273. .num_cs = 4,
  274. };
  275. static struct resource omap2_mcspi1_resources[] = {
  276. {
  277. .start = OMAP2_MCSPI1_BASE,
  278. .end = OMAP2_MCSPI1_BASE + 0xff,
  279. .flags = IORESOURCE_MEM,
  280. },
  281. };
  282. static struct platform_device omap2_mcspi1 = {
  283. .name = "omap2_mcspi",
  284. .id = 1,
  285. .num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
  286. .resource = omap2_mcspi1_resources,
  287. .dev = {
  288. .platform_data = &omap2_mcspi1_config,
  289. },
  290. };
  291. static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
  292. .num_cs = 2,
  293. };
  294. static struct resource omap2_mcspi2_resources[] = {
  295. {
  296. .start = OMAP2_MCSPI2_BASE,
  297. .end = OMAP2_MCSPI2_BASE + 0xff,
  298. .flags = IORESOURCE_MEM,
  299. },
  300. };
  301. static struct platform_device omap2_mcspi2 = {
  302. .name = "omap2_mcspi",
  303. .id = 2,
  304. .num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
  305. .resource = omap2_mcspi2_resources,
  306. .dev = {
  307. .platform_data = &omap2_mcspi2_config,
  308. },
  309. };
  310. #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
  311. defined(CONFIG_ARCH_OMAP4)
  312. static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
  313. .num_cs = 2,
  314. };
  315. static struct resource omap2_mcspi3_resources[] = {
  316. {
  317. .start = OMAP2_MCSPI3_BASE,
  318. .end = OMAP2_MCSPI3_BASE + 0xff,
  319. .flags = IORESOURCE_MEM,
  320. },
  321. };
  322. static struct platform_device omap2_mcspi3 = {
  323. .name = "omap2_mcspi",
  324. .id = 3,
  325. .num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
  326. .resource = omap2_mcspi3_resources,
  327. .dev = {
  328. .platform_data = &omap2_mcspi3_config,
  329. },
  330. };
  331. #endif
  332. #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
  333. static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
  334. .num_cs = 1,
  335. };
  336. static struct resource omap2_mcspi4_resources[] = {
  337. {
  338. .start = OMAP2_MCSPI4_BASE,
  339. .end = OMAP2_MCSPI4_BASE + 0xff,
  340. .flags = IORESOURCE_MEM,
  341. },
  342. };
  343. static struct platform_device omap2_mcspi4 = {
  344. .name = "omap2_mcspi",
  345. .id = 4,
  346. .num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
  347. .resource = omap2_mcspi4_resources,
  348. .dev = {
  349. .platform_data = &omap2_mcspi4_config,
  350. },
  351. };
  352. #endif
  353. #ifdef CONFIG_ARCH_OMAP4
  354. static inline void omap4_mcspi_fixup(void)
  355. {
  356. omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
  357. omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff;
  358. omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
  359. omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff;
  360. omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
  361. omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff;
  362. omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
  363. omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff;
  364. }
  365. #else
  366. static inline void omap4_mcspi_fixup(void)
  367. {
  368. }
  369. #endif
  370. #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
  371. defined(CONFIG_ARCH_OMAP4)
  372. static inline void omap2_mcspi3_init(void)
  373. {
  374. platform_device_register(&omap2_mcspi3);
  375. }
  376. #else
  377. static inline void omap2_mcspi3_init(void)
  378. {
  379. }
  380. #endif
  381. #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
  382. static inline void omap2_mcspi4_init(void)
  383. {
  384. platform_device_register(&omap2_mcspi4);
  385. }
  386. #else
  387. static inline void omap2_mcspi4_init(void)
  388. {
  389. }
  390. #endif
  391. static void omap_init_mcspi(void)
  392. {
  393. if (cpu_is_omap44xx())
  394. omap4_mcspi_fixup();
  395. platform_device_register(&omap2_mcspi1);
  396. platform_device_register(&omap2_mcspi2);
  397. if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
  398. omap2_mcspi3_init();
  399. if (cpu_is_omap343x() || cpu_is_omap44xx())
  400. omap2_mcspi4_init();
  401. }
  402. #else
  403. static inline void omap_init_mcspi(void) {}
  404. #endif
  405. static struct resource omap2_pmu_resource = {
  406. .start = 3,
  407. .end = 3,
  408. .flags = IORESOURCE_IRQ,
  409. };
  410. static struct resource omap3_pmu_resource = {
  411. .start = INT_34XX_BENCH_MPU_EMUL,
  412. .end = INT_34XX_BENCH_MPU_EMUL,
  413. .flags = IORESOURCE_IRQ,
  414. };
  415. static struct platform_device omap_pmu_device = {
  416. .name = "arm-pmu",
  417. .id = ARM_PMU_DEVICE_CPU,
  418. .num_resources = 1,
  419. };
  420. static void omap_init_pmu(void)
  421. {
  422. if (cpu_is_omap24xx())
  423. omap_pmu_device.resource = &omap2_pmu_resource;
  424. else if (cpu_is_omap34xx())
  425. omap_pmu_device.resource = &omap3_pmu_resource;
  426. else
  427. return;
  428. platform_device_register(&omap_pmu_device);
  429. }
  430. #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
  431. #ifdef CONFIG_ARCH_OMAP2
  432. static struct resource omap2_sham_resources[] = {
  433. {
  434. .start = OMAP24XX_SEC_SHA1MD5_BASE,
  435. .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
  436. .flags = IORESOURCE_MEM,
  437. },
  438. {
  439. .start = INT_24XX_SHA1MD5,
  440. .flags = IORESOURCE_IRQ,
  441. }
  442. };
  443. static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
  444. #else
  445. #define omap2_sham_resources NULL
  446. #define omap2_sham_resources_sz 0
  447. #endif
  448. #ifdef CONFIG_ARCH_OMAP3
  449. static struct resource omap3_sham_resources[] = {
  450. {
  451. .start = OMAP34XX_SEC_SHA1MD5_BASE,
  452. .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
  453. .flags = IORESOURCE_MEM,
  454. },
  455. {
  456. .start = INT_34XX_SHA1MD52_IRQ,
  457. .flags = IORESOURCE_IRQ,
  458. },
  459. {
  460. .start = OMAP34XX_DMA_SHA1MD5_RX,
  461. .flags = IORESOURCE_DMA,
  462. }
  463. };
  464. static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
  465. #else
  466. #define omap3_sham_resources NULL
  467. #define omap3_sham_resources_sz 0
  468. #endif
  469. static struct platform_device sham_device = {
  470. .name = "omap-sham",
  471. .id = -1,
  472. };
  473. static void omap_init_sham(void)
  474. {
  475. if (cpu_is_omap24xx()) {
  476. sham_device.resource = omap2_sham_resources;
  477. sham_device.num_resources = omap2_sham_resources_sz;
  478. } else if (cpu_is_omap34xx()) {
  479. sham_device.resource = omap3_sham_resources;
  480. sham_device.num_resources = omap3_sham_resources_sz;
  481. } else {
  482. pr_err("%s: platform not supported\n", __func__);
  483. return;
  484. }
  485. platform_device_register(&sham_device);
  486. }
  487. #else
  488. static inline void omap_init_sham(void) { }
  489. #endif
  490. /*-------------------------------------------------------------------------*/
  491. #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
  492. #define MMCHS_SYSCONFIG 0x0010
  493. #define MMCHS_SYSCONFIG_SWRESET (1 << 1)
  494. #define MMCHS_SYSSTATUS 0x0014
  495. #define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
  496. static struct platform_device dummy_pdev = {
  497. .dev = {
  498. .bus = &platform_bus_type,
  499. },
  500. };
  501. /**
  502. * omap_hsmmc_reset() - Full reset of each HS-MMC controller
  503. *
  504. * Ensure that each MMC controller is fully reset. Controllers
  505. * left in an unknown state (by bootloader) may prevent retention
  506. * or OFF-mode. This is especially important in cases where the
  507. * MMC driver is not enabled, _or_ built as a module.
  508. *
  509. * In order for reset to work, interface, functional and debounce
  510. * clocks must be enabled. The debounce clock comes from func_32k_clk
  511. * and is not under SW control, so we only enable i- and f-clocks.
  512. **/
  513. static void __init omap_hsmmc_reset(void)
  514. {
  515. u32 i, nr_controllers;
  516. if (cpu_is_omap242x())
  517. return;
  518. nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
  519. (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
  520. for (i = 0; i < nr_controllers; i++) {
  521. u32 v, base = 0;
  522. struct clk *iclk, *fclk;
  523. struct device *dev = &dummy_pdev.dev;
  524. switch (i) {
  525. case 0:
  526. base = OMAP2_MMC1_BASE;
  527. break;
  528. case 1:
  529. base = OMAP2_MMC2_BASE;
  530. break;
  531. case 2:
  532. base = OMAP3_MMC3_BASE;
  533. break;
  534. case 3:
  535. if (!cpu_is_omap44xx())
  536. return;
  537. base = OMAP4_MMC4_BASE;
  538. break;
  539. case 4:
  540. if (!cpu_is_omap44xx())
  541. return;
  542. base = OMAP4_MMC5_BASE;
  543. break;
  544. }
  545. if (cpu_is_omap44xx())
  546. base += OMAP4_MMC_REG_OFFSET;
  547. dummy_pdev.id = i;
  548. dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
  549. iclk = clk_get(dev, "ick");
  550. if (iclk && clk_enable(iclk))
  551. iclk = NULL;
  552. fclk = clk_get(dev, "fck");
  553. if (fclk && clk_enable(fclk))
  554. fclk = NULL;
  555. if (!iclk || !fclk) {
  556. printk(KERN_WARNING
  557. "%s: Unable to enable clocks for MMC%d, "
  558. "cannot reset.\n", __func__, i);
  559. break;
  560. }
  561. omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
  562. v = omap_readl(base + MMCHS_SYSSTATUS);
  563. while (!(omap_readl(base + MMCHS_SYSSTATUS) &
  564. MMCHS_SYSSTATUS_RESETDONE))
  565. cpu_relax();
  566. if (fclk) {
  567. clk_disable(fclk);
  568. clk_put(fclk);
  569. }
  570. if (iclk) {
  571. clk_disable(iclk);
  572. clk_put(iclk);
  573. }
  574. }
  575. }
  576. #else
  577. static inline void omap_hsmmc_reset(void) {}
  578. #endif
  579. #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
  580. defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  581. static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
  582. int controller_nr)
  583. {
  584. if ((mmc_controller->slots[0].switch_pin > 0) && \
  585. (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
  586. omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
  587. OMAP_PIN_INPUT_PULLUP);
  588. if ((mmc_controller->slots[0].gpio_wp > 0) && \
  589. (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
  590. omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
  591. OMAP_PIN_INPUT_PULLUP);
  592. if (cpu_is_omap2420() && controller_nr == 0) {
  593. omap_cfg_reg(H18_24XX_MMC_CMD);
  594. omap_cfg_reg(H15_24XX_MMC_CLKI);
  595. omap_cfg_reg(G19_24XX_MMC_CLKO);
  596. omap_cfg_reg(F20_24XX_MMC_DAT0);
  597. omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
  598. omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
  599. if (mmc_controller->slots[0].wires == 4) {
  600. omap_cfg_reg(H14_24XX_MMC_DAT1);
  601. omap_cfg_reg(E19_24XX_MMC_DAT2);
  602. omap_cfg_reg(D19_24XX_MMC_DAT3);
  603. omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
  604. omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
  605. omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
  606. }
  607. /*
  608. * Use internal loop-back in MMC/SDIO Module Input Clock
  609. * selection
  610. */
  611. if (mmc_controller->slots[0].internal_clock) {
  612. u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
  613. v |= (1 << 24);
  614. omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
  615. }
  616. }
  617. if (cpu_is_omap34xx()) {
  618. if (controller_nr == 0) {
  619. omap_mux_init_signal("sdmmc1_clk",
  620. OMAP_PIN_INPUT_PULLUP);
  621. omap_mux_init_signal("sdmmc1_cmd",
  622. OMAP_PIN_INPUT_PULLUP);
  623. omap_mux_init_signal("sdmmc1_dat0",
  624. OMAP_PIN_INPUT_PULLUP);
  625. if (mmc_controller->slots[0].wires == 4 ||
  626. mmc_controller->slots[0].wires == 8) {
  627. omap_mux_init_signal("sdmmc1_dat1",
  628. OMAP_PIN_INPUT_PULLUP);
  629. omap_mux_init_signal("sdmmc1_dat2",
  630. OMAP_PIN_INPUT_PULLUP);
  631. omap_mux_init_signal("sdmmc1_dat3",
  632. OMAP_PIN_INPUT_PULLUP);
  633. }
  634. if (mmc_controller->slots[0].wires == 8) {
  635. omap_mux_init_signal("sdmmc1_dat4",
  636. OMAP_PIN_INPUT_PULLUP);
  637. omap_mux_init_signal("sdmmc1_dat5",
  638. OMAP_PIN_INPUT_PULLUP);
  639. omap_mux_init_signal("sdmmc1_dat6",
  640. OMAP_PIN_INPUT_PULLUP);
  641. omap_mux_init_signal("sdmmc1_dat7",
  642. OMAP_PIN_INPUT_PULLUP);
  643. }
  644. }
  645. if (controller_nr == 1) {
  646. /* MMC2 */
  647. omap_mux_init_signal("sdmmc2_clk",
  648. OMAP_PIN_INPUT_PULLUP);
  649. omap_mux_init_signal("sdmmc2_cmd",
  650. OMAP_PIN_INPUT_PULLUP);
  651. omap_mux_init_signal("sdmmc2_dat0",
  652. OMAP_PIN_INPUT_PULLUP);
  653. /*
  654. * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
  655. * in the board-*.c files
  656. */
  657. if (mmc_controller->slots[0].wires == 4 ||
  658. mmc_controller->slots[0].wires == 8) {
  659. omap_mux_init_signal("sdmmc2_dat1",
  660. OMAP_PIN_INPUT_PULLUP);
  661. omap_mux_init_signal("sdmmc2_dat2",
  662. OMAP_PIN_INPUT_PULLUP);
  663. omap_mux_init_signal("sdmmc2_dat3",
  664. OMAP_PIN_INPUT_PULLUP);
  665. }
  666. if (mmc_controller->slots[0].wires == 8) {
  667. omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
  668. OMAP_PIN_INPUT_PULLUP);
  669. omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
  670. OMAP_PIN_INPUT_PULLUP);
  671. omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
  672. OMAP_PIN_INPUT_PULLUP);
  673. omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
  674. OMAP_PIN_INPUT_PULLUP);
  675. }
  676. }
  677. /*
  678. * For MMC3 the pins need to be muxed in the board-*.c files
  679. */
  680. }
  681. }
  682. void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
  683. int nr_controllers)
  684. {
  685. int i;
  686. char *name;
  687. for (i = 0; i < nr_controllers; i++) {
  688. unsigned long base, size;
  689. unsigned int irq = 0;
  690. if (!mmc_data[i])
  691. continue;
  692. omap2_mmc_mux(mmc_data[i], i);
  693. switch (i) {
  694. case 0:
  695. base = OMAP2_MMC1_BASE;
  696. irq = INT_24XX_MMC_IRQ;
  697. break;
  698. case 1:
  699. base = OMAP2_MMC2_BASE;
  700. irq = INT_24XX_MMC2_IRQ;
  701. break;
  702. case 2:
  703. if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
  704. return;
  705. base = OMAP3_MMC3_BASE;
  706. irq = INT_34XX_MMC3_IRQ;
  707. break;
  708. case 3:
  709. if (!cpu_is_omap44xx())
  710. return;
  711. base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET;
  712. irq = OMAP44XX_IRQ_MMC4;
  713. break;
  714. case 4:
  715. if (!cpu_is_omap44xx())
  716. return;
  717. base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
  718. irq = OMAP44XX_IRQ_MMC5;
  719. break;
  720. default:
  721. continue;
  722. }
  723. if (cpu_is_omap2420()) {
  724. size = OMAP2420_MMC_SIZE;
  725. name = "mmci-omap";
  726. } else if (cpu_is_omap44xx()) {
  727. if (i < 3) {
  728. base += OMAP4_MMC_REG_OFFSET;
  729. irq += OMAP44XX_IRQ_GIC_START;
  730. }
  731. size = OMAP4_HSMMC_SIZE;
  732. name = "mmci-omap-hs";
  733. } else {
  734. size = OMAP3_HSMMC_SIZE;
  735. name = "mmci-omap-hs";
  736. }
  737. omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
  738. };
  739. }
  740. #endif
  741. /*-------------------------------------------------------------------------*/
  742. #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
  743. #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
  744. #define OMAP_HDQ_BASE 0x480B2000
  745. #endif
  746. static struct resource omap_hdq_resources[] = {
  747. {
  748. .start = OMAP_HDQ_BASE,
  749. .end = OMAP_HDQ_BASE + 0x1C,
  750. .flags = IORESOURCE_MEM,
  751. },
  752. {
  753. .start = INT_24XX_HDQ_IRQ,
  754. .flags = IORESOURCE_IRQ,
  755. },
  756. };
  757. static struct platform_device omap_hdq_dev = {
  758. .name = "omap_hdq",
  759. .id = 0,
  760. .dev = {
  761. .platform_data = NULL,
  762. },
  763. .num_resources = ARRAY_SIZE(omap_hdq_resources),
  764. .resource = omap_hdq_resources,
  765. };
  766. static inline void omap_hdq_init(void)
  767. {
  768. (void) platform_device_register(&omap_hdq_dev);
  769. }
  770. #else
  771. static inline void omap_hdq_init(void) {}
  772. #endif
  773. /*---------------------------------------------------------------------------*/
  774. #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
  775. defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
  776. #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
  777. static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
  778. };
  779. #else
  780. static struct resource omap_vout_resource[2] = {
  781. };
  782. #endif
  783. static struct platform_device omap_vout_device = {
  784. .name = "omap_vout",
  785. .num_resources = ARRAY_SIZE(omap_vout_resource),
  786. .resource = &omap_vout_resource[0],
  787. .id = -1,
  788. };
  789. static void omap_init_vout(void)
  790. {
  791. if (platform_device_register(&omap_vout_device) < 0)
  792. printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
  793. }
  794. #else
  795. static inline void omap_init_vout(void) {}
  796. #endif
  797. /*-------------------------------------------------------------------------*/
  798. static int __init omap2_init_devices(void)
  799. {
  800. /* please keep these calls, and their implementations above,
  801. * in alphabetical order so they're easier to sort through.
  802. */
  803. omap_hsmmc_reset();
  804. omap_init_camera();
  805. omap_init_mbox();
  806. omap_init_mcspi();
  807. omap_init_pmu();
  808. omap_hdq_init();
  809. omap_init_sti();
  810. omap_init_sham();
  811. omap_init_vout();
  812. return 0;
  813. }
  814. arch_initcall(omap2_init_devices);