/arch/arm/mach-omap2/clockdomains.h
C++ Header | 937 lines | 702 code | 100 blank | 135 comment | 2 complexity | 4202cdf15f1637f4fe529251871f8244 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/*
2 * OMAP2/3 clockdomains
3 *
4 * Copyright (C) 2008-2009 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 *
7 * Written by Paul Walmsley and Jouni Hรถgander
8 *
9 * This file contains clockdomains and clockdomain wakeup/sleep
10 * dependencies for the OMAP2/3 chips. Some notes:
11 *
12 * A useful validation rule for struct clockdomain: Any clockdomain
13 * referenced by a wkdep_srcs or sleepdep_srcs array must have a
14 * dep_bit assigned. So wkdep_srcs/sleepdep_srcs are really just
15 * software-controllable dependencies. Non-software-controllable
16 * dependencies do exist, but they are not encoded below (yet).
17 *
18 * 24xx does not support programmable sleep dependencies (SLEEPDEP)
19 *
20 * The overly-specific dep_bit names are due to a bit name collision
21 * with CM_FCLKEN_{DSP,IVA2}. The DSP/IVA2 PM_WKDEP and CM_SLEEPDEP shift
22 * value are the same for all powerdomains: 2
23 *
24 * XXX should dep_bit be a mask, so we can test to see if it is 0 as a
25 * sanity check?
26 * XXX encode hardware fixed wakeup dependencies -- esp. for 3430 CORE
27 */
28
29/*
30 * To-Do List
31 * -> Port the Sleep/Wakeup dependencies for the domains
32 * from the Power domain framework
33 */
34
35#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
36#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
37
38#include <plat/clockdomain.h>
39#include "cm.h"
40#include "prm.h"
41
42/*
43 * Clockdomain dependencies for wkdeps/sleepdeps
44 *
45 * XXX Hardware dependencies (e.g., dependencies that cannot be
46 * changed in software) are not included here yet, but should be.
47 */
48
49/* OMAP2/3-common wakeup dependencies */
50
51/*
52 * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
53 * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
54 * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
55 * These can share data since they will never be present simultaneously
56 * on the same device.
57 */
58static struct clkdm_dep gfx_sgx_wkdeps[] = {
59 {
60 .clkdm_name = "core_l3_clkdm",
61 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
62 },
63 {
64 .clkdm_name = "core_l4_clkdm",
65 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
66 },
67 {
68 .clkdm_name = "iva2_clkdm",
69 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
70 },
71 {
72 .clkdm_name = "mpu_clkdm",
73 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
74 CHIP_IS_OMAP3430)
75 },
76 {
77 .clkdm_name = "wkup_clkdm",
78 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
79 CHIP_IS_OMAP3430)
80 },
81 { NULL },
82};
83
84
85/* 24XX-specific possible dependencies */
86
87#ifdef CONFIG_ARCH_OMAP2
88
89/* Wakeup dependency source arrays */
90
91/* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */
92static struct clkdm_dep dsp_24xx_wkdeps[] = {
93 {
94 .clkdm_name = "core_l3_clkdm",
95 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
96 },
97 {
98 .clkdm_name = "core_l4_clkdm",
99 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
100 },
101 {
102 .clkdm_name = "mpu_clkdm",
103 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
104 },
105 {
106 .clkdm_name = "wkup_clkdm",
107 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
108 },
109 { NULL },
110};
111
112/*
113 * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
114 * 2430 adds MDM
115 */
116static struct clkdm_dep mpu_24xx_wkdeps[] = {
117 {
118 .clkdm_name = "core_l3_clkdm",
119 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
120 },
121 {
122 .clkdm_name = "core_l4_clkdm",
123 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
124 },
125 {
126 .clkdm_name = "dsp_clkdm",
127 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
128 },
129 {
130 .clkdm_name = "wkup_clkdm",
131 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
132 },
133 {
134 .clkdm_name = "mdm_clkdm",
135 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
136 },
137 { NULL },
138};
139
140/*
141 * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
142 * 2430 adds MDM
143 */
144static struct clkdm_dep core_24xx_wkdeps[] = {
145 {
146 .clkdm_name = "dsp_clkdm",
147 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
148 },
149 {
150 .clkdm_name = "gfx_clkdm",
151 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
152 },
153 {
154 .clkdm_name = "mpu_clkdm",
155 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
156 },
157 {
158 .clkdm_name = "wkup_clkdm",
159 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
160 },
161 {
162 .clkdm_name = "mdm_clkdm",
163 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
164 },
165 { NULL },
166};
167
168#endif
169
170
171/* 2430-specific possible wakeup dependencies */
172
173#ifdef CONFIG_ARCH_OMAP2430
174
175/* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
176static struct clkdm_dep mdm_2430_wkdeps[] = {
177 {
178 .clkdm_name = "core_l3_clkdm",
179 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
180 },
181 {
182 .clkdm_name = "core_l4_clkdm",
183 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
184 },
185 {
186 .clkdm_name = "mpu_clkdm",
187 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
188 },
189 {
190 .clkdm_name = "wkup_clkdm",
191 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
192 },
193 { NULL },
194};
195
196#endif /* CONFIG_ARCH_OMAP2430 */
197
198
199/* OMAP3-specific possible dependencies */
200
201#ifdef CONFIG_ARCH_OMAP3
202
203/* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
204static struct clkdm_dep per_wkdeps[] = {
205 {
206 .clkdm_name = "core_l3_clkdm",
207 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
208 },
209 {
210 .clkdm_name = "core_l4_clkdm",
211 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
212 },
213 {
214 .clkdm_name = "iva2_clkdm",
215 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
216 },
217 {
218 .clkdm_name = "mpu_clkdm",
219 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
220 },
221 {
222 .clkdm_name = "wkup_clkdm",
223 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
224 },
225 { NULL },
226};
227
228/* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
229static struct clkdm_dep usbhost_wkdeps[] = {
230 {
231 .clkdm_name = "core_l3_clkdm",
232 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
233 },
234 {
235 .clkdm_name = "core_l4_clkdm",
236 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
237 },
238 {
239 .clkdm_name = "iva2_clkdm",
240 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
241 },
242 {
243 .clkdm_name = "mpu_clkdm",
244 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
245 },
246 {
247 .clkdm_name = "wkup_clkdm",
248 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
249 },
250 { NULL },
251};
252
253/* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
254static struct clkdm_dep mpu_3xxx_wkdeps[] = {
255 {
256 .clkdm_name = "core_l3_clkdm",
257 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
258 },
259 {
260 .clkdm_name = "core_l4_clkdm",
261 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
262 },
263 {
264 .clkdm_name = "iva2_clkdm",
265 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
266 },
267 {
268 .clkdm_name = "dss_clkdm",
269 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
270 },
271 {
272 .clkdm_name = "per_clkdm",
273 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
274 },
275 { NULL },
276};
277
278/* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
279static struct clkdm_dep iva2_wkdeps[] = {
280 {
281 .clkdm_name = "core_l3_clkdm",
282 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
283 },
284 {
285 .clkdm_name = "core_l4_clkdm",
286 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
287 },
288 {
289 .clkdm_name = "mpu_clkdm",
290 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
291 },
292 {
293 .clkdm_name = "wkup_clkdm",
294 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
295 },
296 {
297 .clkdm_name = "dss_clkdm",
298 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
299 },
300 {
301 .clkdm_name = "per_clkdm",
302 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
303 },
304 { NULL },
305};
306
307
308/* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
309static struct clkdm_dep cam_wkdeps[] = {
310 {
311 .clkdm_name = "iva2_clkdm",
312 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
313 },
314 {
315 .clkdm_name = "mpu_clkdm",
316 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
317 },
318 {
319 .clkdm_name = "wkup_clkdm",
320 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
321 },
322 { NULL },
323};
324
325/* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
326static struct clkdm_dep dss_wkdeps[] = {
327 {
328 .clkdm_name = "iva2_clkdm",
329 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
330 },
331 {
332 .clkdm_name = "mpu_clkdm",
333 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
334 },
335 {
336 .clkdm_name = "wkup_clkdm",
337 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
338 },
339 { NULL },
340};
341
342/* 3430: PM_WKDEP_NEON: MPU */
343static struct clkdm_dep neon_wkdeps[] = {
344 {
345 .clkdm_name = "mpu_clkdm",
346 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
347 },
348 { NULL },
349};
350
351
352/* Sleep dependency source arrays for OMAP3-specific clkdms */
353
354/* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
355static struct clkdm_dep dss_sleepdeps[] = {
356 {
357 .clkdm_name = "mpu_clkdm",
358 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
359 },
360 {
361 .clkdm_name = "iva2_clkdm",
362 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
363 },
364 { NULL },
365};
366
367/* 3430: CM_SLEEPDEP_PER: MPU, IVA */
368static struct clkdm_dep per_sleepdeps[] = {
369 {
370 .clkdm_name = "mpu_clkdm",
371 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
372 },
373 {
374 .clkdm_name = "iva2_clkdm",
375 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
376 },
377 { NULL },
378};
379
380/* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
381static struct clkdm_dep usbhost_sleepdeps[] = {
382 {
383 .clkdm_name = "mpu_clkdm",
384 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
385 },
386 {
387 .clkdm_name = "iva2_clkdm",
388 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
389 },
390 { NULL },
391};
392
393/* 3430: CM_SLEEPDEP_CAM: MPU */
394static struct clkdm_dep cam_sleepdeps[] = {
395 {
396 .clkdm_name = "mpu_clkdm",
397 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
398 },
399 { NULL },
400};
401
402/*
403 * 3430ES1: CM_SLEEPDEP_GFX: MPU
404 * 3430ES2: CM_SLEEPDEP_SGX: MPU
405 * These can share data since they will never be present simultaneously
406 * on the same device.
407 */
408static struct clkdm_dep gfx_sgx_sleepdeps[] = {
409 {
410 .clkdm_name = "mpu_clkdm",
411 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
412 },
413 { NULL },
414};
415
416#endif /* CONFIG_ARCH_OMAP3 */
417
418
419/*
420 * OMAP2/3-common clockdomains
421 *
422 * Even though the 2420 has a single PRCM module from the
423 * interconnect's perspective, internally it does appear to have
424 * separate PRM and CM clockdomains. The usual test case is
425 * sys_clkout/sys_clkout2.
426 */
427
428#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
429
430/* This is an implicit clockdomain - it is never defined as such in TRM */
431static struct clockdomain wkup_clkdm = {
432 .name = "wkup_clkdm",
433 .pwrdm = { .name = "wkup_pwrdm" },
434 .dep_bit = OMAP_EN_WKUP_SHIFT,
435 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
436};
437
438static struct clockdomain prm_clkdm = {
439 .name = "prm_clkdm",
440 .pwrdm = { .name = "wkup_pwrdm" },
441 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
442};
443
444static struct clockdomain cm_clkdm = {
445 .name = "cm_clkdm",
446 .pwrdm = { .name = "core_pwrdm" },
447 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
448};
449
450#endif
451
452/*
453 * 2420-only clockdomains
454 */
455
456#if defined(CONFIG_ARCH_OMAP2420)
457
458static struct clockdomain mpu_2420_clkdm = {
459 .name = "mpu_clkdm",
460 .pwrdm = { .name = "mpu_pwrdm" },
461 .flags = CLKDM_CAN_HWSUP,
462 .clkstctrl_reg = OMAP2420_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
463 .wkdep_srcs = mpu_24xx_wkdeps,
464 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
465 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
466};
467
468static struct clockdomain iva1_2420_clkdm = {
469 .name = "iva1_clkdm",
470 .pwrdm = { .name = "dsp_pwrdm" },
471 .flags = CLKDM_CAN_HWSUP_SWSUP,
472 .clkstctrl_reg = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
473 OMAP2_CM_CLKSTCTRL),
474 .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
475 .wkdep_srcs = dsp_24xx_wkdeps,
476 .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
477 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
478};
479
480static struct clockdomain dsp_2420_clkdm = {
481 .name = "dsp_clkdm",
482 .pwrdm = { .name = "dsp_pwrdm" },
483 .flags = CLKDM_CAN_HWSUP_SWSUP,
484 .clkstctrl_reg = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
485 OMAP2_CM_CLKSTCTRL),
486 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
487 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
488};
489
490static struct clockdomain gfx_2420_clkdm = {
491 .name = "gfx_clkdm",
492 .pwrdm = { .name = "gfx_pwrdm" },
493 .flags = CLKDM_CAN_HWSUP_SWSUP,
494 .clkstctrl_reg = OMAP2420_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
495 .wkdep_srcs = gfx_sgx_wkdeps,
496 .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
497 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
498};
499
500static struct clockdomain core_l3_2420_clkdm = {
501 .name = "core_l3_clkdm",
502 .pwrdm = { .name = "core_pwrdm" },
503 .flags = CLKDM_CAN_HWSUP,
504 .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
505 .wkdep_srcs = core_24xx_wkdeps,
506 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
507 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
508};
509
510static struct clockdomain core_l4_2420_clkdm = {
511 .name = "core_l4_clkdm",
512 .pwrdm = { .name = "core_pwrdm" },
513 .flags = CLKDM_CAN_HWSUP,
514 .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
515 .wkdep_srcs = core_24xx_wkdeps,
516 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
517 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
518};
519
520static struct clockdomain dss_2420_clkdm = {
521 .name = "dss_clkdm",
522 .pwrdm = { .name = "core_pwrdm" },
523 .flags = CLKDM_CAN_HWSUP,
524 .clkstctrl_reg = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
525 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
526 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
527};
528
529#endif /* CONFIG_ARCH_OMAP2420 */
530
531
532/*
533 * 2430-only clockdomains
534 */
535
536#if defined(CONFIG_ARCH_OMAP2430)
537
538static struct clockdomain mpu_2430_clkdm = {
539 .name = "mpu_clkdm",
540 .pwrdm = { .name = "mpu_pwrdm" },
541 .flags = CLKDM_CAN_HWSUP_SWSUP,
542 .clkstctrl_reg = OMAP2430_CM_REGADDR(MPU_MOD,
543 OMAP2_CM_CLKSTCTRL),
544 .wkdep_srcs = mpu_24xx_wkdeps,
545 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
546 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
547};
548
549/* Another case of bit name collisions between several registers: EN_MDM */
550static struct clockdomain mdm_clkdm = {
551 .name = "mdm_clkdm",
552 .pwrdm = { .name = "mdm_pwrdm" },
553 .flags = CLKDM_CAN_HWSUP_SWSUP,
554 .clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP2430_MDM_MOD,
555 OMAP2_CM_CLKSTCTRL),
556 .dep_bit = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
557 .wkdep_srcs = mdm_2430_wkdeps,
558 .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
559 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
560};
561
562static struct clockdomain dsp_2430_clkdm = {
563 .name = "dsp_clkdm",
564 .pwrdm = { .name = "dsp_pwrdm" },
565 .flags = CLKDM_CAN_HWSUP_SWSUP,
566 .clkstctrl_reg = OMAP2430_CM_REGADDR(OMAP24XX_DSP_MOD,
567 OMAP2_CM_CLKSTCTRL),
568 .dep_bit = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
569 .wkdep_srcs = dsp_24xx_wkdeps,
570 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
571 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
572};
573
574static struct clockdomain gfx_2430_clkdm = {
575 .name = "gfx_clkdm",
576 .pwrdm = { .name = "gfx_pwrdm" },
577 .flags = CLKDM_CAN_HWSUP_SWSUP,
578 .clkstctrl_reg = OMAP2430_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
579 .wkdep_srcs = gfx_sgx_wkdeps,
580 .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
581 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
582};
583
584/*
585 * XXX add usecounting for clkdm dependencies, otherwise the presence
586 * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
587 * could cause trouble
588 */
589static struct clockdomain core_l3_2430_clkdm = {
590 .name = "core_l3_clkdm",
591 .pwrdm = { .name = "core_pwrdm" },
592 .flags = CLKDM_CAN_HWSUP,
593 .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
594 .dep_bit = OMAP24XX_EN_CORE_SHIFT,
595 .wkdep_srcs = core_24xx_wkdeps,
596 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
597 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
598};
599
600/*
601 * XXX add usecounting for clkdm dependencies, otherwise the presence
602 * of a single dep bit for core_l3_24xx_clkdm and core_l4_24xx_clkdm
603 * could cause trouble
604 */
605static struct clockdomain core_l4_2430_clkdm = {
606 .name = "core_l4_clkdm",
607 .pwrdm = { .name = "core_pwrdm" },
608 .flags = CLKDM_CAN_HWSUP,
609 .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
610 .dep_bit = OMAP24XX_EN_CORE_SHIFT,
611 .wkdep_srcs = core_24xx_wkdeps,
612 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
613 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
614};
615
616static struct clockdomain dss_2430_clkdm = {
617 .name = "dss_clkdm",
618 .pwrdm = { .name = "core_pwrdm" },
619 .flags = CLKDM_CAN_HWSUP,
620 .clkstctrl_reg = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
621 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
622 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
623};
624
625#endif /* CONFIG_ARCH_OMAP2430 */
626
627
628/*
629 * OMAP3 clockdomains
630 */
631
632#if defined(CONFIG_ARCH_OMAP3)
633
634static struct clockdomain mpu_3xxx_clkdm = {
635 .name = "mpu_clkdm",
636 .pwrdm = { .name = "mpu_pwrdm" },
637 .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
638 .clkstctrl_reg = OMAP34XX_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
639 .dep_bit = OMAP3430_EN_MPU_SHIFT,
640 .wkdep_srcs = mpu_3xxx_wkdeps,
641 .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
642 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
643};
644
645static struct clockdomain neon_clkdm = {
646 .name = "neon_clkdm",
647 .pwrdm = { .name = "neon_pwrdm" },
648 .flags = CLKDM_CAN_HWSUP_SWSUP,
649 .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_NEON_MOD,
650 OMAP2_CM_CLKSTCTRL),
651 .wkdep_srcs = neon_wkdeps,
652 .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
653 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
654};
655
656static struct clockdomain iva2_clkdm = {
657 .name = "iva2_clkdm",
658 .pwrdm = { .name = "iva2_pwrdm" },
659 .flags = CLKDM_CAN_HWSUP_SWSUP,
660 .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
661 OMAP2_CM_CLKSTCTRL),
662 .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
663 .wkdep_srcs = iva2_wkdeps,
664 .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
665 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
666};
667
668static struct clockdomain gfx_3430es1_clkdm = {
669 .name = "gfx_clkdm",
670 .pwrdm = { .name = "gfx_pwrdm" },
671 .flags = CLKDM_CAN_HWSUP_SWSUP,
672 .clkstctrl_reg = OMAP34XX_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
673 .wkdep_srcs = gfx_sgx_wkdeps,
674 .sleepdep_srcs = gfx_sgx_sleepdeps,
675 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
676 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
677};
678
679static struct clockdomain sgx_clkdm = {
680 .name = "sgx_clkdm",
681 .pwrdm = { .name = "sgx_pwrdm" },
682 .flags = CLKDM_CAN_HWSUP_SWSUP,
683 .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD,
684 OMAP2_CM_CLKSTCTRL),
685 .wkdep_srcs = gfx_sgx_wkdeps,
686 .sleepdep_srcs = gfx_sgx_sleepdeps,
687 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
688 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
689};
690
691/*
692 * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
693 * then that information was removed from the 34xx ES2+ TRM. It is
694 * unclear whether the core is still there, but the clockdomain logic
695 * is there, and must be programmed to an appropriate state if the
696 * CORE clockdomain is to become inactive.
697 */
698static struct clockdomain d2d_clkdm = {
699 .name = "d2d_clkdm",
700 .pwrdm = { .name = "core_pwrdm" },
701 .flags = CLKDM_CAN_HWSUP_SWSUP,
702 .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
703 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
704 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
705};
706
707/*
708 * XXX add usecounting for clkdm dependencies, otherwise the presence
709 * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
710 * could cause trouble
711 */
712static struct clockdomain core_l3_3xxx_clkdm = {
713 .name = "core_l3_clkdm",
714 .pwrdm = { .name = "core_pwrdm" },
715 .flags = CLKDM_CAN_HWSUP,
716 .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
717 .dep_bit = OMAP3430_EN_CORE_SHIFT,
718 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
719 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
720};
721
722/*
723 * XXX add usecounting for clkdm dependencies, otherwise the presence
724 * of a single dep bit for core_l3_3xxx_clkdm and core_l4_3xxx_clkdm
725 * could cause trouble
726 */
727static struct clockdomain core_l4_3xxx_clkdm = {
728 .name = "core_l4_clkdm",
729 .pwrdm = { .name = "core_pwrdm" },
730 .flags = CLKDM_CAN_HWSUP,
731 .clkstctrl_reg = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
732 .dep_bit = OMAP3430_EN_CORE_SHIFT,
733 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
734 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
735};
736
737/* Another case of bit name collisions between several registers: EN_DSS */
738static struct clockdomain dss_3xxx_clkdm = {
739 .name = "dss_clkdm",
740 .pwrdm = { .name = "dss_pwrdm" },
741 .flags = CLKDM_CAN_HWSUP_SWSUP,
742 .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD,
743 OMAP2_CM_CLKSTCTRL),
744 .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
745 .wkdep_srcs = dss_wkdeps,
746 .sleepdep_srcs = dss_sleepdeps,
747 .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
748 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
749};
750
751static struct clockdomain cam_clkdm = {
752 .name = "cam_clkdm",
753 .pwrdm = { .name = "cam_pwrdm" },
754 .flags = CLKDM_CAN_HWSUP_SWSUP,
755 .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD,
756 OMAP2_CM_CLKSTCTRL),
757 .wkdep_srcs = cam_wkdeps,
758 .sleepdep_srcs = cam_sleepdeps,
759 .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
760 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
761};
762
763static struct clockdomain usbhost_clkdm = {
764 .name = "usbhost_clkdm",
765 .pwrdm = { .name = "usbhost_pwrdm" },
766 .flags = CLKDM_CAN_HWSUP_SWSUP,
767 .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD,
768 OMAP2_CM_CLKSTCTRL),
769 .wkdep_srcs = usbhost_wkdeps,
770 .sleepdep_srcs = usbhost_sleepdeps,
771 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
772 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
773};
774
775static struct clockdomain per_clkdm = {
776 .name = "per_clkdm",
777 .pwrdm = { .name = "per_pwrdm" },
778 .flags = CLKDM_CAN_HWSUP_SWSUP,
779 .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD,
780 OMAP2_CM_CLKSTCTRL),
781 .dep_bit = OMAP3430_EN_PER_SHIFT,
782 .wkdep_srcs = per_wkdeps,
783 .sleepdep_srcs = per_sleepdeps,
784 .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
785 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
786};
787
788/*
789 * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
790 * switched of even if sdti is in use
791 */
792static struct clockdomain emu_clkdm = {
793 .name = "emu_clkdm",
794 .pwrdm = { .name = "emu_pwrdm" },
795 .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP,
796 .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD,
797 OMAP2_CM_CLKSTCTRL),
798 .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
799 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
800};
801
802static struct clockdomain dpll1_clkdm = {
803 .name = "dpll1_clkdm",
804 .pwrdm = { .name = "dpll1_pwrdm" },
805 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
806};
807
808static struct clockdomain dpll2_clkdm = {
809 .name = "dpll2_clkdm",
810 .pwrdm = { .name = "dpll2_pwrdm" },
811 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
812};
813
814static struct clockdomain dpll3_clkdm = {
815 .name = "dpll3_clkdm",
816 .pwrdm = { .name = "dpll3_pwrdm" },
817 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
818};
819
820static struct clockdomain dpll4_clkdm = {
821 .name = "dpll4_clkdm",
822 .pwrdm = { .name = "dpll4_pwrdm" },
823 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
824};
825
826static struct clockdomain dpll5_clkdm = {
827 .name = "dpll5_clkdm",
828 .pwrdm = { .name = "dpll5_pwrdm" },
829 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
830};
831
832#endif /* CONFIG_ARCH_OMAP3 */
833
834#include "clockdomains44xx.h"
835
836/*
837 * Clockdomain hwsup dependencies (OMAP3 only)
838 */
839
840static struct clkdm_autodep clkdm_autodeps[] = {
841 {
842 .clkdm = { .name = "mpu_clkdm" },
843 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
844 },
845 {
846 .clkdm = { .name = "iva2_clkdm" },
847 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
848 },
849 {
850 .clkdm = { .name = NULL },
851 }
852};
853
854/*
855 * List of clockdomain pointers per platform
856 */
857
858static struct clockdomain *clockdomains_omap[] = {
859
860#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
861 &wkup_clkdm,
862 &cm_clkdm,
863 &prm_clkdm,
864#endif
865
866#ifdef CONFIG_ARCH_OMAP2420
867 &mpu_2420_clkdm,
868 &iva1_2420_clkdm,
869 &dsp_2420_clkdm,
870 &gfx_2420_clkdm,
871 &core_l3_2420_clkdm,
872 &core_l4_2420_clkdm,
873 &dss_2420_clkdm,
874#endif
875
876#ifdef CONFIG_ARCH_OMAP2430
877 &mpu_2430_clkdm,
878 &mdm_clkdm,
879 &dsp_2430_clkdm,
880 &gfx_2430_clkdm,
881 &core_l3_2430_clkdm,
882 &core_l4_2430_clkdm,
883 &dss_2430_clkdm,
884#endif
885
886#ifdef CONFIG_ARCH_OMAP3
887 &mpu_3xxx_clkdm,
888 &neon_clkdm,
889 &iva2_clkdm,
890 &gfx_3430es1_clkdm,
891 &sgx_clkdm,
892 &d2d_clkdm,
893 &core_l3_3xxx_clkdm,
894 &core_l4_3xxx_clkdm,
895 &dss_3xxx_clkdm,
896 &cam_clkdm,
897 &usbhost_clkdm,
898 &per_clkdm,
899 &emu_clkdm,
900 &dpll1_clkdm,
901 &dpll2_clkdm,
902 &dpll3_clkdm,
903 &dpll4_clkdm,
904 &dpll5_clkdm,
905#endif
906
907#ifdef CONFIG_ARCH_OMAP4
908 &l4_cefuse_44xx_clkdm,
909 &l4_cfg_44xx_clkdm,
910 &tesla_44xx_clkdm,
911 &l3_gfx_44xx_clkdm,
912 &ivahd_44xx_clkdm,
913 &l4_secure_44xx_clkdm,
914 &l4_per_44xx_clkdm,
915 &abe_44xx_clkdm,
916 &l3_instr_44xx_clkdm,
917 &l3_init_44xx_clkdm,
918 &mpuss_44xx_clkdm,
919 &mpu0_44xx_clkdm,
920 &mpu1_44xx_clkdm,
921 &l3_emif_44xx_clkdm,
922 &l4_ao_44xx_clkdm,
923 &ducati_44xx_clkdm,
924 &l3_2_44xx_clkdm,
925 &l3_1_44xx_clkdm,
926 &l3_d2d_44xx_clkdm,
927 &iss_44xx_clkdm,
928 &l3_dss_44xx_clkdm,
929 &l4_wkup_44xx_clkdm,
930 &emu_sys_44xx_clkdm,
931 &l3_dma_44xx_clkdm,
932#endif
933
934 NULL,
935};
936
937#endif