/arch/arm/mach-omap2/clock3xxx_data.c

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  1. /*
  2. * OMAP3 clock data
  3. *
  4. * Copyright (C) 2007-2010 Texas Instruments, Inc.
  5. * Copyright (C) 2007-2010 Nokia Corporation
  6. *
  7. * Written by Paul Walmsley
  8. * With many device clock fixes by Kevin Hilman and Jouni Hรถgander
  9. * DPLL bypass clock support added by Roman Tereshonkov
  10. *
  11. */
  12. /*
  13. * Virtual clocks are introduced as convenient tools.
  14. * They are sources for other clocks and not supposed
  15. * to be requested from drivers directly.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/clk.h>
  19. #include <linux/list.h>
  20. #include <plat/control.h>
  21. #include <plat/clkdev_omap.h>
  22. #include "clock.h"
  23. #include "clock3xxx.h"
  24. #include "clock34xx.h"
  25. #include "clock36xx.h"
  26. #include "clock3517.h"
  27. #include "cm.h"
  28. #include "cm-regbits-34xx.h"
  29. #include "prm.h"
  30. #include "prm-regbits-34xx.h"
  31. /*
  32. * clocks
  33. */
  34. #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
  35. /* Maximum DPLL multiplier, divider values for OMAP3 */
  36. #define OMAP3_MAX_DPLL_MULT 2047
  37. #define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
  38. #define OMAP3_MAX_DPLL_DIV 128
  39. /*
  40. * DPLL1 supplies clock to the MPU.
  41. * DPLL2 supplies clock to the IVA2.
  42. * DPLL3 supplies CORE domain clocks.
  43. * DPLL4 supplies peripheral clocks.
  44. * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  45. */
  46. /* Forward declarations for DPLL bypass clocks */
  47. static struct clk dpll1_fck;
  48. static struct clk dpll2_fck;
  49. /* PRM CLOCKS */
  50. /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  51. static struct clk omap_32k_fck = {
  52. .name = "omap_32k_fck",
  53. .ops = &clkops_null,
  54. .rate = 32768,
  55. };
  56. static struct clk secure_32k_fck = {
  57. .name = "secure_32k_fck",
  58. .ops = &clkops_null,
  59. .rate = 32768,
  60. };
  61. /* Virtual source clocks for osc_sys_ck */
  62. static struct clk virt_12m_ck = {
  63. .name = "virt_12m_ck",
  64. .ops = &clkops_null,
  65. .rate = 12000000,
  66. };
  67. static struct clk virt_13m_ck = {
  68. .name = "virt_13m_ck",
  69. .ops = &clkops_null,
  70. .rate = 13000000,
  71. };
  72. static struct clk virt_16_8m_ck = {
  73. .name = "virt_16_8m_ck",
  74. .ops = &clkops_null,
  75. .rate = 16800000,
  76. };
  77. static struct clk virt_19_2m_ck = {
  78. .name = "virt_19_2m_ck",
  79. .ops = &clkops_null,
  80. .rate = 19200000,
  81. };
  82. static struct clk virt_26m_ck = {
  83. .name = "virt_26m_ck",
  84. .ops = &clkops_null,
  85. .rate = 26000000,
  86. };
  87. static struct clk virt_38_4m_ck = {
  88. .name = "virt_38_4m_ck",
  89. .ops = &clkops_null,
  90. .rate = 38400000,
  91. };
  92. static const struct clksel_rate osc_sys_12m_rates[] = {
  93. { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
  94. { .div = 0 }
  95. };
  96. static const struct clksel_rate osc_sys_13m_rates[] = {
  97. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  98. { .div = 0 }
  99. };
  100. static const struct clksel_rate osc_sys_16_8m_rates[] = {
  101. { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS },
  102. { .div = 0 }
  103. };
  104. static const struct clksel_rate osc_sys_19_2m_rates[] = {
  105. { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
  106. { .div = 0 }
  107. };
  108. static const struct clksel_rate osc_sys_26m_rates[] = {
  109. { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
  110. { .div = 0 }
  111. };
  112. static const struct clksel_rate osc_sys_38_4m_rates[] = {
  113. { .div = 1, .val = 4, .flags = RATE_IN_3XXX },
  114. { .div = 0 }
  115. };
  116. static const struct clksel osc_sys_clksel[] = {
  117. { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
  118. { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
  119. { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
  120. { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
  121. { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
  122. { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
  123. { .parent = NULL },
  124. };
  125. /* Oscillator clock */
  126. /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
  127. static struct clk osc_sys_ck = {
  128. .name = "osc_sys_ck",
  129. .ops = &clkops_null,
  130. .init = &omap2_init_clksel_parent,
  131. .clksel_reg = OMAP3430_PRM_CLKSEL,
  132. .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
  133. .clksel = osc_sys_clksel,
  134. /* REVISIT: deal with autoextclkmode? */
  135. .recalc = &omap2_clksel_recalc,
  136. };
  137. static const struct clksel_rate div2_rates[] = {
  138. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  139. { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
  140. { .div = 0 }
  141. };
  142. static const struct clksel sys_clksel[] = {
  143. { .parent = &osc_sys_ck, .rates = div2_rates },
  144. { .parent = NULL }
  145. };
  146. /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
  147. /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
  148. static struct clk sys_ck = {
  149. .name = "sys_ck",
  150. .ops = &clkops_null,
  151. .parent = &osc_sys_ck,
  152. .init = &omap2_init_clksel_parent,
  153. .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
  154. .clksel_mask = OMAP_SYSCLKDIV_MASK,
  155. .clksel = sys_clksel,
  156. .recalc = &omap2_clksel_recalc,
  157. };
  158. static struct clk sys_altclk = {
  159. .name = "sys_altclk",
  160. .ops = &clkops_null,
  161. };
  162. /* Optional external clock input for some McBSPs */
  163. static struct clk mcbsp_clks = {
  164. .name = "mcbsp_clks",
  165. .ops = &clkops_null,
  166. };
  167. /* PRM EXTERNAL CLOCK OUTPUT */
  168. static struct clk sys_clkout1 = {
  169. .name = "sys_clkout1",
  170. .ops = &clkops_omap2_dflt,
  171. .parent = &osc_sys_ck,
  172. .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
  173. .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
  174. .recalc = &followparent_recalc,
  175. };
  176. /* DPLLS */
  177. /* CM CLOCKS */
  178. static const struct clksel_rate div16_dpll_rates[] = {
  179. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  180. { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
  181. { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
  182. { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
  183. { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
  184. { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
  185. { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
  186. { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
  187. { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
  188. { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
  189. { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
  190. { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
  191. { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
  192. { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
  193. { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
  194. { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
  195. { .div = 0 }
  196. };
  197. static const struct clksel_rate dpll4_rates[] = {
  198. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  199. { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
  200. { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
  201. { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
  202. { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
  203. { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
  204. { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
  205. { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
  206. { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
  207. { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
  208. { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
  209. { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
  210. { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
  211. { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
  212. { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
  213. { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
  214. { .div = 17, .val = 17, .flags = RATE_IN_36XX },
  215. { .div = 18, .val = 18, .flags = RATE_IN_36XX },
  216. { .div = 19, .val = 19, .flags = RATE_IN_36XX },
  217. { .div = 20, .val = 20, .flags = RATE_IN_36XX },
  218. { .div = 21, .val = 21, .flags = RATE_IN_36XX },
  219. { .div = 22, .val = 22, .flags = RATE_IN_36XX },
  220. { .div = 23, .val = 23, .flags = RATE_IN_36XX },
  221. { .div = 24, .val = 24, .flags = RATE_IN_36XX },
  222. { .div = 25, .val = 25, .flags = RATE_IN_36XX },
  223. { .div = 26, .val = 26, .flags = RATE_IN_36XX },
  224. { .div = 27, .val = 27, .flags = RATE_IN_36XX },
  225. { .div = 28, .val = 28, .flags = RATE_IN_36XX },
  226. { .div = 29, .val = 29, .flags = RATE_IN_36XX },
  227. { .div = 30, .val = 30, .flags = RATE_IN_36XX },
  228. { .div = 31, .val = 31, .flags = RATE_IN_36XX },
  229. { .div = 32, .val = 32, .flags = RATE_IN_36XX },
  230. { .div = 0 }
  231. };
  232. /* DPLL1 */
  233. /* MPU clock source */
  234. /* Type: DPLL */
  235. static struct dpll_data dpll1_dd = {
  236. .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
  237. .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
  238. .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
  239. .clk_bypass = &dpll1_fck,
  240. .clk_ref = &sys_ck,
  241. .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
  242. .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
  243. .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
  244. .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  245. .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
  246. .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
  247. .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
  248. .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
  249. .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
  250. .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
  251. .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
  252. .max_multiplier = OMAP3_MAX_DPLL_MULT,
  253. .min_divider = 1,
  254. .max_divider = OMAP3_MAX_DPLL_DIV,
  255. .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
  256. };
  257. static struct clk dpll1_ck = {
  258. .name = "dpll1_ck",
  259. .ops = &clkops_null,
  260. .parent = &sys_ck,
  261. .dpll_data = &dpll1_dd,
  262. .round_rate = &omap2_dpll_round_rate,
  263. .set_rate = &omap3_noncore_dpll_set_rate,
  264. .clkdm_name = "dpll1_clkdm",
  265. .recalc = &omap3_dpll_recalc,
  266. };
  267. /*
  268. * This virtual clock provides the CLKOUTX2 output from the DPLL if the
  269. * DPLL isn't bypassed.
  270. */
  271. static struct clk dpll1_x2_ck = {
  272. .name = "dpll1_x2_ck",
  273. .ops = &clkops_null,
  274. .parent = &dpll1_ck,
  275. .clkdm_name = "dpll1_clkdm",
  276. .recalc = &omap3_clkoutx2_recalc,
  277. };
  278. /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
  279. static const struct clksel div16_dpll1_x2m2_clksel[] = {
  280. { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
  281. { .parent = NULL }
  282. };
  283. /*
  284. * Does not exist in the TRM - needed to separate the M2 divider from
  285. * bypass selection in mpu_ck
  286. */
  287. static struct clk dpll1_x2m2_ck = {
  288. .name = "dpll1_x2m2_ck",
  289. .ops = &clkops_null,
  290. .parent = &dpll1_x2_ck,
  291. .init = &omap2_init_clksel_parent,
  292. .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
  293. .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
  294. .clksel = div16_dpll1_x2m2_clksel,
  295. .clkdm_name = "dpll1_clkdm",
  296. .recalc = &omap2_clksel_recalc,
  297. };
  298. /* DPLL2 */
  299. /* IVA2 clock source */
  300. /* Type: DPLL */
  301. static struct dpll_data dpll2_dd = {
  302. .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
  303. .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
  304. .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
  305. .clk_bypass = &dpll2_fck,
  306. .clk_ref = &sys_ck,
  307. .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
  308. .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
  309. .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
  310. .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
  311. (1 << DPLL_LOW_POWER_BYPASS),
  312. .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
  313. .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
  314. .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
  315. .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
  316. .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
  317. .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
  318. .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
  319. .max_multiplier = OMAP3_MAX_DPLL_MULT,
  320. .min_divider = 1,
  321. .max_divider = OMAP3_MAX_DPLL_DIV,
  322. .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
  323. };
  324. static struct clk dpll2_ck = {
  325. .name = "dpll2_ck",
  326. .ops = &clkops_omap3_noncore_dpll_ops,
  327. .parent = &sys_ck,
  328. .dpll_data = &dpll2_dd,
  329. .round_rate = &omap2_dpll_round_rate,
  330. .set_rate = &omap3_noncore_dpll_set_rate,
  331. .clkdm_name = "dpll2_clkdm",
  332. .recalc = &omap3_dpll_recalc,
  333. };
  334. static const struct clksel div16_dpll2_m2x2_clksel[] = {
  335. { .parent = &dpll2_ck, .rates = div16_dpll_rates },
  336. { .parent = NULL }
  337. };
  338. /*
  339. * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
  340. * or CLKOUTX2. CLKOUT seems most plausible.
  341. */
  342. static struct clk dpll2_m2_ck = {
  343. .name = "dpll2_m2_ck",
  344. .ops = &clkops_null,
  345. .parent = &dpll2_ck,
  346. .init = &omap2_init_clksel_parent,
  347. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
  348. OMAP3430_CM_CLKSEL2_PLL),
  349. .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
  350. .clksel = div16_dpll2_m2x2_clksel,
  351. .clkdm_name = "dpll2_clkdm",
  352. .recalc = &omap2_clksel_recalc,
  353. };
  354. /*
  355. * DPLL3
  356. * Source clock for all interfaces and for some device fclks
  357. * REVISIT: Also supports fast relock bypass - not included below
  358. */
  359. static struct dpll_data dpll3_dd = {
  360. .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  361. .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
  362. .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
  363. .clk_bypass = &sys_ck,
  364. .clk_ref = &sys_ck,
  365. .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
  366. .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  367. .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
  368. .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
  369. .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
  370. .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
  371. .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
  372. .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
  373. .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
  374. .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
  375. .max_multiplier = OMAP3_MAX_DPLL_MULT,
  376. .min_divider = 1,
  377. .max_divider = OMAP3_MAX_DPLL_DIV,
  378. .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
  379. };
  380. static struct clk dpll3_ck = {
  381. .name = "dpll3_ck",
  382. .ops = &clkops_null,
  383. .parent = &sys_ck,
  384. .dpll_data = &dpll3_dd,
  385. .round_rate = &omap2_dpll_round_rate,
  386. .clkdm_name = "dpll3_clkdm",
  387. .recalc = &omap3_dpll_recalc,
  388. };
  389. /*
  390. * This virtual clock provides the CLKOUTX2 output from the DPLL if the
  391. * DPLL isn't bypassed
  392. */
  393. static struct clk dpll3_x2_ck = {
  394. .name = "dpll3_x2_ck",
  395. .ops = &clkops_null,
  396. .parent = &dpll3_ck,
  397. .clkdm_name = "dpll3_clkdm",
  398. .recalc = &omap3_clkoutx2_recalc,
  399. };
  400. static const struct clksel_rate div31_dpll3_rates[] = {
  401. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  402. { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
  403. { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS },
  404. { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS },
  405. { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS },
  406. { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS },
  407. { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS },
  408. { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS },
  409. { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS },
  410. { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS },
  411. { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS },
  412. { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS },
  413. { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS },
  414. { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS },
  415. { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS },
  416. { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS },
  417. { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS },
  418. { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS },
  419. { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS },
  420. { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS },
  421. { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS },
  422. { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS },
  423. { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS },
  424. { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS },
  425. { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS },
  426. { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS },
  427. { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS },
  428. { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS },
  429. { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS },
  430. { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS },
  431. { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS },
  432. { .div = 0 },
  433. };
  434. static const struct clksel div31_dpll3m2_clksel[] = {
  435. { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
  436. { .parent = NULL }
  437. };
  438. /* DPLL3 output M2 - primary control point for CORE speed */
  439. static struct clk dpll3_m2_ck = {
  440. .name = "dpll3_m2_ck",
  441. .ops = &clkops_null,
  442. .parent = &dpll3_ck,
  443. .init = &omap2_init_clksel_parent,
  444. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  445. .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
  446. .clksel = div31_dpll3m2_clksel,
  447. .clkdm_name = "dpll3_clkdm",
  448. .round_rate = &omap2_clksel_round_rate,
  449. .set_rate = &omap3_core_dpll_m2_set_rate,
  450. .recalc = &omap2_clksel_recalc,
  451. };
  452. static struct clk core_ck = {
  453. .name = "core_ck",
  454. .ops = &clkops_null,
  455. .parent = &dpll3_m2_ck,
  456. .recalc = &followparent_recalc,
  457. };
  458. static struct clk dpll3_m2x2_ck = {
  459. .name = "dpll3_m2x2_ck",
  460. .ops = &clkops_null,
  461. .parent = &dpll3_m2_ck,
  462. .clkdm_name = "dpll3_clkdm",
  463. .recalc = &omap3_clkoutx2_recalc,
  464. };
  465. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  466. static const struct clksel div16_dpll3_clksel[] = {
  467. { .parent = &dpll3_ck, .rates = div16_dpll_rates },
  468. { .parent = NULL }
  469. };
  470. /* This virtual clock is the source for dpll3_m3x2_ck */
  471. static struct clk dpll3_m3_ck = {
  472. .name = "dpll3_m3_ck",
  473. .ops = &clkops_null,
  474. .parent = &dpll3_ck,
  475. .init = &omap2_init_clksel_parent,
  476. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  477. .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
  478. .clksel = div16_dpll3_clksel,
  479. .clkdm_name = "dpll3_clkdm",
  480. .recalc = &omap2_clksel_recalc,
  481. };
  482. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  483. static struct clk dpll3_m3x2_ck = {
  484. .name = "dpll3_m3x2_ck",
  485. .ops = &clkops_omap2_dflt_wait,
  486. .parent = &dpll3_m3_ck,
  487. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  488. .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
  489. .flags = INVERT_ENABLE,
  490. .clkdm_name = "dpll3_clkdm",
  491. .recalc = &omap3_clkoutx2_recalc,
  492. };
  493. static struct clk emu_core_alwon_ck = {
  494. .name = "emu_core_alwon_ck",
  495. .ops = &clkops_null,
  496. .parent = &dpll3_m3x2_ck,
  497. .clkdm_name = "dpll3_clkdm",
  498. .recalc = &followparent_recalc,
  499. };
  500. /* DPLL4 */
  501. /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
  502. /* Type: DPLL */
  503. static struct dpll_data dpll4_dd;
  504. static struct dpll_data dpll4_dd_34xx __initdata = {
  505. .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
  506. .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
  507. .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
  508. .clk_bypass = &sys_ck,
  509. .clk_ref = &sys_ck,
  510. .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
  511. .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  512. .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
  513. .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
  514. .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
  515. .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
  516. .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
  517. .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
  518. .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
  519. .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
  520. .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
  521. .max_multiplier = OMAP3_MAX_DPLL_MULT,
  522. .min_divider = 1,
  523. .max_divider = OMAP3_MAX_DPLL_DIV,
  524. .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
  525. };
  526. static struct dpll_data dpll4_dd_3630 __initdata = {
  527. .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
  528. .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
  529. .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
  530. .clk_bypass = &sys_ck,
  531. .clk_ref = &sys_ck,
  532. .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  533. .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
  534. .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
  535. .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
  536. .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
  537. .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
  538. .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
  539. .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
  540. .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
  541. .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
  542. .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
  543. .min_divider = 1,
  544. .max_divider = OMAP3_MAX_DPLL_DIV,
  545. .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
  546. .flags = DPLL_J_TYPE
  547. };
  548. static struct clk dpll4_ck = {
  549. .name = "dpll4_ck",
  550. .ops = &clkops_omap3_noncore_dpll_ops,
  551. .parent = &sys_ck,
  552. .dpll_data = &dpll4_dd,
  553. .round_rate = &omap2_dpll_round_rate,
  554. .set_rate = &omap3_dpll4_set_rate,
  555. .clkdm_name = "dpll4_clkdm",
  556. .recalc = &omap3_dpll_recalc,
  557. };
  558. /*
  559. * This virtual clock provides the CLKOUTX2 output from the DPLL if the
  560. * DPLL isn't bypassed --
  561. * XXX does this serve any downstream clocks?
  562. */
  563. static struct clk dpll4_x2_ck = {
  564. .name = "dpll4_x2_ck",
  565. .ops = &clkops_null,
  566. .parent = &dpll4_ck,
  567. .clkdm_name = "dpll4_clkdm",
  568. .recalc = &omap3_clkoutx2_recalc,
  569. };
  570. static const struct clksel dpll4_clksel[] = {
  571. { .parent = &dpll4_ck, .rates = dpll4_rates },
  572. { .parent = NULL }
  573. };
  574. /* This virtual clock is the source for dpll4_m2x2_ck */
  575. static struct clk dpll4_m2_ck = {
  576. .name = "dpll4_m2_ck",
  577. .ops = &clkops_null,
  578. .parent = &dpll4_ck,
  579. .init = &omap2_init_clksel_parent,
  580. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
  581. .clksel_mask = OMAP3630_DIV_96M_MASK,
  582. .clksel = dpll4_clksel,
  583. .clkdm_name = "dpll4_clkdm",
  584. .recalc = &omap2_clksel_recalc,
  585. };
  586. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  587. static struct clk dpll4_m2x2_ck = {
  588. .name = "dpll4_m2x2_ck",
  589. .ops = &clkops_omap2_dflt_wait,
  590. .parent = &dpll4_m2_ck,
  591. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  592. .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
  593. .flags = INVERT_ENABLE,
  594. .clkdm_name = "dpll4_clkdm",
  595. .recalc = &omap3_clkoutx2_recalc,
  596. };
  597. /*
  598. * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
  599. * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM:
  600. * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
  601. * CM_96K_(F)CLK.
  602. */
  603. /* Adding 192MHz Clock node needed by SGX */
  604. static struct clk omap_192m_alwon_fck = {
  605. .name = "omap_192m_alwon_fck",
  606. .ops = &clkops_null,
  607. .parent = &dpll4_m2x2_ck,
  608. .recalc = &followparent_recalc,
  609. };
  610. static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
  611. { .div = 1, .val = 1, .flags = RATE_IN_36XX },
  612. { .div = 2, .val = 2, .flags = RATE_IN_36XX },
  613. { .div = 0 }
  614. };
  615. static const struct clksel omap_96m_alwon_fck_clksel[] = {
  616. { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
  617. { .parent = NULL }
  618. };
  619. static const struct clksel_rate omap_96m_dpll_rates[] = {
  620. { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
  621. { .div = 0 }
  622. };
  623. static const struct clksel_rate omap_96m_sys_rates[] = {
  624. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  625. { .div = 0 }
  626. };
  627. static struct clk omap_96m_alwon_fck = {
  628. .name = "omap_96m_alwon_fck",
  629. .ops = &clkops_null,
  630. .parent = &dpll4_m2x2_ck,
  631. .recalc = &followparent_recalc,
  632. };
  633. static struct clk omap_96m_alwon_fck_3630 = {
  634. .name = "omap_96m_alwon_fck",
  635. .parent = &omap_192m_alwon_fck,
  636. .init = &omap2_init_clksel_parent,
  637. .ops = &clkops_null,
  638. .recalc = &omap2_clksel_recalc,
  639. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  640. .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
  641. .clksel = omap_96m_alwon_fck_clksel
  642. };
  643. static struct clk cm_96m_fck = {
  644. .name = "cm_96m_fck",
  645. .ops = &clkops_null,
  646. .parent = &omap_96m_alwon_fck,
  647. .recalc = &followparent_recalc,
  648. };
  649. static const struct clksel omap_96m_fck_clksel[] = {
  650. { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
  651. { .parent = &sys_ck, .rates = omap_96m_sys_rates },
  652. { .parent = NULL }
  653. };
  654. static struct clk omap_96m_fck = {
  655. .name = "omap_96m_fck",
  656. .ops = &clkops_null,
  657. .parent = &sys_ck,
  658. .init = &omap2_init_clksel_parent,
  659. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  660. .clksel_mask = OMAP3430_SOURCE_96M_MASK,
  661. .clksel = omap_96m_fck_clksel,
  662. .recalc = &omap2_clksel_recalc,
  663. };
  664. /* This virtual clock is the source for dpll4_m3x2_ck */
  665. static struct clk dpll4_m3_ck = {
  666. .name = "dpll4_m3_ck",
  667. .ops = &clkops_null,
  668. .parent = &dpll4_ck,
  669. .init = &omap2_init_clksel_parent,
  670. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
  671. .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
  672. .clksel = dpll4_clksel,
  673. .clkdm_name = "dpll4_clkdm",
  674. .recalc = &omap2_clksel_recalc,
  675. };
  676. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  677. static struct clk dpll4_m3x2_ck = {
  678. .name = "dpll4_m3x2_ck",
  679. .ops = &clkops_omap2_dflt_wait,
  680. .parent = &dpll4_m3_ck,
  681. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  682. .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
  683. .flags = INVERT_ENABLE,
  684. .clkdm_name = "dpll4_clkdm",
  685. .recalc = &omap3_clkoutx2_recalc,
  686. };
  687. static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
  688. { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
  689. { .div = 0 }
  690. };
  691. static const struct clksel_rate omap_54m_alt_rates[] = {
  692. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  693. { .div = 0 }
  694. };
  695. static const struct clksel omap_54m_clksel[] = {
  696. { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
  697. { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
  698. { .parent = NULL }
  699. };
  700. static struct clk omap_54m_fck = {
  701. .name = "omap_54m_fck",
  702. .ops = &clkops_null,
  703. .init = &omap2_init_clksel_parent,
  704. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  705. .clksel_mask = OMAP3430_SOURCE_54M_MASK,
  706. .clksel = omap_54m_clksel,
  707. .recalc = &omap2_clksel_recalc,
  708. };
  709. static const struct clksel_rate omap_48m_cm96m_rates[] = {
  710. { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
  711. { .div = 0 }
  712. };
  713. static const struct clksel_rate omap_48m_alt_rates[] = {
  714. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  715. { .div = 0 }
  716. };
  717. static const struct clksel omap_48m_clksel[] = {
  718. { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
  719. { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
  720. { .parent = NULL }
  721. };
  722. static struct clk omap_48m_fck = {
  723. .name = "omap_48m_fck",
  724. .ops = &clkops_null,
  725. .init = &omap2_init_clksel_parent,
  726. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
  727. .clksel_mask = OMAP3430_SOURCE_48M_MASK,
  728. .clksel = omap_48m_clksel,
  729. .recalc = &omap2_clksel_recalc,
  730. };
  731. static struct clk omap_12m_fck = {
  732. .name = "omap_12m_fck",
  733. .ops = &clkops_null,
  734. .parent = &omap_48m_fck,
  735. .fixed_div = 4,
  736. .recalc = &omap_fixed_divisor_recalc,
  737. };
  738. /* This virtual clock is the source for dpll4_m4x2_ck */
  739. static struct clk dpll4_m4_ck = {
  740. .name = "dpll4_m4_ck",
  741. .ops = &clkops_null,
  742. .parent = &dpll4_ck,
  743. .init = &omap2_init_clksel_parent,
  744. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
  745. .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
  746. .clksel = dpll4_clksel,
  747. .clkdm_name = "dpll4_clkdm",
  748. .recalc = &omap2_clksel_recalc,
  749. .set_rate = &omap2_clksel_set_rate,
  750. .round_rate = &omap2_clksel_round_rate,
  751. };
  752. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  753. static struct clk dpll4_m4x2_ck = {
  754. .name = "dpll4_m4x2_ck",
  755. .ops = &clkops_omap2_dflt_wait,
  756. .parent = &dpll4_m4_ck,
  757. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  758. .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
  759. .flags = INVERT_ENABLE,
  760. .clkdm_name = "dpll4_clkdm",
  761. .recalc = &omap3_clkoutx2_recalc,
  762. };
  763. /* This virtual clock is the source for dpll4_m5x2_ck */
  764. static struct clk dpll4_m5_ck = {
  765. .name = "dpll4_m5_ck",
  766. .ops = &clkops_null,
  767. .parent = &dpll4_ck,
  768. .init = &omap2_init_clksel_parent,
  769. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
  770. .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
  771. .clksel = dpll4_clksel,
  772. .clkdm_name = "dpll4_clkdm",
  773. .set_rate = &omap2_clksel_set_rate,
  774. .round_rate = &omap2_clksel_round_rate,
  775. .recalc = &omap2_clksel_recalc,
  776. };
  777. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  778. static struct clk dpll4_m5x2_ck = {
  779. .name = "dpll4_m5x2_ck",
  780. .ops = &clkops_omap2_dflt_wait,
  781. .parent = &dpll4_m5_ck,
  782. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  783. .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
  784. .flags = INVERT_ENABLE,
  785. .clkdm_name = "dpll4_clkdm",
  786. .recalc = &omap3_clkoutx2_recalc,
  787. };
  788. /* This virtual clock is the source for dpll4_m6x2_ck */
  789. static struct clk dpll4_m6_ck = {
  790. .name = "dpll4_m6_ck",
  791. .ops = &clkops_null,
  792. .parent = &dpll4_ck,
  793. .init = &omap2_init_clksel_parent,
  794. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
  795. .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
  796. .clksel = dpll4_clksel,
  797. .clkdm_name = "dpll4_clkdm",
  798. .recalc = &omap2_clksel_recalc,
  799. };
  800. /* The PWRDN bit is apparently only available on 3430ES2 and above */
  801. static struct clk dpll4_m6x2_ck = {
  802. .name = "dpll4_m6x2_ck",
  803. .ops = &clkops_omap2_dflt_wait,
  804. .parent = &dpll4_m6_ck,
  805. .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
  806. .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
  807. .flags = INVERT_ENABLE,
  808. .clkdm_name = "dpll4_clkdm",
  809. .recalc = &omap3_clkoutx2_recalc,
  810. };
  811. static struct clk emu_per_alwon_ck = {
  812. .name = "emu_per_alwon_ck",
  813. .ops = &clkops_null,
  814. .parent = &dpll4_m6x2_ck,
  815. .clkdm_name = "dpll4_clkdm",
  816. .recalc = &followparent_recalc,
  817. };
  818. /* DPLL5 */
  819. /* Supplies 120MHz clock, USIM source clock */
  820. /* Type: DPLL */
  821. /* 3430ES2 only */
  822. static struct dpll_data dpll5_dd = {
  823. .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
  824. .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
  825. .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
  826. .clk_bypass = &sys_ck,
  827. .clk_ref = &sys_ck,
  828. .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
  829. .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
  830. .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
  831. .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
  832. .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
  833. .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
  834. .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
  835. .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
  836. .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
  837. .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
  838. .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
  839. .max_multiplier = OMAP3_MAX_DPLL_MULT,
  840. .min_divider = 1,
  841. .max_divider = OMAP3_MAX_DPLL_DIV,
  842. .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
  843. };
  844. static struct clk dpll5_ck = {
  845. .name = "dpll5_ck",
  846. .ops = &clkops_omap3_noncore_dpll_ops,
  847. .parent = &sys_ck,
  848. .dpll_data = &dpll5_dd,
  849. .round_rate = &omap2_dpll_round_rate,
  850. .set_rate = &omap3_noncore_dpll_set_rate,
  851. .clkdm_name = "dpll5_clkdm",
  852. .recalc = &omap3_dpll_recalc,
  853. };
  854. static const struct clksel div16_dpll5_clksel[] = {
  855. { .parent = &dpll5_ck, .rates = div16_dpll_rates },
  856. { .parent = NULL }
  857. };
  858. static struct clk dpll5_m2_ck = {
  859. .name = "dpll5_m2_ck",
  860. .ops = &clkops_null,
  861. .parent = &dpll5_ck,
  862. .init = &omap2_init_clksel_parent,
  863. .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
  864. .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
  865. .clksel = div16_dpll5_clksel,
  866. .clkdm_name = "dpll5_clkdm",
  867. .recalc = &omap2_clksel_recalc,
  868. };
  869. /* CM EXTERNAL CLOCK OUTPUTS */
  870. static const struct clksel_rate clkout2_src_core_rates[] = {
  871. { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
  872. { .div = 0 }
  873. };
  874. static const struct clksel_rate clkout2_src_sys_rates[] = {
  875. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  876. { .div = 0 }
  877. };
  878. static const struct clksel_rate clkout2_src_96m_rates[] = {
  879. { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
  880. { .div = 0 }
  881. };
  882. static const struct clksel_rate clkout2_src_54m_rates[] = {
  883. { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
  884. { .div = 0 }
  885. };
  886. static const struct clksel clkout2_src_clksel[] = {
  887. { .parent = &core_ck, .rates = clkout2_src_core_rates },
  888. { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
  889. { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
  890. { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
  891. { .parent = NULL }
  892. };
  893. static struct clk clkout2_src_ck = {
  894. .name = "clkout2_src_ck",
  895. .ops = &clkops_omap2_dflt,
  896. .init = &omap2_init_clksel_parent,
  897. .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
  898. .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
  899. .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
  900. .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
  901. .clksel = clkout2_src_clksel,
  902. .clkdm_name = "core_clkdm",
  903. .recalc = &omap2_clksel_recalc,
  904. };
  905. static const struct clksel_rate sys_clkout2_rates[] = {
  906. { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
  907. { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
  908. { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
  909. { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
  910. { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
  911. { .div = 0 },
  912. };
  913. static const struct clksel sys_clkout2_clksel[] = {
  914. { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
  915. { .parent = NULL },
  916. };
  917. static struct clk sys_clkout2 = {
  918. .name = "sys_clkout2",
  919. .ops = &clkops_null,
  920. .init = &omap2_init_clksel_parent,
  921. .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
  922. .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
  923. .clksel = sys_clkout2_clksel,
  924. .recalc = &omap2_clksel_recalc,
  925. .round_rate = &omap2_clksel_round_rate,
  926. .set_rate = &omap2_clksel_set_rate
  927. };
  928. /* CM OUTPUT CLOCKS */
  929. static struct clk corex2_fck = {
  930. .name = "corex2_fck",
  931. .ops = &clkops_null,
  932. .parent = &dpll3_m2x2_ck,
  933. .recalc = &followparent_recalc,
  934. };
  935. /* DPLL power domain clock controls */
  936. static const struct clksel_rate div4_rates[] = {
  937. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  938. { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
  939. { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
  940. { .div = 0 }
  941. };
  942. static const struct clksel div4_core_clksel[] = {
  943. { .parent = &core_ck, .rates = div4_rates },
  944. { .parent = NULL }
  945. };
  946. /*
  947. * REVISIT: Are these in DPLL power domain or CM power domain? docs
  948. * may be inconsistent here?
  949. */
  950. static struct clk dpll1_fck = {
  951. .name = "dpll1_fck",
  952. .ops = &clkops_null,
  953. .parent = &core_ck,
  954. .init = &omap2_init_clksel_parent,
  955. .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
  956. .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
  957. .clksel = div4_core_clksel,
  958. .recalc = &omap2_clksel_recalc,
  959. };
  960. static struct clk mpu_ck = {
  961. .name = "mpu_ck",
  962. .ops = &clkops_null,
  963. .parent = &dpll1_x2m2_ck,
  964. .clkdm_name = "mpu_clkdm",
  965. .recalc = &followparent_recalc,
  966. };
  967. /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
  968. static const struct clksel_rate arm_fck_rates[] = {
  969. { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
  970. { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
  971. { .div = 0 },
  972. };
  973. static const struct clksel arm_fck_clksel[] = {
  974. { .parent = &mpu_ck, .rates = arm_fck_rates },
  975. { .parent = NULL }
  976. };
  977. static struct clk arm_fck = {
  978. .name = "arm_fck",
  979. .ops = &clkops_null,
  980. .parent = &mpu_ck,
  981. .init = &omap2_init_clksel_parent,
  982. .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
  983. .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
  984. .clksel = arm_fck_clksel,
  985. .clkdm_name = "mpu_clkdm",
  986. .recalc = &omap2_clksel_recalc,
  987. };
  988. /* XXX What about neon_clkdm ? */
  989. /*
  990. * REVISIT: This clock is never specifically defined in the 3430 TRM,
  991. * although it is referenced - so this is a guess
  992. */
  993. static struct clk emu_mpu_alwon_ck = {
  994. .name = "emu_mpu_alwon_ck",
  995. .ops = &clkops_null,
  996. .parent = &mpu_ck,
  997. .recalc = &followparent_recalc,
  998. };
  999. static struct clk dpll2_fck = {
  1000. .name = "dpll2_fck",
  1001. .ops = &clkops_null,
  1002. .parent = &core_ck,
  1003. .init = &omap2_init_clksel_parent,
  1004. .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
  1005. .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
  1006. .clksel = div4_core_clksel,
  1007. .recalc = &omap2_clksel_recalc,
  1008. };
  1009. static struct clk iva2_ck = {
  1010. .name = "iva2_ck",
  1011. .ops = &clkops_omap2_dflt_wait,
  1012. .parent = &dpll2_m2_ck,
  1013. .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
  1014. .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
  1015. .clkdm_name = "iva2_clkdm",
  1016. .recalc = &followparent_recalc,
  1017. };
  1018. /* Common interface clocks */
  1019. static const struct clksel div2_core_clksel[] = {
  1020. { .parent = &core_ck, .rates = div2_rates },
  1021. { .parent = NULL }
  1022. };
  1023. static struct clk l3_ick = {
  1024. .name = "l3_ick",
  1025. .ops = &clkops_null,
  1026. .parent = &core_ck,
  1027. .init = &omap2_init_clksel_parent,
  1028. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1029. .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
  1030. .clksel = div2_core_clksel,
  1031. .clkdm_name = "core_l3_clkdm",
  1032. .recalc = &omap2_clksel_recalc,
  1033. };
  1034. static const struct clksel div2_l3_clksel[] = {
  1035. { .parent = &l3_ick, .rates = div2_rates },
  1036. { .parent = NULL }
  1037. };
  1038. static struct clk l4_ick = {
  1039. .name = "l4_ick",
  1040. .ops = &clkops_null,
  1041. .parent = &l3_ick,
  1042. .init = &omap2_init_clksel_parent,
  1043. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1044. .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
  1045. .clksel = div2_l3_clksel,
  1046. .clkdm_name = "core_l4_clkdm",
  1047. .recalc = &omap2_clksel_recalc,
  1048. };
  1049. static const struct clksel div2_l4_clksel[] = {
  1050. { .parent = &l4_ick, .rates = div2_rates },
  1051. { .parent = NULL }
  1052. };
  1053. static struct clk rm_ick = {
  1054. .name = "rm_ick",
  1055. .ops = &clkops_null,
  1056. .parent = &l4_ick,
  1057. .init = &omap2_init_clksel_parent,
  1058. .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
  1059. .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
  1060. .clksel = div2_l4_clksel,
  1061. .recalc = &omap2_clksel_recalc,
  1062. };
  1063. /* GFX power domain */
  1064. /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
  1065. static const struct clksel gfx_l3_clksel[] = {
  1066. { .parent = &l3_ick, .rates = gfx_l3_rates },
  1067. { .parent = NULL }
  1068. };
  1069. /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
  1070. static struct clk gfx_l3_ck = {
  1071. .name = "gfx_l3_ck",
  1072. .ops = &clkops_omap2_dflt_wait,
  1073. .parent = &l3_ick,
  1074. .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
  1075. .enable_bit = OMAP_EN_GFX_SHIFT,
  1076. .recalc = &followparent_recalc,
  1077. };
  1078. static struct clk gfx_l3_fck = {
  1079. .name = "gfx_l3_fck",
  1080. .ops = &clkops_null,
  1081. .parent = &gfx_l3_ck,
  1082. .init = &omap2_init_clksel_parent,
  1083. .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
  1084. .clksel_mask = OMAP_CLKSEL_GFX_MASK,
  1085. .clksel = gfx_l3_clksel,
  1086. .clkdm_name = "gfx_3430es1_clkdm",
  1087. .recalc = &omap2_clksel_recalc,
  1088. };
  1089. static struct clk gfx_l3_ick = {
  1090. .name = "gfx_l3_ick",
  1091. .ops = &clkops_null,
  1092. .parent = &gfx_l3_ck,
  1093. .clkdm_name = "gfx_3430es1_clkdm",
  1094. .recalc = &followparent_recalc,
  1095. };
  1096. static struct clk gfx_cg1_ck = {
  1097. .name = "gfx_cg1_ck",
  1098. .ops = &clkops_omap2_dflt_wait,
  1099. .parent = &gfx_l3_fck, /* REVISIT: correct? */
  1100. .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
  1101. .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
  1102. .clkdm_name = "gfx_3430es1_clkdm",
  1103. .recalc = &followparent_recalc,
  1104. };
  1105. static struct clk gfx_cg2_ck = {
  1106. .name = "gfx_cg2_ck",
  1107. .ops = &clkops_omap2_dflt_wait,
  1108. .parent = &gfx_l3_fck, /* REVISIT: correct? */
  1109. .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
  1110. .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
  1111. .clkdm_name = "gfx_3430es1_clkdm",
  1112. .recalc = &followparent_recalc,
  1113. };
  1114. /* SGX power domain - 3430ES2 only */
  1115. static const struct clksel_rate sgx_core_rates[] = {
  1116. { .div = 2, .val = 5, .flags = RATE_IN_36XX },
  1117. { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
  1118. { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
  1119. { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
  1120. { .div = 0 },
  1121. };
  1122. static const struct clksel_rate sgx_192m_rates[] = {
  1123. { .div = 1, .val = 4, .flags = RATE_IN_36XX },
  1124. { .div = 0 },
  1125. };
  1126. static const struct clksel_rate sgx_corex2_rates[] = {
  1127. { .div = 3, .val = 6, .flags = RATE_IN_36XX },
  1128. { .div = 5, .val = 7, .flags = RATE_IN_36XX },
  1129. { .div = 0 },
  1130. };
  1131. static const struct clksel_rate sgx_96m_rates[] = {
  1132. { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
  1133. { .div = 0 },
  1134. };
  1135. static const struct clksel sgx_clksel[] = {
  1136. { .parent = &core_ck, .rates = sgx_core_rates },
  1137. { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
  1138. { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
  1139. { .parent = &corex2_fck, .rates = sgx_corex2_rates },
  1140. { .parent = NULL }
  1141. };
  1142. static struct clk sgx_fck = {
  1143. .name = "sgx_fck",
  1144. .ops = &clkops_omap2_dflt_wait,
  1145. .init = &omap2_init_clksel_parent,
  1146. .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
  1147. .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
  1148. .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
  1149. .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
  1150. .clksel = sgx_clksel,
  1151. .clkdm_name = "sgx_clkdm",
  1152. .recalc = &omap2_clksel_recalc,
  1153. .set_rate = &omap2_clksel_set_rate,
  1154. .round_rate = &omap2_clksel_round_rate
  1155. };
  1156. static struct clk sgx_ick = {
  1157. .name = "sgx_ick",
  1158. .ops = &clkops_omap2_dflt_wait,
  1159. .parent = &l3_ick,
  1160. .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
  1161. .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
  1162. .clkdm_name = "sgx_clkdm",
  1163. .recalc = &followparent_recalc,
  1164. };
  1165. /* CORE power domain */
  1166. static struct clk d2d_26m_fck = {
  1167. .name = "d2d_26m_fck",
  1168. .ops = &clkops_omap2_dflt_wait,
  1169. .parent = &sys_ck,
  1170. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1171. .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
  1172. .clkdm_name = "d2d_clkdm",
  1173. .recalc = &followparent_recalc,
  1174. };
  1175. static struct clk modem_fck = {
  1176. .name = "modem_fck",
  1177. .ops = &clkops_omap2_dflt_wait,
  1178. .parent = &sys_ck,
  1179. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1180. .enable_bit = OMAP3430_EN_MODEM_SHIFT,
  1181. .clkdm_name = "d2d_clkdm",
  1182. .recalc = &followparent_recalc,
  1183. };
  1184. static struct clk sad2d_ick = {
  1185. .name = "sad2d_ick",
  1186. .ops = &clkops_omap2_dflt_wait,
  1187. .parent = &l3_ick,
  1188. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
  1189. .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
  1190. .clkdm_name = "d2d_clkdm",
  1191. .recalc = &followparent_recalc,
  1192. };
  1193. static struct clk mad2d_ick = {
  1194. .name = "mad2d_ick",
  1195. .ops = &clkops_omap2_dflt_wait,
  1196. .parent = &l3_ick,
  1197. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
  1198. .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
  1199. .clkdm_name = "d2d_clkdm",
  1200. .recalc = &followparent_recalc,
  1201. };
  1202. static const struct clksel omap343x_gpt_clksel[] = {
  1203. { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
  1204. { .parent = &sys_ck, .rates = gpt_sys_rates },
  1205. { .parent = NULL}
  1206. };
  1207. static struct clk gpt10_fck = {
  1208. .name = "gpt10_fck",
  1209. .ops = &clkops_omap2_dflt_wait,
  1210. .parent = &sys_ck,
  1211. .init = &omap2_init_clksel_parent,
  1212. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1213. .enable_bit = OMAP3430_EN_GPT10_SHIFT,
  1214. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1215. .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
  1216. .clksel = omap343x_gpt_clksel,
  1217. .clkdm_name = "core_l4_clkdm",
  1218. .recalc = &omap2_clksel_recalc,
  1219. };
  1220. static struct clk gpt11_fck = {
  1221. .name = "gpt11_fck",
  1222. .ops = &clkops_omap2_dflt_wait,
  1223. .parent = &sys_ck,
  1224. .init = &omap2_init_clksel_parent,
  1225. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1226. .enable_bit = OMAP3430_EN_GPT11_SHIFT,
  1227. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1228. .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
  1229. .clksel = omap343x_gpt_clksel,
  1230. .clkdm_name = "core_l4_clkdm",
  1231. .recalc = &omap2_clksel_recalc,
  1232. };
  1233. static struct clk cpefuse_fck = {
  1234. .name = "cpefuse_fck",
  1235. .ops = &clkops_omap2_dflt,
  1236. .parent = &sys_ck,
  1237. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
  1238. .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
  1239. .recalc = &followparent_recalc,
  1240. };
  1241. static struct clk ts_fck = {
  1242. .name = "ts_fck",
  1243. .ops = &clkops_omap2_dflt,
  1244. .parent = &omap_32k_fck,
  1245. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
  1246. .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
  1247. .recalc = &followparent_recalc,
  1248. };
  1249. static struct clk usbtll_fck = {
  1250. .name = "usbtll_fck",
  1251. .ops = &clkops_omap2_dflt,
  1252. .parent = &dpll5_m2_ck,
  1253. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
  1254. .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
  1255. .recalc = &followparent_recalc,
  1256. };
  1257. /* CORE 96M FCLK-derived clocks */
  1258. static struct clk core_96m_fck = {
  1259. .name = "core_96m_fck",
  1260. .ops = &clkops_null,
  1261. .parent = &omap_96m_fck,
  1262. .clkdm_name = "core_l4_clkdm",
  1263. .recalc = &followparent_recalc,
  1264. };
  1265. static struct clk mmchs3_fck = {
  1266. .name = "mmchs3_fck",
  1267. .ops = &clkops_omap2_dflt_wait,
  1268. .parent = &core_96m_fck,
  1269. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1270. .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
  1271. .clkdm_name = "core_l4_clkdm",
  1272. .recalc = &followparent_recalc,
  1273. };
  1274. static struct clk mmchs2_fck = {
  1275. .name = "mmchs2_fck",
  1276. .ops = &clkops_omap2_dflt_wait,
  1277. .parent = &core_96m_fck,
  1278. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1279. .enable_bit = OMAP3430_EN_MMC2_SHIFT,
  1280. .clkdm_name = "core_l4_clkdm",
  1281. .recalc = &followparent_recalc,
  1282. };
  1283. static struct clk mspro_fck = {
  1284. .name = "mspro_fck",
  1285. .ops = &clkops_omap2_dflt_wait,
  1286. .parent = &core_96m_fck,
  1287. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1288. .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
  1289. .clkdm_name = "core_l4_clkdm",
  1290. .recalc = &followparent_recalc,
  1291. };
  1292. static struct clk mmchs1_fck = {
  1293. .name = "mmchs1_fck",
  1294. .ops = &clkops_omap2_dflt_wait,
  1295. .parent = &core_96m_fck,
  1296. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1297. .enable_bit = OMAP3430_EN_MMC1_SHIFT,
  1298. .clkdm_name = "core_l4_clkdm",
  1299. .recalc = &followparent_recalc,
  1300. };
  1301. static struct clk i2c3_fck = {
  1302. .name = "i2c3_fck",
  1303. .ops = &clkops_omap2_dflt_wait,
  1304. .parent = &core_96m_fck,
  1305. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1306. .enable_bit = OMAP3430_EN_I2C3_SHIFT,
  1307. .clkdm_name = "core_l4_clkdm",
  1308. .recalc = &followparent_recalc,
  1309. };
  1310. static struct clk i2c2_fck = {
  1311. .name = "i2c2_fck",
  1312. .ops = &clkops_omap2_dflt_wait,
  1313. .parent = &core_96m_fck,
  1314. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1315. .enable_bit = OMAP3430_EN_I2C2_SHIFT,
  1316. .clkdm_name = "core_l4_clkdm",
  1317. .recalc = &followparent_recalc,
  1318. };
  1319. static struct clk i2c1_fck = {
  1320. .name = "i2c1_fck",
  1321. .ops = &clkops_omap2_dflt_wait,
  1322. .parent = &core_96m_fck,
  1323. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1324. .enable_bit = OMAP3430_EN_I2C1_SHIFT,
  1325. .clkdm_name = "core_l4_clkdm",
  1326. .recalc = &followparent_recalc,
  1327. };
  1328. /*
  1329. * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
  1330. * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
  1331. */
  1332. static const struct clksel_rate common_mcbsp_96m_rates[] = {
  1333. { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
  1334. { .div = 0 }
  1335. };
  1336. static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
  1337. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  1338. { .div = 0 }
  1339. };
  1340. static const struct clksel mcbsp_15_clksel[] = {
  1341. { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
  1342. { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
  1343. { .parent = NULL }
  1344. };
  1345. static struct clk mcbsp5_fck = {
  1346. .name = "mcbsp5_fck",
  1347. .ops = &clkops_omap2_dflt_wait,
  1348. .init = &omap2_init_clksel_parent,
  1349. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1350. .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
  1351. .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
  1352. .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
  1353. .clksel = mcbsp_15_clksel,
  1354. .clkdm_name = "core_l4_clkdm",
  1355. .recalc = &omap2_clksel_recalc,
  1356. };
  1357. static struct clk mcbsp1_fck = {
  1358. .name = "mcbsp1_fck",
  1359. .ops = &clkops_omap2_dflt_wait,
  1360. .init = &omap2_init_clksel_parent,
  1361. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1362. .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
  1363. .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
  1364. .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
  1365. .clksel = mcbsp_15_clksel,
  1366. .clkdm_name = "core_l4_clkdm",
  1367. .recalc = &omap2_clksel_recalc,
  1368. };
  1369. /* CORE_48M_FCK-derived clocks */
  1370. static struct clk core_48m_fck = {
  1371. .name = "core_48m_fck",
  1372. .ops = &clkops_null,
  1373. .parent = &omap_48m_fck,
  1374. .clkdm_name = "core_l4_clkdm",
  1375. .recalc = &followparent_recalc,
  1376. };
  1377. static struct clk mcspi4_fck = {
  1378. .name = "mcspi4_fck",
  1379. .ops = &clkops_omap2_dflt_wait,
  1380. .parent = &core_48m_fck,
  1381. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1382. .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
  1383. .recalc = &followparent_recalc,
  1384. };
  1385. static struct clk mcspi3_fck = {
  1386. .name = "mcspi3_fck",
  1387. .ops = &clkops_omap2_dflt_wait,
  1388. .parent = &core_48m_fck,
  1389. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1390. .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
  1391. .recalc = &followparent_recalc,
  1392. };
  1393. static struct clk mcspi2_fck = {
  1394. .name = "mcspi2_fck",
  1395. .ops = &clkops_omap2_dflt_wait,
  1396. .parent = &core_48m_fck,
  1397. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1398. .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
  1399. .recalc = &followparent_recalc,
  1400. };
  1401. static struct clk mcspi1_fck = {
  1402. .name = "mcspi1_fck",
  1403. .ops = &clkops_omap2_dflt_wait,
  1404. .parent = &core_48m_fck,
  1405. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1406. .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
  1407. .recalc = &followparent_recalc,
  1408. };
  1409. static struct clk uart2_fck = {
  1410. .name = "uart2_fck",
  1411. .ops = &clkops_omap2_dflt_wait,
  1412. .parent = &core_48m_fck,
  1413. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1414. .enable_bit = OMAP3430_EN_UART2_SHIFT,
  1415. .clkdm_name = "core_l4_clkdm",
  1416. .recalc = &followparent_recalc,
  1417. };
  1418. static struct clk uart1_fck = {
  1419. .name = "uart1_fck",
  1420. .ops = &clkops_omap2_dflt_wait,
  1421. .parent = &core_48m_fck,
  1422. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1423. .enable_bit = OMAP3430_EN_UART1_SHIFT,
  1424. .clkdm_name = "core_l4_clkdm",
  1425. .recalc = &followparent_recalc,
  1426. };
  1427. static struct clk fshostusb_fck = {
  1428. .name = "fshostusb_fck",
  1429. .ops = &clkops_omap2_dflt_wait,
  1430. .parent = &core_48m_fck,
  1431. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1432. .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
  1433. .recalc = &followparent_recalc,
  1434. };
  1435. /* CORE_12M_FCK based clocks */
  1436. static struct clk core_12m_fck = {
  1437. .name = "core_12m_fck",
  1438. .ops = &clkops_null,
  1439. .parent = &omap_12m_fck,
  1440. .clkdm_name = "core_l4_clkdm",
  1441. .recalc = &followparent_recalc,
  1442. };
  1443. static struct clk hdq_fck = {
  1444. .name = "hdq_fck",
  1445. .ops = &clkops_omap2_dflt_wait,
  1446. .parent = &core_12m_fck,
  1447. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1448. .enable_bit = OMAP3430_EN_HDQ_SHIFT,
  1449. .recalc = &followparent_recalc,
  1450. };
  1451. /* DPLL3-derived clock */
  1452. static const struct clksel_rate ssi_ssr_corex2_rates[] = {
  1453. { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
  1454. { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
  1455. { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
  1456. { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
  1457. { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
  1458. { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
  1459. { .div = 0 }
  1460. };
  1461. static const struct clksel ssi_ssr_clksel[] = {
  1462. { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
  1463. { .parent = NULL }
  1464. };
  1465. static struct clk ssi_ssr_fck_3430es1 = {
  1466. .name = "ssi_ssr_fck",
  1467. .ops = &clkops_omap2_dflt,
  1468. .init = &omap2_init_clksel_parent,
  1469. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1470. .enable_bit = OMAP3430_EN_SSI_SHIFT,
  1471. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1472. .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
  1473. .clksel = ssi_ssr_clksel,
  1474. .clkdm_name = "core_l4_clkdm",
  1475. .recalc = &omap2_clksel_recalc,
  1476. };
  1477. static struct clk ssi_ssr_fck_3430es2 = {
  1478. .name = "ssi_ssr_fck",
  1479. .ops = &clkops_omap3430es2_ssi_wait,
  1480. .init = &omap2_init_clksel_parent,
  1481. .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
  1482. .enable_bit = OMAP3430_EN_SSI_SHIFT,
  1483. .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
  1484. .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
  1485. .clksel = ssi_ss