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/arch/arm/mach-omap2/clock3xxx_data.c

https://bitbucket.org/sammyz/iscream_thunderc-2.6.35-rebase
C | 3513 lines | 2936 code | 379 blank | 198 comment | 15 complexity | f77f709fd25d7bf418ad9eac0ac12617 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0

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   1/*
   2 * OMAP3 clock data
   3 *
   4 * Copyright (C) 2007-2010 Texas Instruments, Inc.
   5 * Copyright (C) 2007-2010 Nokia Corporation
   6 *
   7 * Written by Paul Walmsley
   8 * With many device clock fixes by Kevin Hilman and Jouni Hรถgander
   9 * DPLL bypass clock support added by Roman Tereshonkov
  10 *
  11 */
  12
  13/*
  14 * Virtual clocks are introduced as convenient tools.
  15 * They are sources for other clocks and not supposed
  16 * to be requested from drivers directly.
  17 */
  18
  19#include <linux/kernel.h>
  20#include <linux/clk.h>
  21#include <linux/list.h>
  22
  23#include <plat/control.h>
  24#include <plat/clkdev_omap.h>
  25
  26#include "clock.h"
  27#include "clock3xxx.h"
  28#include "clock34xx.h"
  29#include "clock36xx.h"
  30#include "clock3517.h"
  31
  32#include "cm.h"
  33#include "cm-regbits-34xx.h"
  34#include "prm.h"
  35#include "prm-regbits-34xx.h"
  36
  37/*
  38 * clocks
  39 */
  40
  41#define OMAP_CM_REGADDR		OMAP34XX_CM_REGADDR
  42
  43/* Maximum DPLL multiplier, divider values for OMAP3 */
  44#define OMAP3_MAX_DPLL_MULT		2047
  45#define OMAP3630_MAX_JTYPE_DPLL_MULT	4095
  46#define OMAP3_MAX_DPLL_DIV		128
  47
  48/*
  49 * DPLL1 supplies clock to the MPU.
  50 * DPLL2 supplies clock to the IVA2.
  51 * DPLL3 supplies CORE domain clocks.
  52 * DPLL4 supplies peripheral clocks.
  53 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  54 */
  55
  56/* Forward declarations for DPLL bypass clocks */
  57static struct clk dpll1_fck;
  58static struct clk dpll2_fck;
  59
  60/* PRM CLOCKS */
  61
  62/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  63static struct clk omap_32k_fck = {
  64	.name		= "omap_32k_fck",
  65	.ops		= &clkops_null,
  66	.rate		= 32768,
  67};
  68
  69static struct clk secure_32k_fck = {
  70	.name		= "secure_32k_fck",
  71	.ops		= &clkops_null,
  72	.rate		= 32768,
  73};
  74
  75/* Virtual source clocks for osc_sys_ck */
  76static struct clk virt_12m_ck = {
  77	.name		= "virt_12m_ck",
  78	.ops		= &clkops_null,
  79	.rate		= 12000000,
  80};
  81
  82static struct clk virt_13m_ck = {
  83	.name		= "virt_13m_ck",
  84	.ops		= &clkops_null,
  85	.rate		= 13000000,
  86};
  87
  88static struct clk virt_16_8m_ck = {
  89	.name		= "virt_16_8m_ck",
  90	.ops		= &clkops_null,
  91	.rate		= 16800000,
  92};
  93
  94static struct clk virt_19_2m_ck = {
  95	.name		= "virt_19_2m_ck",
  96	.ops		= &clkops_null,
  97	.rate		= 19200000,
  98};
  99
 100static struct clk virt_26m_ck = {
 101	.name		= "virt_26m_ck",
 102	.ops		= &clkops_null,
 103	.rate		= 26000000,
 104};
 105
 106static struct clk virt_38_4m_ck = {
 107	.name		= "virt_38_4m_ck",
 108	.ops		= &clkops_null,
 109	.rate		= 38400000,
 110};
 111
 112static const struct clksel_rate osc_sys_12m_rates[] = {
 113	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 114	{ .div = 0 }
 115};
 116
 117static const struct clksel_rate osc_sys_13m_rates[] = {
 118	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 119	{ .div = 0 }
 120};
 121
 122static const struct clksel_rate osc_sys_16_8m_rates[] = {
 123	{ .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS },
 124	{ .div = 0 }
 125};
 126
 127static const struct clksel_rate osc_sys_19_2m_rates[] = {
 128	{ .div = 1, .val = 2, .flags = RATE_IN_3XXX },
 129	{ .div = 0 }
 130};
 131
 132static const struct clksel_rate osc_sys_26m_rates[] = {
 133	{ .div = 1, .val = 3, .flags = RATE_IN_3XXX },
 134	{ .div = 0 }
 135};
 136
 137static const struct clksel_rate osc_sys_38_4m_rates[] = {
 138	{ .div = 1, .val = 4, .flags = RATE_IN_3XXX },
 139	{ .div = 0 }
 140};
 141
 142static const struct clksel osc_sys_clksel[] = {
 143	{ .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 144	{ .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 145	{ .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 146	{ .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 147	{ .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 148	{ .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 149	{ .parent = NULL },
 150};
 151
 152/* Oscillator clock */
 153/* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 154static struct clk osc_sys_ck = {
 155	.name		= "osc_sys_ck",
 156	.ops		= &clkops_null,
 157	.init		= &omap2_init_clksel_parent,
 158	.clksel_reg	= OMAP3430_PRM_CLKSEL,
 159	.clksel_mask	= OMAP3430_SYS_CLKIN_SEL_MASK,
 160	.clksel		= osc_sys_clksel,
 161	/* REVISIT: deal with autoextclkmode? */
 162	.recalc		= &omap2_clksel_recalc,
 163};
 164
 165static const struct clksel_rate div2_rates[] = {
 166	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 167	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 168	{ .div = 0 }
 169};
 170
 171static const struct clksel sys_clksel[] = {
 172	{ .parent = &osc_sys_ck, .rates = div2_rates },
 173	{ .parent = NULL }
 174};
 175
 176/* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 177/* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 178static struct clk sys_ck = {
 179	.name		= "sys_ck",
 180	.ops		= &clkops_null,
 181	.parent		= &osc_sys_ck,
 182	.init		= &omap2_init_clksel_parent,
 183	.clksel_reg	= OMAP3430_PRM_CLKSRC_CTRL,
 184	.clksel_mask	= OMAP_SYSCLKDIV_MASK,
 185	.clksel		= sys_clksel,
 186	.recalc		= &omap2_clksel_recalc,
 187};
 188
 189static struct clk sys_altclk = {
 190	.name		= "sys_altclk",
 191	.ops		= &clkops_null,
 192};
 193
 194/* Optional external clock input for some McBSPs */
 195static struct clk mcbsp_clks = {
 196	.name		= "mcbsp_clks",
 197	.ops		= &clkops_null,
 198};
 199
 200/* PRM EXTERNAL CLOCK OUTPUT */
 201
 202static struct clk sys_clkout1 = {
 203	.name		= "sys_clkout1",
 204	.ops		= &clkops_omap2_dflt,
 205	.parent		= &osc_sys_ck,
 206	.enable_reg	= OMAP3430_PRM_CLKOUT_CTRL,
 207	.enable_bit	= OMAP3430_CLKOUT_EN_SHIFT,
 208	.recalc		= &followparent_recalc,
 209};
 210
 211/* DPLLS */
 212
 213/* CM CLOCKS */
 214
 215static const struct clksel_rate div16_dpll_rates[] = {
 216	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 217	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 218	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 219	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 220	{ .div = 5, .val = 5, .flags = RATE_IN_3XXX },
 221	{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
 222	{ .div = 7, .val = 7, .flags = RATE_IN_3XXX },
 223	{ .div = 8, .val = 8, .flags = RATE_IN_3XXX },
 224	{ .div = 9, .val = 9, .flags = RATE_IN_3XXX },
 225	{ .div = 10, .val = 10, .flags = RATE_IN_3XXX },
 226	{ .div = 11, .val = 11, .flags = RATE_IN_3XXX },
 227	{ .div = 12, .val = 12, .flags = RATE_IN_3XXX },
 228	{ .div = 13, .val = 13, .flags = RATE_IN_3XXX },
 229	{ .div = 14, .val = 14, .flags = RATE_IN_3XXX },
 230	{ .div = 15, .val = 15, .flags = RATE_IN_3XXX },
 231	{ .div = 16, .val = 16, .flags = RATE_IN_3XXX },
 232	{ .div = 0 }
 233};
 234
 235static const struct clksel_rate dpll4_rates[] = {
 236	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 237	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 238	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 239	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 240	{ .div = 5, .val = 5, .flags = RATE_IN_3XXX },
 241	{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
 242	{ .div = 7, .val = 7, .flags = RATE_IN_3XXX },
 243	{ .div = 8, .val = 8, .flags = RATE_IN_3XXX },
 244	{ .div = 9, .val = 9, .flags = RATE_IN_3XXX },
 245	{ .div = 10, .val = 10, .flags = RATE_IN_3XXX },
 246	{ .div = 11, .val = 11, .flags = RATE_IN_3XXX },
 247	{ .div = 12, .val = 12, .flags = RATE_IN_3XXX },
 248	{ .div = 13, .val = 13, .flags = RATE_IN_3XXX },
 249	{ .div = 14, .val = 14, .flags = RATE_IN_3XXX },
 250	{ .div = 15, .val = 15, .flags = RATE_IN_3XXX },
 251	{ .div = 16, .val = 16, .flags = RATE_IN_3XXX },
 252	{ .div = 17, .val = 17, .flags = RATE_IN_36XX },
 253	{ .div = 18, .val = 18, .flags = RATE_IN_36XX },
 254	{ .div = 19, .val = 19, .flags = RATE_IN_36XX },
 255	{ .div = 20, .val = 20, .flags = RATE_IN_36XX },
 256	{ .div = 21, .val = 21, .flags = RATE_IN_36XX },
 257	{ .div = 22, .val = 22, .flags = RATE_IN_36XX },
 258	{ .div = 23, .val = 23, .flags = RATE_IN_36XX },
 259	{ .div = 24, .val = 24, .flags = RATE_IN_36XX },
 260	{ .div = 25, .val = 25, .flags = RATE_IN_36XX },
 261	{ .div = 26, .val = 26, .flags = RATE_IN_36XX },
 262	{ .div = 27, .val = 27, .flags = RATE_IN_36XX },
 263	{ .div = 28, .val = 28, .flags = RATE_IN_36XX },
 264	{ .div = 29, .val = 29, .flags = RATE_IN_36XX },
 265	{ .div = 30, .val = 30, .flags = RATE_IN_36XX },
 266	{ .div = 31, .val = 31, .flags = RATE_IN_36XX },
 267	{ .div = 32, .val = 32, .flags = RATE_IN_36XX },
 268	{ .div = 0 }
 269};
 270
 271/* DPLL1 */
 272/* MPU clock source */
 273/* Type: DPLL */
 274static struct dpll_data dpll1_dd = {
 275	.mult_div1_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 276	.mult_mask	= OMAP3430_MPU_DPLL_MULT_MASK,
 277	.div1_mask	= OMAP3430_MPU_DPLL_DIV_MASK,
 278	.clk_bypass	= &dpll1_fck,
 279	.clk_ref	= &sys_ck,
 280	.freqsel_mask	= OMAP3430_MPU_DPLL_FREQSEL_MASK,
 281	.control_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 282	.enable_mask	= OMAP3430_EN_MPU_DPLL_MASK,
 283	.modes		= (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 284	.auto_recal_bit	= OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 285	.recal_en_bit	= OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 286	.recal_st_bit	= OMAP3430_MPU_DPLL_ST_SHIFT,
 287	.autoidle_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 288	.autoidle_mask	= OMAP3430_AUTO_MPU_DPLL_MASK,
 289	.idlest_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 290	.idlest_mask	= OMAP3430_ST_MPU_CLK_MASK,
 291	.max_multiplier = OMAP3_MAX_DPLL_MULT,
 292	.min_divider	= 1,
 293	.max_divider	= OMAP3_MAX_DPLL_DIV,
 294	.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 295};
 296
 297static struct clk dpll1_ck = {
 298	.name		= "dpll1_ck",
 299	.ops		= &clkops_null,
 300	.parent		= &sys_ck,
 301	.dpll_data	= &dpll1_dd,
 302	.round_rate	= &omap2_dpll_round_rate,
 303	.set_rate	= &omap3_noncore_dpll_set_rate,
 304	.clkdm_name	= "dpll1_clkdm",
 305	.recalc		= &omap3_dpll_recalc,
 306};
 307
 308/*
 309 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 310 * DPLL isn't bypassed.
 311 */
 312static struct clk dpll1_x2_ck = {
 313	.name		= "dpll1_x2_ck",
 314	.ops		= &clkops_null,
 315	.parent		= &dpll1_ck,
 316	.clkdm_name	= "dpll1_clkdm",
 317	.recalc		= &omap3_clkoutx2_recalc,
 318};
 319
 320/* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 321static const struct clksel div16_dpll1_x2m2_clksel[] = {
 322	{ .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 323	{ .parent = NULL }
 324};
 325
 326/*
 327 * Does not exist in the TRM - needed to separate the M2 divider from
 328 * bypass selection in mpu_ck
 329 */
 330static struct clk dpll1_x2m2_ck = {
 331	.name		= "dpll1_x2m2_ck",
 332	.ops		= &clkops_null,
 333	.parent		= &dpll1_x2_ck,
 334	.init		= &omap2_init_clksel_parent,
 335	.clksel_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 336	.clksel_mask	= OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 337	.clksel		= div16_dpll1_x2m2_clksel,
 338	.clkdm_name	= "dpll1_clkdm",
 339	.recalc		= &omap2_clksel_recalc,
 340};
 341
 342/* DPLL2 */
 343/* IVA2 clock source */
 344/* Type: DPLL */
 345
 346static struct dpll_data dpll2_dd = {
 347	.mult_div1_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 348	.mult_mask	= OMAP3430_IVA2_DPLL_MULT_MASK,
 349	.div1_mask	= OMAP3430_IVA2_DPLL_DIV_MASK,
 350	.clk_bypass	= &dpll2_fck,
 351	.clk_ref	= &sys_ck,
 352	.freqsel_mask	= OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 353	.control_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 354	.enable_mask	= OMAP3430_EN_IVA2_DPLL_MASK,
 355	.modes		= (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 356				(1 << DPLL_LOW_POWER_BYPASS),
 357	.auto_recal_bit	= OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 358	.recal_en_bit	= OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 359	.recal_st_bit	= OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 360	.autoidle_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 361	.autoidle_mask	= OMAP3430_AUTO_IVA2_DPLL_MASK,
 362	.idlest_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 363	.idlest_mask	= OMAP3430_ST_IVA2_CLK_MASK,
 364	.max_multiplier = OMAP3_MAX_DPLL_MULT,
 365	.min_divider	= 1,
 366	.max_divider	= OMAP3_MAX_DPLL_DIV,
 367	.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 368};
 369
 370static struct clk dpll2_ck = {
 371	.name		= "dpll2_ck",
 372	.ops		= &clkops_omap3_noncore_dpll_ops,
 373	.parent		= &sys_ck,
 374	.dpll_data	= &dpll2_dd,
 375	.round_rate	= &omap2_dpll_round_rate,
 376	.set_rate	= &omap3_noncore_dpll_set_rate,
 377	.clkdm_name	= "dpll2_clkdm",
 378	.recalc		= &omap3_dpll_recalc,
 379};
 380
 381static const struct clksel div16_dpll2_m2x2_clksel[] = {
 382	{ .parent = &dpll2_ck, .rates = div16_dpll_rates },
 383	{ .parent = NULL }
 384};
 385
 386/*
 387 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 388 * or CLKOUTX2. CLKOUT seems most plausible.
 389 */
 390static struct clk dpll2_m2_ck = {
 391	.name		= "dpll2_m2_ck",
 392	.ops		= &clkops_null,
 393	.parent		= &dpll2_ck,
 394	.init		= &omap2_init_clksel_parent,
 395	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 396					  OMAP3430_CM_CLKSEL2_PLL),
 397	.clksel_mask	= OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 398	.clksel		= div16_dpll2_m2x2_clksel,
 399	.clkdm_name	= "dpll2_clkdm",
 400	.recalc		= &omap2_clksel_recalc,
 401};
 402
 403/*
 404 * DPLL3
 405 * Source clock for all interfaces and for some device fclks
 406 * REVISIT: Also supports fast relock bypass - not included below
 407 */
 408static struct dpll_data dpll3_dd = {
 409	.mult_div1_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 410	.mult_mask	= OMAP3430_CORE_DPLL_MULT_MASK,
 411	.div1_mask	= OMAP3430_CORE_DPLL_DIV_MASK,
 412	.clk_bypass	= &sys_ck,
 413	.clk_ref	= &sys_ck,
 414	.freqsel_mask	= OMAP3430_CORE_DPLL_FREQSEL_MASK,
 415	.control_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 416	.enable_mask	= OMAP3430_EN_CORE_DPLL_MASK,
 417	.auto_recal_bit	= OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 418	.recal_en_bit	= OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 419	.recal_st_bit	= OMAP3430_CORE_DPLL_ST_SHIFT,
 420	.autoidle_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 421	.autoidle_mask	= OMAP3430_AUTO_CORE_DPLL_MASK,
 422	.idlest_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 423	.idlest_mask	= OMAP3430_ST_CORE_CLK_MASK,
 424	.max_multiplier = OMAP3_MAX_DPLL_MULT,
 425	.min_divider	= 1,
 426	.max_divider	= OMAP3_MAX_DPLL_DIV,
 427	.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 428};
 429
 430static struct clk dpll3_ck = {
 431	.name		= "dpll3_ck",
 432	.ops		= &clkops_null,
 433	.parent		= &sys_ck,
 434	.dpll_data	= &dpll3_dd,
 435	.round_rate	= &omap2_dpll_round_rate,
 436	.clkdm_name	= "dpll3_clkdm",
 437	.recalc		= &omap3_dpll_recalc,
 438};
 439
 440/*
 441 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 442 * DPLL isn't bypassed
 443 */
 444static struct clk dpll3_x2_ck = {
 445	.name		= "dpll3_x2_ck",
 446	.ops		= &clkops_null,
 447	.parent		= &dpll3_ck,
 448	.clkdm_name	= "dpll3_clkdm",
 449	.recalc		= &omap3_clkoutx2_recalc,
 450};
 451
 452static const struct clksel_rate div31_dpll3_rates[] = {
 453	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 454	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 455	{ .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS },
 456	{ .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS },
 457	{ .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS },
 458	{ .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS },
 459	{ .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS },
 460	{ .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS },
 461	{ .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS },
 462	{ .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS },
 463	{ .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS },
 464	{ .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS },
 465	{ .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS },
 466	{ .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS },
 467	{ .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS },
 468	{ .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS },
 469	{ .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS },
 470	{ .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS },
 471	{ .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS },
 472	{ .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS },
 473	{ .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS },
 474	{ .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS },
 475	{ .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS },
 476	{ .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS },
 477	{ .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS },
 478	{ .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS },
 479	{ .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS },
 480	{ .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS },
 481	{ .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS },
 482	{ .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS },
 483	{ .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS },
 484	{ .div = 0 },
 485};
 486
 487static const struct clksel div31_dpll3m2_clksel[] = {
 488	{ .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 489	{ .parent = NULL }
 490};
 491
 492/* DPLL3 output M2 - primary control point for CORE speed */
 493static struct clk dpll3_m2_ck = {
 494	.name		= "dpll3_m2_ck",
 495	.ops		= &clkops_null,
 496	.parent		= &dpll3_ck,
 497	.init		= &omap2_init_clksel_parent,
 498	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 499	.clksel_mask	= OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 500	.clksel		= div31_dpll3m2_clksel,
 501	.clkdm_name	= "dpll3_clkdm",
 502	.round_rate	= &omap2_clksel_round_rate,
 503	.set_rate	= &omap3_core_dpll_m2_set_rate,
 504	.recalc		= &omap2_clksel_recalc,
 505};
 506
 507static struct clk core_ck = {
 508	.name		= "core_ck",
 509	.ops		= &clkops_null,
 510	.parent		= &dpll3_m2_ck,
 511	.recalc		= &followparent_recalc,
 512};
 513
 514static struct clk dpll3_m2x2_ck = {
 515	.name		= "dpll3_m2x2_ck",
 516	.ops		= &clkops_null,
 517	.parent		= &dpll3_m2_ck,
 518	.clkdm_name	= "dpll3_clkdm",
 519	.recalc		= &omap3_clkoutx2_recalc,
 520};
 521
 522/* The PWRDN bit is apparently only available on 3430ES2 and above */
 523static const struct clksel div16_dpll3_clksel[] = {
 524	{ .parent = &dpll3_ck, .rates = div16_dpll_rates },
 525	{ .parent = NULL }
 526};
 527
 528/* This virtual clock is the source for dpll3_m3x2_ck */
 529static struct clk dpll3_m3_ck = {
 530	.name		= "dpll3_m3_ck",
 531	.ops		= &clkops_null,
 532	.parent		= &dpll3_ck,
 533	.init		= &omap2_init_clksel_parent,
 534	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 535	.clksel_mask	= OMAP3430_DIV_DPLL3_MASK,
 536	.clksel		= div16_dpll3_clksel,
 537	.clkdm_name	= "dpll3_clkdm",
 538	.recalc		= &omap2_clksel_recalc,
 539};
 540
 541/* The PWRDN bit is apparently only available on 3430ES2 and above */
 542static struct clk dpll3_m3x2_ck = {
 543	.name		= "dpll3_m3x2_ck",
 544	.ops		= &clkops_omap2_dflt_wait,
 545	.parent		= &dpll3_m3_ck,
 546	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 547	.enable_bit	= OMAP3430_PWRDN_EMU_CORE_SHIFT,
 548	.flags		= INVERT_ENABLE,
 549	.clkdm_name	= "dpll3_clkdm",
 550	.recalc		= &omap3_clkoutx2_recalc,
 551};
 552
 553static struct clk emu_core_alwon_ck = {
 554	.name		= "emu_core_alwon_ck",
 555	.ops		= &clkops_null,
 556	.parent		= &dpll3_m3x2_ck,
 557	.clkdm_name	= "dpll3_clkdm",
 558	.recalc		= &followparent_recalc,
 559};
 560
 561/* DPLL4 */
 562/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 563/* Type: DPLL */
 564static struct dpll_data dpll4_dd;
 565
 566static struct dpll_data dpll4_dd_34xx __initdata = {
 567	.mult_div1_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 568	.mult_mask	= OMAP3430_PERIPH_DPLL_MULT_MASK,
 569	.div1_mask	= OMAP3430_PERIPH_DPLL_DIV_MASK,
 570	.clk_bypass	= &sys_ck,
 571	.clk_ref	= &sys_ck,
 572	.freqsel_mask	= OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 573	.control_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 574	.enable_mask	= OMAP3430_EN_PERIPH_DPLL_MASK,
 575	.modes		= (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 576	.auto_recal_bit	= OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 577	.recal_en_bit	= OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 578	.recal_st_bit	= OMAP3430_PERIPH_DPLL_ST_SHIFT,
 579	.autoidle_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 580	.autoidle_mask	= OMAP3430_AUTO_PERIPH_DPLL_MASK,
 581	.idlest_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 582	.idlest_mask	= OMAP3430_ST_PERIPH_CLK_MASK,
 583	.max_multiplier = OMAP3_MAX_DPLL_MULT,
 584	.min_divider	= 1,
 585	.max_divider	= OMAP3_MAX_DPLL_DIV,
 586	.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 587};
 588
 589static struct dpll_data dpll4_dd_3630 __initdata = {
 590	.mult_div1_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 591	.mult_mask	= OMAP3630_PERIPH_DPLL_MULT_MASK,
 592	.div1_mask	= OMAP3430_PERIPH_DPLL_DIV_MASK,
 593	.clk_bypass	= &sys_ck,
 594	.clk_ref	= &sys_ck,
 595	.control_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 596	.enable_mask	= OMAP3430_EN_PERIPH_DPLL_MASK,
 597	.modes		= (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 598	.auto_recal_bit	= OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 599	.recal_en_bit	= OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 600	.recal_st_bit	= OMAP3430_PERIPH_DPLL_ST_SHIFT,
 601	.autoidle_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 602	.autoidle_mask	= OMAP3430_AUTO_PERIPH_DPLL_MASK,
 603	.idlest_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 604	.idlest_mask	= OMAP3430_ST_PERIPH_CLK_MASK,
 605	.max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
 606	.min_divider	= 1,
 607	.max_divider	= OMAP3_MAX_DPLL_DIV,
 608	.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
 609	.flags		= DPLL_J_TYPE
 610};
 611
 612static struct clk dpll4_ck = {
 613	.name		= "dpll4_ck",
 614	.ops		= &clkops_omap3_noncore_dpll_ops,
 615	.parent		= &sys_ck,
 616	.dpll_data	= &dpll4_dd,
 617	.round_rate	= &omap2_dpll_round_rate,
 618	.set_rate	= &omap3_dpll4_set_rate,
 619	.clkdm_name	= "dpll4_clkdm",
 620	.recalc		= &omap3_dpll_recalc,
 621};
 622
 623/*
 624 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 625 * DPLL isn't bypassed --
 626 * XXX does this serve any downstream clocks?
 627 */
 628static struct clk dpll4_x2_ck = {
 629	.name		= "dpll4_x2_ck",
 630	.ops		= &clkops_null,
 631	.parent		= &dpll4_ck,
 632	.clkdm_name	= "dpll4_clkdm",
 633	.recalc		= &omap3_clkoutx2_recalc,
 634};
 635
 636static const struct clksel dpll4_clksel[] = {
 637	{ .parent = &dpll4_ck, .rates = dpll4_rates },
 638	{ .parent = NULL }
 639};
 640
 641/* This virtual clock is the source for dpll4_m2x2_ck */
 642static struct clk dpll4_m2_ck = {
 643	.name		= "dpll4_m2_ck",
 644	.ops		= &clkops_null,
 645	.parent		= &dpll4_ck,
 646	.init		= &omap2_init_clksel_parent,
 647	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 648	.clksel_mask	= OMAP3630_DIV_96M_MASK,
 649	.clksel		= dpll4_clksel,
 650	.clkdm_name	= "dpll4_clkdm",
 651	.recalc		= &omap2_clksel_recalc,
 652};
 653
 654/* The PWRDN bit is apparently only available on 3430ES2 and above */
 655static struct clk dpll4_m2x2_ck = {
 656	.name		= "dpll4_m2x2_ck",
 657	.ops		= &clkops_omap2_dflt_wait,
 658	.parent		= &dpll4_m2_ck,
 659	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 660	.enable_bit	= OMAP3430_PWRDN_96M_SHIFT,
 661	.flags		= INVERT_ENABLE,
 662	.clkdm_name	= "dpll4_clkdm",
 663	.recalc		= &omap3_clkoutx2_recalc,
 664};
 665
 666/*
 667 * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 668 * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 669 * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 670 * CM_96K_(F)CLK.
 671 */
 672
 673/* Adding 192MHz Clock node needed by SGX */
 674static struct clk omap_192m_alwon_fck = {
 675	.name		= "omap_192m_alwon_fck",
 676	.ops		= &clkops_null,
 677	.parent		= &dpll4_m2x2_ck,
 678	.recalc		= &followparent_recalc,
 679};
 680
 681static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
 682	{ .div = 1, .val = 1, .flags = RATE_IN_36XX },
 683	{ .div = 2, .val = 2, .flags = RATE_IN_36XX },
 684	{ .div = 0 }
 685};
 686
 687static const struct clksel omap_96m_alwon_fck_clksel[] = {
 688	{ .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
 689	{ .parent = NULL }
 690};
 691
 692static const struct clksel_rate omap_96m_dpll_rates[] = {
 693	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 694	{ .div = 0 }
 695};
 696
 697static const struct clksel_rate omap_96m_sys_rates[] = {
 698	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 699	{ .div = 0 }
 700};
 701
 702static struct clk omap_96m_alwon_fck = {
 703	.name		= "omap_96m_alwon_fck",
 704	.ops		= &clkops_null,
 705	.parent		= &dpll4_m2x2_ck,
 706	.recalc		= &followparent_recalc,
 707};
 708
 709static struct clk omap_96m_alwon_fck_3630 = {
 710	.name		= "omap_96m_alwon_fck",
 711	.parent		= &omap_192m_alwon_fck,
 712	.init		= &omap2_init_clksel_parent,
 713	.ops		= &clkops_null,
 714	.recalc		= &omap2_clksel_recalc,
 715	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 716	.clksel_mask	= OMAP3630_CLKSEL_96M_MASK,
 717	.clksel		= omap_96m_alwon_fck_clksel
 718};
 719
 720static struct clk cm_96m_fck = {
 721	.name		= "cm_96m_fck",
 722	.ops		= &clkops_null,
 723	.parent		= &omap_96m_alwon_fck,
 724	.recalc		= &followparent_recalc,
 725};
 726
 727static const struct clksel omap_96m_fck_clksel[] = {
 728	{ .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 729	{ .parent = &sys_ck,	 .rates = omap_96m_sys_rates },
 730	{ .parent = NULL }
 731};
 732
 733static struct clk omap_96m_fck = {
 734	.name		= "omap_96m_fck",
 735	.ops		= &clkops_null,
 736	.parent		= &sys_ck,
 737	.init		= &omap2_init_clksel_parent,
 738	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 739	.clksel_mask	= OMAP3430_SOURCE_96M_MASK,
 740	.clksel		= omap_96m_fck_clksel,
 741	.recalc		= &omap2_clksel_recalc,
 742};
 743
 744/* This virtual clock is the source for dpll4_m3x2_ck */
 745static struct clk dpll4_m3_ck = {
 746	.name		= "dpll4_m3_ck",
 747	.ops		= &clkops_null,
 748	.parent		= &dpll4_ck,
 749	.init		= &omap2_init_clksel_parent,
 750	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 751	.clksel_mask	= OMAP3430_CLKSEL_TV_MASK,
 752	.clksel		= dpll4_clksel,
 753	.clkdm_name	= "dpll4_clkdm",
 754	.recalc		= &omap2_clksel_recalc,
 755};
 756
 757/* The PWRDN bit is apparently only available on 3430ES2 and above */
 758static struct clk dpll4_m3x2_ck = {
 759	.name		= "dpll4_m3x2_ck",
 760	.ops		= &clkops_omap2_dflt_wait,
 761	.parent		= &dpll4_m3_ck,
 762	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 763	.enable_bit	= OMAP3430_PWRDN_TV_SHIFT,
 764	.flags		= INVERT_ENABLE,
 765	.clkdm_name	= "dpll4_clkdm",
 766	.recalc		= &omap3_clkoutx2_recalc,
 767};
 768
 769static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 770	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 771	{ .div = 0 }
 772};
 773
 774static const struct clksel_rate omap_54m_alt_rates[] = {
 775	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 776	{ .div = 0 }
 777};
 778
 779static const struct clksel omap_54m_clksel[] = {
 780	{ .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 781	{ .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 782	{ .parent = NULL }
 783};
 784
 785static struct clk omap_54m_fck = {
 786	.name		= "omap_54m_fck",
 787	.ops		= &clkops_null,
 788	.init		= &omap2_init_clksel_parent,
 789	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 790	.clksel_mask	= OMAP3430_SOURCE_54M_MASK,
 791	.clksel		= omap_54m_clksel,
 792	.recalc		= &omap2_clksel_recalc,
 793};
 794
 795static const struct clksel_rate omap_48m_cm96m_rates[] = {
 796	{ .div = 2, .val = 0, .flags = RATE_IN_3XXX },
 797	{ .div = 0 }
 798};
 799
 800static const struct clksel_rate omap_48m_alt_rates[] = {
 801	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 802	{ .div = 0 }
 803};
 804
 805static const struct clksel omap_48m_clksel[] = {
 806	{ .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 807	{ .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 808	{ .parent = NULL }
 809};
 810
 811static struct clk omap_48m_fck = {
 812	.name		= "omap_48m_fck",
 813	.ops		= &clkops_null,
 814	.init		= &omap2_init_clksel_parent,
 815	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 816	.clksel_mask	= OMAP3430_SOURCE_48M_MASK,
 817	.clksel		= omap_48m_clksel,
 818	.recalc		= &omap2_clksel_recalc,
 819};
 820
 821static struct clk omap_12m_fck = {
 822	.name		= "omap_12m_fck",
 823	.ops		= &clkops_null,
 824	.parent		= &omap_48m_fck,
 825	.fixed_div	= 4,
 826	.recalc		= &omap_fixed_divisor_recalc,
 827};
 828
 829/* This virtual clock is the source for dpll4_m4x2_ck */
 830static struct clk dpll4_m4_ck = {
 831	.name		= "dpll4_m4_ck",
 832	.ops		= &clkops_null,
 833	.parent		= &dpll4_ck,
 834	.init		= &omap2_init_clksel_parent,
 835	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 836	.clksel_mask	= OMAP3430_CLKSEL_DSS1_MASK,
 837	.clksel		= dpll4_clksel,
 838	.clkdm_name	= "dpll4_clkdm",
 839	.recalc		= &omap2_clksel_recalc,
 840	.set_rate	= &omap2_clksel_set_rate,
 841	.round_rate	= &omap2_clksel_round_rate,
 842};
 843
 844/* The PWRDN bit is apparently only available on 3430ES2 and above */
 845static struct clk dpll4_m4x2_ck = {
 846	.name		= "dpll4_m4x2_ck",
 847	.ops		= &clkops_omap2_dflt_wait,
 848	.parent		= &dpll4_m4_ck,
 849	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 850	.enable_bit	= OMAP3430_PWRDN_DSS1_SHIFT,
 851	.flags		= INVERT_ENABLE,
 852	.clkdm_name	= "dpll4_clkdm",
 853	.recalc		= &omap3_clkoutx2_recalc,
 854};
 855
 856/* This virtual clock is the source for dpll4_m5x2_ck */
 857static struct clk dpll4_m5_ck = {
 858	.name		= "dpll4_m5_ck",
 859	.ops		= &clkops_null,
 860	.parent		= &dpll4_ck,
 861	.init		= &omap2_init_clksel_parent,
 862	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 863	.clksel_mask	= OMAP3430_CLKSEL_CAM_MASK,
 864	.clksel		= dpll4_clksel,
 865	.clkdm_name	= "dpll4_clkdm",
 866	.set_rate	= &omap2_clksel_set_rate,
 867	.round_rate	= &omap2_clksel_round_rate,
 868	.recalc		= &omap2_clksel_recalc,
 869};
 870
 871/* The PWRDN bit is apparently only available on 3430ES2 and above */
 872static struct clk dpll4_m5x2_ck = {
 873	.name		= "dpll4_m5x2_ck",
 874	.ops		= &clkops_omap2_dflt_wait,
 875	.parent		= &dpll4_m5_ck,
 876	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 877	.enable_bit	= OMAP3430_PWRDN_CAM_SHIFT,
 878	.flags		= INVERT_ENABLE,
 879	.clkdm_name	= "dpll4_clkdm",
 880	.recalc		= &omap3_clkoutx2_recalc,
 881};
 882
 883/* This virtual clock is the source for dpll4_m6x2_ck */
 884static struct clk dpll4_m6_ck = {
 885	.name		= "dpll4_m6_ck",
 886	.ops		= &clkops_null,
 887	.parent		= &dpll4_ck,
 888	.init		= &omap2_init_clksel_parent,
 889	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 890	.clksel_mask	= OMAP3430_DIV_DPLL4_MASK,
 891	.clksel		= dpll4_clksel,
 892	.clkdm_name	= "dpll4_clkdm",
 893	.recalc		= &omap2_clksel_recalc,
 894};
 895
 896/* The PWRDN bit is apparently only available on 3430ES2 and above */
 897static struct clk dpll4_m6x2_ck = {
 898	.name		= "dpll4_m6x2_ck",
 899	.ops		= &clkops_omap2_dflt_wait,
 900	.parent		= &dpll4_m6_ck,
 901	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 902	.enable_bit	= OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 903	.flags		= INVERT_ENABLE,
 904	.clkdm_name	= "dpll4_clkdm",
 905	.recalc		= &omap3_clkoutx2_recalc,
 906};
 907
 908static struct clk emu_per_alwon_ck = {
 909	.name		= "emu_per_alwon_ck",
 910	.ops		= &clkops_null,
 911	.parent		= &dpll4_m6x2_ck,
 912	.clkdm_name	= "dpll4_clkdm",
 913	.recalc		= &followparent_recalc,
 914};
 915
 916/* DPLL5 */
 917/* Supplies 120MHz clock, USIM source clock */
 918/* Type: DPLL */
 919/* 3430ES2 only */
 920static struct dpll_data dpll5_dd = {
 921	.mult_div1_reg	= OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 922	.mult_mask	= OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 923	.div1_mask	= OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 924	.clk_bypass	= &sys_ck,
 925	.clk_ref	= &sys_ck,
 926	.freqsel_mask	= OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 927	.control_reg	= OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 928	.enable_mask	= OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 929	.modes		= (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 930	.auto_recal_bit	= OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 931	.recal_en_bit	= OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 932	.recal_st_bit	= OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 933	.autoidle_reg	= OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 934	.autoidle_mask	= OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 935	.idlest_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 936	.idlest_mask	= OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 937	.max_multiplier = OMAP3_MAX_DPLL_MULT,
 938	.min_divider	= 1,
 939	.max_divider	= OMAP3_MAX_DPLL_DIV,
 940	.rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 941};
 942
 943static struct clk dpll5_ck = {
 944	.name		= "dpll5_ck",
 945	.ops		= &clkops_omap3_noncore_dpll_ops,
 946	.parent		= &sys_ck,
 947	.dpll_data	= &dpll5_dd,
 948	.round_rate	= &omap2_dpll_round_rate,
 949	.set_rate	= &omap3_noncore_dpll_set_rate,
 950	.clkdm_name	= "dpll5_clkdm",
 951	.recalc		= &omap3_dpll_recalc,
 952};
 953
 954static const struct clksel div16_dpll5_clksel[] = {
 955	{ .parent = &dpll5_ck, .rates = div16_dpll_rates },
 956	{ .parent = NULL }
 957};
 958
 959static struct clk dpll5_m2_ck = {
 960	.name		= "dpll5_m2_ck",
 961	.ops		= &clkops_null,
 962	.parent		= &dpll5_ck,
 963	.init		= &omap2_init_clksel_parent,
 964	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 965	.clksel_mask	= OMAP3430ES2_DIV_120M_MASK,
 966	.clksel		= div16_dpll5_clksel,
 967	.clkdm_name	= "dpll5_clkdm",
 968	.recalc		= &omap2_clksel_recalc,
 969};
 970
 971/* CM EXTERNAL CLOCK OUTPUTS */
 972
 973static const struct clksel_rate clkout2_src_core_rates[] = {
 974	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 975	{ .div = 0 }
 976};
 977
 978static const struct clksel_rate clkout2_src_sys_rates[] = {
 979	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 980	{ .div = 0 }
 981};
 982
 983static const struct clksel_rate clkout2_src_96m_rates[] = {
 984	{ .div = 1, .val = 2, .flags = RATE_IN_3XXX },
 985	{ .div = 0 }
 986};
 987
 988static const struct clksel_rate clkout2_src_54m_rates[] = {
 989	{ .div = 1, .val = 3, .flags = RATE_IN_3XXX },
 990	{ .div = 0 }
 991};
 992
 993static const struct clksel clkout2_src_clksel[] = {
 994	{ .parent = &core_ck,		.rates = clkout2_src_core_rates },
 995	{ .parent = &sys_ck,		.rates = clkout2_src_sys_rates },
 996	{ .parent = &cm_96m_fck,	.rates = clkout2_src_96m_rates },
 997	{ .parent = &omap_54m_fck,	.rates = clkout2_src_54m_rates },
 998	{ .parent = NULL }
 999};
1000
1001static struct clk clkout2_src_ck = {
1002	.name		= "clkout2_src_ck",
1003	.ops		= &clkops_omap2_dflt,
1004	.init		= &omap2_init_clksel_parent,
1005	.enable_reg	= OMAP3430_CM_CLKOUT_CTRL,
1006	.enable_bit	= OMAP3430_CLKOUT2_EN_SHIFT,
1007	.clksel_reg	= OMAP3430_CM_CLKOUT_CTRL,
1008	.clksel_mask	= OMAP3430_CLKOUT2SOURCE_MASK,
1009	.clksel		= clkout2_src_clksel,
1010	.clkdm_name	= "core_clkdm",
1011	.recalc		= &omap2_clksel_recalc,
1012};
1013
1014static const struct clksel_rate sys_clkout2_rates[] = {
1015	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1016	{ .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1017	{ .div = 4, .val = 2, .flags = RATE_IN_3XXX },
1018	{ .div = 8, .val = 3, .flags = RATE_IN_3XXX },
1019	{ .div = 16, .val = 4, .flags = RATE_IN_3XXX },
1020	{ .div = 0 },
1021};
1022
1023static const struct clksel sys_clkout2_clksel[] = {
1024	{ .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1025	{ .parent = NULL },
1026};
1027
1028static struct clk sys_clkout2 = {
1029	.name		= "sys_clkout2",
1030	.ops		= &clkops_null,
1031	.init		= &omap2_init_clksel_parent,
1032	.clksel_reg	= OMAP3430_CM_CLKOUT_CTRL,
1033	.clksel_mask	= OMAP3430_CLKOUT2_DIV_MASK,
1034	.clksel		= sys_clkout2_clksel,
1035	.recalc		= &omap2_clksel_recalc,
1036	.round_rate	= &omap2_clksel_round_rate,
1037	.set_rate	= &omap2_clksel_set_rate
1038};
1039
1040/* CM OUTPUT CLOCKS */
1041
1042static struct clk corex2_fck = {
1043	.name		= "corex2_fck",
1044	.ops		= &clkops_null,
1045	.parent		= &dpll3_m2x2_ck,
1046	.recalc		= &followparent_recalc,
1047};
1048
1049/* DPLL power domain clock controls */
1050
1051static const struct clksel_rate div4_rates[] = {
1052	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1053	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1054	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1055	{ .div = 0 }
1056};
1057
1058static const struct clksel div4_core_clksel[] = {
1059	{ .parent = &core_ck, .rates = div4_rates },
1060	{ .parent = NULL }
1061};
1062
1063/*
1064 * REVISIT: Are these in DPLL power domain or CM power domain? docs
1065 * may be inconsistent here?
1066 */
1067static struct clk dpll1_fck = {
1068	.name		= "dpll1_fck",
1069	.ops		= &clkops_null,
1070	.parent		= &core_ck,
1071	.init		= &omap2_init_clksel_parent,
1072	.clksel_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1073	.clksel_mask	= OMAP3430_MPU_CLK_SRC_MASK,
1074	.clksel		= div4_core_clksel,
1075	.recalc		= &omap2_clksel_recalc,
1076};
1077
1078static struct clk mpu_ck = {
1079	.name		= "mpu_ck",
1080	.ops		= &clkops_null,
1081	.parent		= &dpll1_x2m2_ck,
1082	.clkdm_name	= "mpu_clkdm",
1083	.recalc		= &followparent_recalc,
1084};
1085
1086/* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1087static const struct clksel_rate arm_fck_rates[] = {
1088	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1089	{ .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1090	{ .div = 0 },
1091};
1092
1093static const struct clksel arm_fck_clksel[] = {
1094	{ .parent = &mpu_ck, .rates = arm_fck_rates },
1095	{ .parent = NULL }
1096};
1097
1098static struct clk arm_fck = {
1099	.name		= "arm_fck",
1100	.ops		= &clkops_null,
1101	.parent		= &mpu_ck,
1102	.init		= &omap2_init_clksel_parent,
1103	.clksel_reg	= OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1104	.clksel_mask	= OMAP3430_ST_MPU_CLK_MASK,
1105	.clksel		= arm_fck_clksel,
1106	.clkdm_name	= "mpu_clkdm",
1107	.recalc		= &omap2_clksel_recalc,
1108};
1109
1110/* XXX What about neon_clkdm ? */
1111
1112/*
1113 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1114 * although it is referenced - so this is a guess
1115 */
1116static struct clk emu_mpu_alwon_ck = {
1117	.name		= "emu_mpu_alwon_ck",
1118	.ops		= &clkops_null,
1119	.parent		= &mpu_ck,
1120	.recalc		= &followparent_recalc,
1121};
1122
1123static struct clk dpll2_fck = {
1124	.name		= "dpll2_fck",
1125	.ops		= &clkops_null,
1126	.parent		= &core_ck,
1127	.init		= &omap2_init_clksel_parent,
1128	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1129	.clksel_mask	= OMAP3430_IVA2_CLK_SRC_MASK,
1130	.clksel		= div4_core_clksel,
1131	.recalc		= &omap2_clksel_recalc,
1132};
1133
1134static struct clk iva2_ck = {
1135	.name		= "iva2_ck",
1136	.ops		= &clkops_omap2_dflt_wait,
1137	.parent		= &dpll2_m2_ck,
1138	.enable_reg	= OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1139	.enable_bit	= OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1140	.clkdm_name	= "iva2_clkdm",
1141	.recalc		= &followparent_recalc,
1142};
1143
1144/* Common interface clocks */
1145
1146static const struct clksel div2_core_clksel[] = {
1147	{ .parent = &core_ck, .rates = div2_rates },
1148	{ .parent = NULL }
1149};
1150
1151static struct clk l3_ick = {
1152	.name		= "l3_ick",
1153	.ops		= &clkops_null,
1154	.parent		= &core_ck,
1155	.init		= &omap2_init_clksel_parent,
1156	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1157	.clksel_mask	= OMAP3430_CLKSEL_L3_MASK,
1158	.clksel		= div2_core_clksel,
1159	.clkdm_name	= "core_l3_clkdm",
1160	.recalc		= &omap2_clksel_recalc,
1161};
1162
1163static const struct clksel div2_l3_clksel[] = {
1164	{ .parent = &l3_ick, .rates = div2_rates },
1165	{ .parent = NULL }
1166};
1167
1168static struct clk l4_ick = {
1169	.name		= "l4_ick",
1170	.ops		= &clkops_null,
1171	.parent		= &l3_ick,
1172	.init		= &omap2_init_clksel_parent,
1173	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1174	.clksel_mask	= OMAP3430_CLKSEL_L4_MASK,
1175	.clksel		= div2_l3_clksel,
1176	.clkdm_name	= "core_l4_clkdm",
1177	.recalc		= &omap2_clksel_recalc,
1178
1179};
1180
1181static const struct clksel div2_l4_clksel[] = {
1182	{ .parent = &l4_ick, .rates = div2_rates },
1183	{ .parent = NULL }
1184};
1185
1186static struct clk rm_ick = {
1187	.name		= "rm_ick",
1188	.ops		= &clkops_null,
1189	.parent		= &l4_ick,
1190	.init		= &omap2_init_clksel_parent,
1191	.clksel_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1192	.clksel_mask	= OMAP3430_CLKSEL_RM_MASK,
1193	.clksel		= div2_l4_clksel,
1194	.recalc		= &omap2_clksel_recalc,
1195};
1196
1197/* GFX power domain */
1198
1199/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1200
1201static const struct clksel gfx_l3_clksel[] = {
1202	{ .parent = &l3_ick, .rates = gfx_l3_rates },
1203	{ .parent = NULL }
1204};
1205
1206/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1207static struct clk gfx_l3_ck = {
1208	.name		= "gfx_l3_ck",
1209	.ops		= &clkops_omap2_dflt_wait,
1210	.parent		= &l3_ick,
1211	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1212	.enable_bit	= OMAP_EN_GFX_SHIFT,
1213	.recalc		= &followparent_recalc,
1214};
1215
1216static struct clk gfx_l3_fck = {
1217	.name		= "gfx_l3_fck",
1218	.ops		= &clkops_null,
1219	.parent		= &gfx_l3_ck,
1220	.init		= &omap2_init_clksel_parent,
1221	.clksel_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1222	.clksel_mask	= OMAP_CLKSEL_GFX_MASK,
1223	.clksel		= gfx_l3_clksel,
1224	.clkdm_name	= "gfx_3430es1_clkdm",
1225	.recalc		= &omap2_clksel_recalc,
1226};
1227
1228static struct clk gfx_l3_ick = {
1229	.name		= "gfx_l3_ick",
1230	.ops		= &clkops_null,
1231	.parent		= &gfx_l3_ck,
1232	.clkdm_name	= "gfx_3430es1_clkdm",
1233	.recalc		= &followparent_recalc,
1234};
1235
1236static struct clk gfx_cg1_ck = {
1237	.name		= "gfx_cg1_ck",
1238	.ops		= &clkops_omap2_dflt_wait,
1239	.parent		= &gfx_l3_fck, /* REVISIT: correct? */
1240	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1241	.enable_bit	= OMAP3430ES1_EN_2D_SHIFT,
1242	.clkdm_name	= "gfx_3430es1_clkdm",
1243	.recalc		= &followparent_recalc,
1244};
1245
1246static struct clk gfx_cg2_ck = {
1247	.name		= "gfx_cg2_ck",
1248	.ops		= &clkops_omap2_dflt_wait,
1249	.parent		= &gfx_l3_fck, /* REVISIT: correct? */
1250	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1251	.enable_bit	= OMAP3430ES1_EN_3D_SHIFT,
1252	.clkdm_name	= "gfx_3430es1_clkdm",
1253	.recalc		= &followparent_recalc,
1254};
1255
1256/* SGX power domain - 3430ES2 only */
1257
1258static const struct clksel_rate sgx_core_rates[] = {
1259	{ .div = 2, .val = 5, .flags = RATE_IN_36XX },
1260	{ .div = 3, .val = 0, .flags = RATE_IN_3XXX },
1261	{ .div = 4, .val = 1, .flags = RATE_IN_3XXX },
1262	{ .div = 6, .val = 2, .flags = RATE_IN_3XXX },
1263	{ .div = 0 },
1264};
1265
1266static const struct clksel_rate sgx_192m_rates[] = {
1267	{ .div = 1,  .val = 4, .flags = RATE_IN_36XX },
1268	{ .div = 0 },
1269};
1270
1271static const struct clksel_rate sgx_corex2_rates[] = {
1272	{ .div = 3, .val = 6, .flags = RATE_IN_36XX },
1273	{ .div = 5, .val = 7, .flags = RATE_IN_36XX },
1274	{ .div = 0 },
1275};
1276
1277static const struct clksel_rate sgx_96m_rates[] = {
1278	{ .div = 1,  .val = 3, .flags = RATE_IN_3XXX },
1279	{ .div = 0 },
1280};
1281
1282static const struct clksel sgx_clksel[] = {
1283	{ .parent = &core_ck,	 .rates = sgx_core_rates },
1284	{ .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1285	{ .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
1286	{ .parent = &corex2_fck, .rates = sgx_corex2_rates },
1287	{ .parent = NULL }
1288};
1289
1290static struct clk sgx_fck = {
1291	.name		= "sgx_fck",
1292	.ops		= &clkops_omap2_dflt_wait,
1293	.init		= &omap2_init_clksel_parent,
1294	.enable_reg	= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1295	.enable_bit	= OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1296	.clksel_reg	= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1297	.clksel_mask	= OMAP3430ES2_CLKSEL_SGX_MASK,
1298	.clksel		= sgx_clksel,
1299	.clkdm_name	= "sgx_clkdm",
1300	.recalc		= &omap2_clksel_recalc,
1301	.set_rate	= &omap2_clksel_set_rate,
1302	.round_rate	= &omap2_clksel_round_rate
1303};
1304
1305static struct clk sgx_ick = {
1306	.name		= "sgx_ick",
1307	.ops		= &clkops_omap2_dflt_wait,
1308	.parent		= &l3_ick,
1309	.enable_reg	= OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1310	.enable_bit	= OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1311	.clkdm_name	= "sgx_clkdm",
1312	.recalc		= &followparent_recalc,
1313};
1314
1315/* CORE power domain */
1316
1317static struct clk d2d_26m_fck = {
1318	.name		= "d2d_26m_fck",
1319	.ops		= &clkops_omap2_dflt_wait,
1320	.parent		= &sys_ck,
1321	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1322	.enable_bit	= OMAP3430ES1_EN_D2D_SHIFT,
1323	.clkdm_name	= "d2d_clkdm",
1324	.recalc		= &followparent_recalc,
1325};
1326
1327static struct clk modem_fck = {
1328	.name		= "modem_fck",
1329	.ops		= &clkops_omap2_dflt_wait,
1330	.parent		= &sys_ck,
1331	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1332	.enable_bit	= OMAP3430_EN_MODEM_SHIFT,
1333	.clkdm_name	= "d2d_clkdm",
1334	.recalc		= &followparent_recalc,
1335};
1336
1337static struct clk sad2d_ick = {
1338	.name		= "sad2d_ick",
1339	.ops		= &clkops_omap2_dflt_wait,
1340	.parent		= &l3_ick,
1341	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1342	.enable_bit	= OMAP3430_EN_SAD2D_SHIFT,
1343	.clkdm_name	= "d2d_clkdm",
1344	.recalc		= &followparent_recalc,
1345};
1346
1347static struct clk mad2d_ick = {
1348	.name		= "mad2d_ick",
1349	.ops		= &clkops_omap2_dflt_wait,
1350	.parent		= &l3_ick,
1351	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1352	.enable_bit	= OMAP3430_EN_MAD2D_SHIFT,
1353	.clkdm_name	= "d2d_clkdm",
1354	.recalc		= &followparent_recalc,
1355};
1356
1357static const struct clksel omap343x_gpt_clksel[] = {
1358	{ .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1359	{ .parent = &sys_ck,	   .rates = gpt_sys_rates },
1360	{ .parent = NULL}
1361};
1362
1363static struct clk gpt10_fck = {
1364	.name		= "gpt10_fck",
1365	.ops		= &clkops_omap2_dflt_wait,
1366	.parent		= &sys_ck,
1367	.init		= &omap2_init_clksel_parent,
1368	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1369	.enable_bit	= OMAP3430_EN_GPT10_SHIFT,
1370	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1371	.clksel_mask	= OMAP3430_CLKSEL_GPT10_MASK,
1372	.clksel		= omap343x_gpt_clksel,
1373	.clkdm_name	= "core_l4_clkdm",
1374	.recalc		= &omap2_clksel_recalc,
1375};
1376
1377static struct clk gpt11_fck = {
1378	.name		= "gpt11_fck",
1379	.ops		= &clkops_omap2_dflt_wait,
1380	.parent		= &sys_ck,
1381	.init		= &omap2_init_clksel_parent,
1382	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1383	.enable_bit	= OMAP3430_EN_GPT11_SHIFT,
1384	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1385	.clksel_mask	= OMAP3430_CLKSEL_GPT11_MASK,
1386	.clksel		= omap343x_gpt_clksel,
1387	.clkdm_name	= "core_l4_clkdm",
1388	.recalc		= &omap2_clksel_recalc,
1389};
1390
1391static struct clk cpefuse_fck = {
1392	.name		= "cpefuse_fck",
1393	.ops		= &clkops_omap2_dflt,
1394	.parent		= &sys_ck,
1395	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1396	.enable_bit	= OMAP3430ES2_EN_CPEFUSE_SHIFT,
1397	.recalc		= &followparent_recalc,
1398};
1399
1400static struct clk ts_fck = {
1401	.name		= "ts_fck",
1402	.ops		= &clkops_omap2_dflt,
1403	.parent		= &omap_32k_fck,
1404	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1405	.enable_bit	= OMAP3430ES2_EN_TS_SHIFT,
1406	.recalc		= &followparent_recalc,
1407};
1408
1409static struct clk usbtll_fck = {
1410	.name		= "usbtll_fck",
1411	.ops		= &clkops_omap2_dflt,
1412	.parent		= &dpll5_m2_ck,
1413	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1414	.enable_bit	= OMAP3430ES2_EN_USBTLL_SHIFT,
1415	.recalc		= &followparent_recalc,
1416};
1417
1418/* CORE 96M FCLK-derived clocks */
1419
1420static struct clk core_96m_fck = {
1421	.name		= "core_96m_fck",
1422	.ops		= &clkops_null,
1423	.parent		= &omap_96m_fck,
1424	.clkdm_name	= "core_l4_clkdm",
1425	.recalc		= &followparent_recalc,
1426};
1427
1428static struct clk mmchs3_fck = {
1429	.name		= "mmchs3_fck",
1430	.ops		= &clkops_omap2_dflt_wait,
1431	.parent		= &core_96m_fck,
1432	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1433	.enable_bit	= OMAP3430ES2_EN_MMC3_SHIFT,
1434	.clkdm_name	= "core_l4_clkdm",
1435	.recalc		= &followparent_recalc,
1436};
1437
1438static struct clk mmchs2_fck = {
1439	.name		= "mmchs2_fck",
1440	.ops		= &clkops_omap2_dflt_wait,
1441	.parent		= &core_96m_fck,
1442	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1443	.enable_bit	= OMAP3430_EN_MMC2_SHIFT,
1444	.clkdm_name	= "core_l4_clkdm",
1445	.recalc		= &followparent_recalc,
1446};
1447
1448static struct clk mspro_fck = {
1449	.name		= "mspro_fck",
1450	.ops		= &clkops_omap2_dflt_wait,
1451	.parent		= &core_96m_fck,
1452	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1453	.enable_bit	= OMAP3430_EN_MSPRO_SHIFT,
1454	.clkdm_name	= "core_l4_clkdm",
1455	.recalc		= &followparent_recalc,
1456};
1457
1458static struct clk mmchs1_fck = {
1459	.name		= "mmchs1_fck",
1460	.ops		= &clkops_omap2_dflt_wait,
1461	.parent		= &core_96m_fck,
1462	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1463	.enable_bit	= OMAP3430_EN_MMC1_SHIFT,
1464	.clkdm_name	= "core_l4_clkdm",
1465	.recalc		= &followparent_recalc,
1466};
1467
1468static struct clk i2c3_fck = {
1469	.name		= "i2c3_fck",
1470	.ops		= &clkops_omap2_dflt_wait,
1471	.parent		= &core_96m_fck,
1472	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1473	.enable_bit	= OMAP3430_EN_I2C3_SHIFT,
1474	.clkdm_name	= "core_l4_clkdm",
1475	.recalc		= &followparent_recalc,
1476};
1477
1478static struct clk i2c2_fck = {
1479	.name		= "i2c2_fck",
1480	.ops		= &clkops_omap2_dflt_wait,
1481	.parent		= &core_96m_fck,
1482	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1483	.enable_bit	= OMAP3430_EN_I2C2_SHIFT,
1484	.clkdm_name	= "core_l4_clkdm",
1485	.recalc		= &followparent_recalc,
1486};
1487
1488static struct clk i2c1_fck = {
1489	.name		= "i2c1_fck",
1490	.ops		= &clkops_omap2_dflt_wait,
1491	.parent		= &core_96m_fck,
1492	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1493	.enable_bit	= OMAP3430_EN_I2C1_SHIFT,
1494	.clkdm_name	= "core_l4_clkdm",
1495	.recalc		= &followparent_recalc,
1496};
1497
1498/*
1499 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1500 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1501 */
1502static const struct clksel_rate common_mcbsp_96m_rates[] = {
1503	{ .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1504	{ .div = 0 }
1505};
1506
1507static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1508	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1509	{ .div = 0 }
1510};
1511
1512static const struct clksel mcbsp_15_clksel[] = {
1513	{ .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1514	{ .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1515	{ .parent = NULL }
1516};
1517
1518static struct clk mcbsp5_fck = {
1519	.name		= "mcbsp5_fck",
1520	.ops		= &clkops_omap2_dflt_wait,
1521	.init		= &omap2_init_clksel_parent,
1522	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1523	.enable_bit	= OMAP3430_EN_MCBSP5_SHIFT,
1524	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1525	.clksel_mask	= OMAP2_MCBSP5_CLKS_MASK,
1526	.clksel		= mcbsp_15_clksel,
1527	.clkdm_name	= "core_l4_clkdm",
1528	.recalc		= &omap2_clksel_recalc,
1529};
1530
1531static struct clk mcbsp1_fck = {
1532	.name		= "mcbsp1_fck",
1533	.ops		= &clkops_omap2_dflt_wait,
1534	.init		= &omap2_init_clksel_parent,
1535	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1536	.enable_bit	= OMAP3430_EN_MCBSP1_SHIFT,
1537	.clksel_reg	= OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1538	.clksel_mask	= OMAP2_MCBSP1_CLKS_MASK,
1539	.clksel		= mcbsp_15_clksel,
1540	.clkdm_name	= "core_l4_clkdm",
1541	.recalc		= &omap2_clksel_recalc,
1542};
1543
1544/* CORE_48M_FCK-derived clocks */
1545
1546static struct clk core_48m_fck = {
1547	.name		= "core_48m_fck",
1548	.ops		= &clkops_null,
1549	.parent		= &omap_48m_fck,
1550	.clkdm_name	= "core_l4_clkdm",
1551	.recalc		= &followparent_recalc,
1552};
1553
1554static struct clk mcspi4_fck = {
1555	.name		= "mcspi4_fck",
1556	.ops		= &clkops_omap2_dflt_wait,
1557	.parent		= &core_48m_fck,
1558	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1559	.enable_bit	= OMAP3430_EN_MCSPI4_SHIFT,
1560	.recalc		= &followparent_recalc,
1561};
1562
1563static struct clk mcspi3_fck = {
1564	.name		= "mcspi3_fck",
1565	.ops		= &clkops_omap2_dflt_wait,
1566	.parent		= &core_48m_fck,
1567	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1568	.enable_bit	= OMAP3430_EN_MCSPI3_SHIFT,
1569	.recalc		= &followparent_recalc,
1570};
1571
1572static struct clk mcspi2_fck = {
1573	.name		= "mcspi2_fck",
1574	.ops		= &clkops_omap2_dflt_wait,
1575	.parent		= &core_48m_fck,
1576	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1577	.enable_bit	= OMAP3430_EN_MCSPI2_SHIFT,
1578	.recalc		= &followparent_recalc,
1579};
1580
1581static struct clk mcspi1_fck = {
1582	.name		= "mcspi1_fck",
1583	.ops		= &clkops_omap2_dflt_wait,
1584	.parent		= &core_48m_fck,
1585	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1586	.enable_bit	= OMAP3430_EN_MCSPI1_SHIFT,
1587	.recalc		= &followparent_recalc,
1588};
1589
1590static struct clk uart2_fck = {
1591	.name		= "uart2_fck",
1592	.ops		= &clkops_omap2_dflt_wait,
1593	.parent		= &core_48m_fck,
1594	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1595	.enable_bit	= OMAP3430_EN_UART2_SHIFT,
1596	.clkdm_name	= "core_l4_clkdm",
1597	.recalc		= &followparent_recalc,
1598};
1599
1600static struct clk uart1_fck = {
1601	.name		= "uart1_fck",
1602	.ops		= &clkops_omap2_dflt_wait,
1603	.parent		= &core_48m_fck,
1604	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1605	.enable_bit	= OMAP3430_EN_UART1_SHIFT,
1606	.clkdm_name	= "core_l4_clkdm",
1607	.recalc		= &followparent_recalc,
1608};
1609
1610static struct clk fshostusb_fck = {
1611	.name		= "fshostusb_fck",
1612	.ops		= &clkops_omap2_dflt_wait,
1613	.parent		= &core_48m_fck,
1614	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1615	.enable_bit	= OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1616	.recalc		= &followparent_recalc,
1617};
1618
1619/* CORE_12M_FCK based clocks */
1620
1621static struct clk core_12m_fck = {
1622	.name		= "core_12m_fck",
1623	.ops		= &clkops_null,
1624	.parent		= &omap_12m_fck,
1625	.clkdm_name	= "core_l4_clkdm",
1626	.recalc		= &followparent_recalc,
1627};
1628
1629static struct clk hdq_fck = {
1630	.name		= "hdq_fck",
1631	.ops		= &clkops_omap2_dflt_wait,
1632	.parent		= &core_12m_fck,
1633	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1634	.enable_bit	= OMAP3430_EN_HDQ_SHIFT,
1635	.recalc		= &followparent_recalc,
1636};
1637
1638/* DPLL3-derived clock */
1639
1640static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1641	{ .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1642	{ .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1643	{ .div = 3, .val = 3, .flags = RATE_IN_3XXX },
1644	{ .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1645	{ .div = 6, .val = 6, .flags = RATE_IN_3XXX },
1646	{ .div = 8, .val = 8, .flags = RATE_IN_3XXX },
1647	{ .div = 0 }
1648};
1649
1650static const struct clksel ssi_ssr_clksel[] = {
1651	{ .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1652	{ .parent = NULL }
1653};
1654
1655static struct clk ssi_ssr_fck_3430es1 = {
1656	.name		= "ssi_ssr_fck",
1657	.ops		= &clkops_omap2_dflt,
1658	.init		= &omap2_init_clksel_parent,
1659	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1660	.enable_bit	= OMAP3430_EN_SSI_SHIFT,
1661	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1662	.clksel_mask	= OMAP3430_CLKSEL_SSI_MASK,
1663	.clksel		= ssi_ssr_clksel,
1664	.clkdm_name	= "core_l4_clkdm",
1665	.recalc		= &omap2_clksel_recalc,
1666};
1667
1668static struct clk ssi_ssr_fck_3430es2 = {
1669	.name		= "ssi_ssr_fck",
1670	.ops		= &clkops_omap3430es2_ssi_wait,
1671	.init		= &omap2_init_clksel_parent,
1672	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1673	.enable_bit	= OMAP3430_EN_SSI_SHIFT,
1674	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1675	.clksel_mask	= OMAP3430_CLKSEL_SSI_MASK,
1676	.clksel		= ssi_ss

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