/arch/arm/mach-mv78xx0/irq.c

 1/*
 2 * arch/arm/mach-mv78xx0/irq.c
 3 *
 4 * MV78xx0 IRQ handling.
 5 *
 6 * This file is licensed under the terms of the GNU General Public
 7 * License version 2.  This program is licensed "as is" without any
 8 * warranty of any kind, whether express or implied.
 9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/pci.h>
14#include <linux/irq.h>
15#include <asm/gpio.h>
16#include <mach/bridge-regs.h>
17#include <plat/irq.h>
18#include "common.h"
19
20static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
21{
22	BUG_ON(irq < IRQ_MV78XX0_GPIO_0_7 || irq > IRQ_MV78XX0_GPIO_24_31);
23
24	orion_gpio_irq_handler((irq - IRQ_MV78XX0_GPIO_0_7) << 3);
25}
26
27void __init mv78xx0_init_irq(void)
28{
29	int i;
30
31	/* Initialize gpiolib. */
32	orion_gpio_init();
33
34	orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
35	orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
36	orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
37
38	/*
39	 * Mask and clear GPIO IRQ interrupts.
40	 */
41	writel(0, GPIO_LEVEL_MASK(0));
42	writel(0, GPIO_EDGE_MASK(0));
43	writel(0, GPIO_EDGE_CAUSE(0));
44
45	for (i = IRQ_MV78XX0_GPIO_START; i < NR_IRQS; i++) {
46		set_irq_chip(i, &orion_gpio_irq_chip);
47		set_irq_handler(i, handle_level_irq);
48		irq_desc[i].status |= IRQ_LEVEL;
49		set_irq_flags(i, IRQF_VALID);
50	}
51	set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
52	set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
53	set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);
54	set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler);
55}