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/arch/arm/mach-msm/timer.c

https://bitbucket.org/sammyz/iscream_thunderc-2.6.35-rebase
C | 1101 lines | 875 code | 149 blank | 77 comment | 121 complexity | dc426bf05f38ddede69a655a793e823c MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
   1/*
   2 * Copyright (C) 2007 Google, Inc.
   3 * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
   4 *
   5 * This software is licensed under the terms of the GNU General Public
   6 * License version 2, as published by the Free Software Foundation, and
   7 * may be copied, distributed, and modified under those terms.
   8 *
   9 * This program is distributed in the hope that it will be useful,
  10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 * GNU General Public License for more details.
  13 *
  14 */
  15
  16#include <linux/init.h>
  17#include <linux/time.h>
  18#include <linux/interrupt.h>
  19#include <linux/irq.h>
  20#include <linux/clk.h>
  21#include <linux/clockchips.h>
  22#include <linux/delay.h>
  23#include <linux/io.h>
  24#include <linux/percpu.h>
  25
  26#include <asm/mach/time.h>
  27#include <mach/msm_iomap.h>
  28#include <mach/irqs.h>
  29
  30#if defined(CONFIG_MSM_SMD)
  31#include "smd_private.h"
  32#endif
  33#include "timer.h"
  34#include "clock-8x60.h"
  35
  36enum {
  37	MSM_TIMER_DEBUG_SYNC = 1U << 0,
  38};
  39static int msm_timer_debug_mask;
  40module_param_named(debug_mask, msm_timer_debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);
  41
  42#if defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60)
  43#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4)
  44#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
  45#else
  46#define MSM_GPT_BASE MSM_TMR_BASE
  47#define MSM_DGT_BASE (MSM_TMR_BASE + 0x10)
  48#endif
  49
  50#ifdef CONFIG_MSM7X00A_USE_GP_TIMER
  51	#define DG_TIMER_RATING 100
  52	#define MSM_GLOBAL_TIMER MSM_CLOCK_GPT
  53#else
  54	#define DG_TIMER_RATING 300
  55	#define MSM_GLOBAL_TIMER MSM_CLOCK_DGT
  56#endif
  57
  58#if defined(CONFIG_ARCH_MSM_ARM11)
  59#define MSM_DGT_SHIFT (5)
  60#else
  61#define MSM_DGT_SHIFT (0)
  62#endif
  63
  64#define TIMER_MATCH_VAL         0x0000
  65#define TIMER_COUNT_VAL         0x0004
  66#define TIMER_ENABLE            0x0008
  67#define TIMER_CLEAR             0x000C
  68#define DGT_CLK_CTL             0x0034
  69enum {
  70	DGT_CLK_CTL_DIV_1 = 0,
  71	DGT_CLK_CTL_DIV_2 = 1,
  72	DGT_CLK_CTL_DIV_3 = 2,
  73	DGT_CLK_CTL_DIV_4 = 3,
  74};
  75#define TIMER_ENABLE_EN              1
  76#define TIMER_ENABLE_CLR_ON_MATCH_EN 2
  77
  78#define LOCAL_TIMER 0
  79#define GLOBAL_TIMER 1
  80
  81/*
  82 * MSM_TMR_GLOBAL is added to the regbase of a timer to force the memory access
  83 * to come from the CPU0 region.
  84 */
  85#ifdef MSM_TMR0_BASE
  86#define MSM_TMR_GLOBAL		(MSM_TMR0_BASE - MSM_TMR_BASE)
  87#else
  88#define MSM_TMR_GLOBAL		0
  89#endif
  90
  91#if defined(CONFIG_MSM_DIRECT_SCLK_ACCESS)
  92#define MPM_SCLK_COUNT_VAL    0x0024
  93#endif
  94
  95#define NR_TIMERS ARRAY_SIZE(msm_clocks)
  96
  97#if defined(CONFIG_ARCH_QSD8X50)
  98#define DGT_HZ 4800000	/* Uses TCXO/4 (19.2 MHz / 4) */
  99#elif defined(CONFIG_ARCH_MSM7X30)
 100#define DGT_HZ 6144000	/* Uses LPXO/4 (24.576 MHz / 4) */
 101#elif defined(CONFIG_ARCH_MSM8X60)
 102/* Uses PXO/4 (24.576 MHz / 4) on V1, (27 MHz / 4) on V2 */
 103#define DGT_HZ 6750000
 104#else
 105#define DGT_HZ 19200000	/* Uses TCXO (19.2 MHz) */
 106#endif
 107
 108#define GPT_HZ 32768
 109#define SCLK_HZ 32768
 110
 111#if defined(CONFIG_MSM_N_WAY_SMSM)
 112/* Time Master State Bits */
 113#define MASTER_BITS_PER_CPU        1
 114#define MASTER_TIME_PENDING \
 115	(0x01UL << (MASTER_BITS_PER_CPU * SMSM_APPS_STATE))
 116
 117/* Time Slave State Bits */
 118#define SLAVE_TIME_REQUEST         0x0400
 119#define SLAVE_TIME_POLL            0x0800
 120#define SLAVE_TIME_INIT            0x1000
 121#endif
 122
 123static irqreturn_t msm_timer_interrupt(int irq, void *dev_id);
 124static cycle_t msm_gpt_read(struct clocksource *cs);
 125static cycle_t msm_dgt_read(struct clocksource *cs);
 126static void msm_timer_set_mode(enum clock_event_mode mode,
 127			       struct clock_event_device *evt);
 128static int msm_timer_set_next_event(unsigned long cycles,
 129				    struct clock_event_device *evt);
 130
 131enum {
 132	MSM_CLOCK_FLAGS_UNSTABLE_COUNT = 1U << 0,
 133	MSM_CLOCK_FLAGS_ODD_MATCH_WRITE = 1U << 1,
 134	MSM_CLOCK_FLAGS_DELAYED_WRITE_POST = 1U << 2,
 135};
 136
 137struct msm_clock {
 138	struct clock_event_device   clockevent;
 139	struct clocksource          clocksource;
 140	struct irqaction            irq;
 141	void __iomem                *regbase;
 142	uint32_t                    freq;
 143	uint32_t                    shift;
 144	uint32_t                    flags;
 145	uint32_t                    write_delay;
 146	uint32_t                    rollover_offset;
 147	uint32_t                    index;
 148};
 149
 150enum {
 151	MSM_CLOCK_GPT,
 152	MSM_CLOCK_DGT,
 153};
 154
 155
 156struct msm_clock_percpu_data {
 157	uint32_t                  last_set;
 158	uint32_t                  sleep_offset;
 159	uint32_t                  alarm_vtime;
 160	uint32_t                  alarm;
 161	uint32_t                  non_sleep_offset;
 162	uint32_t                  in_sync;
 163	cycle_t                   stopped_tick;
 164	int                       stopped;
 165	uint32_t                  last_sync_gpt;
 166	u64                       last_sync_jiffies;
 167};
 168
 169struct msm_timer_sync_data_t {
 170	struct msm_clock *clock;
 171	uint32_t         timeout;
 172	int              exit_sleep;
 173};
 174
 175static struct msm_clock msm_clocks[] = {
 176	[MSM_CLOCK_GPT] = {
 177		.clockevent = {
 178			.name           = "gp_timer",
 179			.features       = CLOCK_EVT_FEAT_ONESHOT,
 180			.shift          = 32,
 181			.rating         = 200,
 182			.set_next_event = msm_timer_set_next_event,
 183			.set_mode       = msm_timer_set_mode,
 184		},
 185		.clocksource = {
 186			.name           = "gp_timer",
 187			.rating         = 200,
 188			.read           = msm_gpt_read,
 189			.mask           = CLOCKSOURCE_MASK(32),
 190			.shift          = 17,
 191			.flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 192		},
 193		.irq = {
 194			.name    = "gp_timer",
 195			.flags   = IRQF_DISABLED | IRQF_TIMER |
 196				   IRQF_TRIGGER_RISING,
 197			.handler = msm_timer_interrupt,
 198			.dev_id  = &msm_clocks[0].clockevent,
 199			.irq     = INT_GP_TIMER_EXP
 200		},
 201		.regbase = MSM_GPT_BASE,
 202		.freq = GPT_HZ,
 203		.index = MSM_CLOCK_GPT,
 204		.flags =
 205			MSM_CLOCK_FLAGS_UNSTABLE_COUNT |
 206			MSM_CLOCK_FLAGS_ODD_MATCH_WRITE |
 207			MSM_CLOCK_FLAGS_DELAYED_WRITE_POST,
 208		.write_delay = 9,
 209	},
 210	[MSM_CLOCK_DGT] = {
 211		.clockevent = {
 212			.name           = "dg_timer",
 213			.features       = CLOCK_EVT_FEAT_ONESHOT,
 214			.shift          = 32 + MSM_DGT_SHIFT,
 215			.rating         = DG_TIMER_RATING,
 216			.set_next_event = msm_timer_set_next_event,
 217			.set_mode       = msm_timer_set_mode,
 218		},
 219		.clocksource = {
 220			.name           = "dg_timer",
 221			.rating         = DG_TIMER_RATING,
 222			.read           = msm_dgt_read,
 223			.mask           = CLOCKSOURCE_MASK((32-MSM_DGT_SHIFT)),
 224			.shift          = 24 - MSM_DGT_SHIFT,
 225			.flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 226		},
 227		.irq = {
 228			.name    = "dg_timer",
 229			.flags   = IRQF_DISABLED | IRQF_TIMER |
 230				   IRQF_TRIGGER_RISING,
 231			.handler = msm_timer_interrupt,
 232			.dev_id  = &msm_clocks[1].clockevent,
 233			.irq     = INT_DEBUG_TIMER_EXP
 234		},
 235		.regbase = MSM_DGT_BASE,
 236		.freq = DGT_HZ >> MSM_DGT_SHIFT,
 237		.index = MSM_CLOCK_DGT,
 238		.shift = MSM_DGT_SHIFT,
 239		.write_delay = 2,
 240	}
 241};
 242
 243static struct clock_event_device *local_clock_event;
 244
 245static DEFINE_PER_CPU(struct msm_clock_percpu_data[NR_TIMERS],
 246    msm_clocks_percpu);
 247
 248static DEFINE_PER_CPU(struct msm_clock *, msm_active_clock);
 249
 250static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
 251{
 252	struct clock_event_device *evt = dev_id;
 253	if (smp_processor_id() != 0)
 254		evt = local_clock_event;
 255	if (evt->event_handler == NULL)
 256		return IRQ_HANDLED;
 257	evt->event_handler(evt);
 258	return IRQ_HANDLED;
 259}
 260
 261static uint32_t msm_read_timer_count(struct msm_clock *clock, int global)
 262{
 263	uint32_t t1, t2;
 264	int loop_count = 0;
 265
 266	if (global)
 267		t1 = readl(clock->regbase + TIMER_COUNT_VAL + MSM_TMR_GLOBAL);
 268	else
 269		t1 = readl(clock->regbase + TIMER_COUNT_VAL);
 270
 271	if (!(clock->flags & MSM_CLOCK_FLAGS_UNSTABLE_COUNT))
 272		return t1;
 273	while (1) {
 274		if (global)
 275			t2 = readl(clock->regbase + TIMER_COUNT_VAL +
 276					MSM_TMR_GLOBAL);
 277		else
 278			t2 = readl(clock->regbase + TIMER_COUNT_VAL);
 279		if (t1 == t2)
 280			return t1;
 281		if (loop_count++ > 10) {
 282			printk(KERN_ERR "msm_read_timer_count timer %s did not"
 283			       "stabilize %u != %u\n", clock->clockevent.name,
 284			       t2, t1);
 285			return t2;
 286		}
 287		t1 = t2;
 288	}
 289}
 290
 291static cycle_t msm_gpt_read(struct clocksource *cs)
 292{
 293	struct msm_clock *clock = &msm_clocks[MSM_CLOCK_GPT];
 294	struct msm_clock_percpu_data *clock_state =
 295		&per_cpu(msm_clocks_percpu, 0)[MSM_CLOCK_GPT];
 296
 297	if (clock_state->stopped)
 298		return clock_state->stopped_tick;
 299
 300	return msm_read_timer_count(clock, GLOBAL_TIMER) +
 301		clock_state->sleep_offset;
 302}
 303
 304static cycle_t msm_dgt_read(struct clocksource *cs)
 305{
 306	struct msm_clock *clock = &msm_clocks[MSM_CLOCK_DGT];
 307	struct msm_clock_percpu_data *clock_state =
 308		&per_cpu(msm_clocks_percpu, 0)[MSM_CLOCK_DGT];
 309
 310	if (clock_state->stopped)
 311		return clock_state->stopped_tick >> MSM_DGT_SHIFT;
 312
 313	return (msm_read_timer_count(clock, GLOBAL_TIMER) +
 314		clock_state->sleep_offset) >> MSM_DGT_SHIFT;
 315}
 316
 317#ifdef CONFIG_SMP
 318static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt)
 319{
 320	int i;
 321	for (i = 0; i < NR_TIMERS; i++)
 322		if (evt == &(msm_clocks[i].clockevent))
 323			return &msm_clocks[i];
 324	return &msm_clocks[MSM_GLOBAL_TIMER];
 325}
 326#endif
 327
 328static int msm_timer_set_next_event(unsigned long cycles,
 329				    struct clock_event_device *evt)
 330{
 331	int i;
 332	struct msm_clock *clock;
 333	struct msm_clock_percpu_data *clock_state;
 334	uint32_t now;
 335	uint32_t alarm;
 336	int late;
 337
 338#ifdef CONFIG_SMP
 339	clock = clockevent_to_clock(evt);
 340#else
 341	clock = container_of(evt, struct msm_clock, clockevent);
 342#endif
 343	clock_state = &__get_cpu_var(msm_clocks_percpu)[clock->index];
 344	if (clock_state->stopped)
 345		return 0;
 346	now = msm_read_timer_count(clock, LOCAL_TIMER);
 347	alarm = now + (cycles << clock->shift);
 348	if (clock->flags & MSM_CLOCK_FLAGS_ODD_MATCH_WRITE)
 349		while (now == clock_state->last_set)
 350			now = msm_read_timer_count(clock, LOCAL_TIMER);
 351
 352	clock_state->alarm = alarm;
 353	writel(alarm, clock->regbase + TIMER_MATCH_VAL);
 354
 355	if (clock->flags & MSM_CLOCK_FLAGS_DELAYED_WRITE_POST) {
 356		/* read the counter four extra times to make sure write posts
 357		   before reading the time */
 358		for (i = 0; i < 4; i++)
 359			readl(clock->regbase + TIMER_COUNT_VAL);
 360	}
 361	now = msm_read_timer_count(clock, LOCAL_TIMER);
 362	clock_state->last_set = now;
 363	clock_state->alarm_vtime = alarm + clock_state->sleep_offset;
 364	late = now - alarm;
 365	if (late >= (int)(-clock->write_delay << clock->shift) && late < DGT_HZ*5) {
 366		static int print_limit = 10;
 367		if (print_limit > 0) {
 368			print_limit--;
 369			printk(KERN_NOTICE "msm_timer_set_next_event(%lu) "
 370			       "clock %s, alarm already expired, now %x, "
 371			       "alarm %x, late %d%s\n",
 372			       cycles, clock->clockevent.name, now, alarm, late,
 373			       print_limit ? "" : " stop printing");
 374		}
 375		return -ETIME;
 376	}
 377	return 0;
 378}
 379
 380static void msm_timer_set_mode(enum clock_event_mode mode,
 381			       struct clock_event_device *evt)
 382{
 383	struct msm_clock *clock;
 384	struct msm_clock_percpu_data *clock_state, *gpt_state;
 385	unsigned long irq_flags;
 386
 387#ifdef CONFIG_SMP
 388	clock = clockevent_to_clock(evt);
 389#else
 390	clock = container_of(evt, struct msm_clock, clockevent);
 391#endif
 392	clock_state = &__get_cpu_var(msm_clocks_percpu)[clock->index];
 393	gpt_state = &__get_cpu_var(msm_clocks_percpu)[MSM_CLOCK_GPT];
 394
 395	local_irq_save(irq_flags);
 396
 397	switch (mode) {
 398	case CLOCK_EVT_MODE_RESUME:
 399	case CLOCK_EVT_MODE_PERIODIC:
 400		break;
 401	case CLOCK_EVT_MODE_ONESHOT:
 402		clock_state->stopped = 0;
 403		clock_state->sleep_offset =
 404			-msm_read_timer_count(clock, LOCAL_TIMER) +
 405			clock_state->stopped_tick;
 406		get_cpu_var(msm_active_clock) = clock;
 407		put_cpu_var(msm_active_clock);
 408		writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
 409		if (clock != &msm_clocks[MSM_CLOCK_GPT])
 410			writel(TIMER_ENABLE_EN,
 411				msm_clocks[MSM_CLOCK_GPT].regbase +
 412			       TIMER_ENABLE);
 413		break;
 414	case CLOCK_EVT_MODE_UNUSED:
 415	case CLOCK_EVT_MODE_SHUTDOWN:
 416		get_cpu_var(msm_active_clock) = NULL;
 417		put_cpu_var(msm_active_clock);
 418		clock_state->in_sync = 0;
 419		clock_state->stopped = 1;
 420		clock_state->stopped_tick =
 421			msm_read_timer_count(clock, LOCAL_TIMER) +
 422			clock_state->sleep_offset;
 423		writel(0, clock->regbase + TIMER_MATCH_VAL);
 424#ifdef CONFIG_ARCH_MSM_SCORPIONMP
 425		if (clock != &msm_clocks[MSM_CLOCK_DGT] || smp_processor_id())
 426#endif
 427			writel(0, clock->regbase + TIMER_ENABLE);
 428		if (clock != &msm_clocks[MSM_CLOCK_GPT]) {
 429			gpt_state->in_sync = 0;
 430			writel(0, msm_clocks[MSM_CLOCK_GPT].regbase +
 431			       TIMER_ENABLE);
 432		}
 433		break;
 434	}
 435	local_irq_restore(irq_flags);
 436}
 437
 438/*
 439 * Retrieve the cycle count from sclk and optionally synchronize local clock
 440 * with the sclk value.
 441 *
 442 * time_start and time_expired are callbacks that must be specified.  The
 443 * protocol uses them to detect timeout.  The update callback is optional.
 444 * If not NULL, update will be called so that it can update local clock.
 445 *
 446 * The function does not use the argument data directly; it passes data to
 447 * the callbacks.
 448 *
 449 * Return value:
 450 *      0: the operation failed
 451 *      >0: the slow clock value after time-sync
 452 */
 453static void (*msm_timer_sync_timeout)(void);
 454#if defined(CONFIG_MSM_DIRECT_SCLK_ACCESS)
 455static uint32_t msm_timer_do_sync_to_sclk(
 456	void (*time_start)(struct msm_timer_sync_data_t *data),
 457	bool (*time_expired)(struct msm_timer_sync_data_t *data),
 458	void (*update)(struct msm_timer_sync_data_t *, uint32_t, uint32_t),
 459	struct msm_timer_sync_data_t *data)
 460{
 461	uint32_t t1, t2;
 462	int loop_count = 10;
 463	int loop_zero_count = 3;
 464	int tmp = USEC_PER_SEC/SCLK_HZ/(loop_zero_count-1);
 465
 466	while (loop_zero_count--) {
 467		t1 = readl(MSM_RPM_MPM_BASE + MPM_SCLK_COUNT_VAL);
 468		do {
 469			udelay(1);
 470			t2 = t1;
 471			t1 = readl(MSM_RPM_MPM_BASE + MPM_SCLK_COUNT_VAL);
 472		} while ((t2 != t1) && --loop_count);
 473
 474		if (!loop_count) {
 475			printk(KERN_EMERG "SCLK  did not stabilize\n");
 476			return 0;
 477		}
 478
 479		if (t1)
 480			break;
 481
 482		udelay(tmp);
 483	}
 484
 485	if (!loop_zero_count) {
 486		printk(KERN_EMERG "SCLK reads zero\n");
 487		return 0;
 488	}
 489
 490	if (update != NULL)
 491		update(data, t1, SCLK_HZ);
 492	return t1;
 493}
 494#elif defined(CONFIG_MSM_N_WAY_SMSM)
 495static uint32_t msm_timer_do_sync_to_sclk(
 496	void (*time_start)(struct msm_timer_sync_data_t *data),
 497	bool (*time_expired)(struct msm_timer_sync_data_t *data),
 498	void (*update)(struct msm_timer_sync_data_t *, uint32_t, uint32_t),
 499	struct msm_timer_sync_data_t *data)
 500{
 501	uint32_t *smem_clock;
 502	uint32_t smem_clock_val;
 503	uint32_t state;
 504
 505	smem_clock = smem_alloc(SMEM_SMEM_SLOW_CLOCK_VALUE, sizeof(uint32_t));
 506	if (smem_clock == NULL) {
 507		printk(KERN_ERR "no smem clock\n");
 508		return 0;
 509	}
 510
 511	state = smsm_get_state(SMSM_MODEM_STATE);
 512	if ((state & SMSM_INIT) == 0) {
 513		printk(KERN_ERR "smsm not initialized\n");
 514		return 0;
 515	}
 516
 517	time_start(data);
 518	while ((state = smsm_get_state(SMSM_TIME_MASTER_DEM)) &
 519		MASTER_TIME_PENDING) {
 520		if (time_expired(data)) {
 521			printk(KERN_EMERG "get_smem_clock: timeout 1 still "
 522				"invalid state %x\n", state);
 523			msm_timer_sync_timeout();
 524		}
 525	}
 526
 527	smsm_change_state(SMSM_APPS_DEM, SLAVE_TIME_POLL | SLAVE_TIME_INIT,
 528		SLAVE_TIME_REQUEST);
 529
 530	time_start(data);
 531	while (!((state = smsm_get_state(SMSM_TIME_MASTER_DEM)) &
 532		MASTER_TIME_PENDING)) {
 533		if (time_expired(data)) {
 534			printk(KERN_EMERG "get_smem_clock: timeout 2 still "
 535				"invalid state %x\n", state);
 536			msm_timer_sync_timeout();
 537		}
 538	}
 539
 540	smsm_change_state(SMSM_APPS_DEM, SLAVE_TIME_REQUEST, SLAVE_TIME_POLL);
 541
 542	time_start(data);
 543	do {
 544		smem_clock_val = *smem_clock;
 545	} while (smem_clock_val == 0 && !time_expired(data));
 546
 547	state = smsm_get_state(SMSM_TIME_MASTER_DEM);
 548
 549	if (smem_clock_val) {
 550		if (update != NULL)
 551			update(data, smem_clock_val, SCLK_HZ);
 552
 553		if (msm_timer_debug_mask & MSM_TIMER_DEBUG_SYNC)
 554			printk(KERN_INFO
 555				"get_smem_clock: state %x clock %u\n",
 556				state, smem_clock_val);
 557	} else {
 558		printk(KERN_EMERG
 559			"get_smem_clock: timeout state %x clock %u\n",
 560			state, smem_clock_val);
 561		msm_timer_sync_timeout();
 562	}
 563
 564	smsm_change_state(SMSM_APPS_DEM, SLAVE_TIME_REQUEST | SLAVE_TIME_POLL,
 565		SLAVE_TIME_INIT);
 566	return smem_clock_val;
 567}
 568#else /* CONFIG_MSM_N_WAY_SMSM */
 569static uint32_t msm_timer_do_sync_to_sclk(
 570	void (*time_start)(struct msm_timer_sync_data_t *data),
 571	bool (*time_expired)(struct msm_timer_sync_data_t *data),
 572	void (*update)(struct msm_timer_sync_data_t *, uint32_t, uint32_t),
 573	struct msm_timer_sync_data_t *data)
 574{
 575	uint32_t *smem_clock;
 576	uint32_t smem_clock_val;
 577	uint32_t last_state;
 578	uint32_t state;
 579
 580	smem_clock = smem_alloc(SMEM_SMEM_SLOW_CLOCK_VALUE,
 581				sizeof(uint32_t));
 582
 583	if (smem_clock == NULL) {
 584		printk(KERN_ERR "no smem clock\n");
 585		return 0;
 586	}
 587
 588	last_state = state = smsm_get_state(SMSM_MODEM_STATE);
 589	smem_clock_val = *smem_clock;
 590	if (smem_clock_val) {
 591		printk(KERN_INFO "get_smem_clock: invalid start state %x "
 592			"clock %u\n", state, smem_clock_val);
 593		smsm_change_state(SMSM_APPS_STATE,
 594				  SMSM_TIMEWAIT, SMSM_TIMEINIT);
 595
 596		time_start(data);
 597		while (*smem_clock != 0 && !time_expired(data))
 598			;
 599
 600		smem_clock_val = *smem_clock;
 601		if (smem_clock_val) {
 602			printk(KERN_EMERG "get_smem_clock: timeout still "
 603				"invalid state %x clock %u\n",
 604				state, smem_clock_val);
 605			msm_timer_sync_timeout();
 606		}
 607	}
 608
 609	time_start(data);
 610	smsm_change_state(SMSM_APPS_STATE, SMSM_TIMEINIT, SMSM_TIMEWAIT);
 611	do {
 612		smem_clock_val = *smem_clock;
 613		state = smsm_get_state(SMSM_MODEM_STATE);
 614		if (state != last_state) {
 615			last_state = state;
 616			if (msm_timer_debug_mask & MSM_TIMER_DEBUG_SYNC)
 617				printk(KERN_INFO
 618					"get_smem_clock: state %x clock %u\n",
 619					state, smem_clock_val);
 620		}
 621	} while (smem_clock_val == 0 && !time_expired(data));
 622
 623	if (smem_clock_val) {
 624		if (update != NULL)
 625			update(data, smem_clock_val, SCLK_HZ);
 626	} else {
 627		printk(KERN_EMERG
 628			"get_smem_clock: timeout state %x clock %u\n",
 629			state, smem_clock_val);
 630		msm_timer_sync_timeout();
 631	}
 632
 633	smsm_change_state(SMSM_APPS_STATE, SMSM_TIMEWAIT, SMSM_TIMEINIT);
 634	return smem_clock_val;
 635}
 636#endif /* CONFIG_MSM_N_WAY_SMSM */
 637
 638/*
 639 * Callback function that initializes the timeout value.
 640 */
 641static void msm_timer_sync_to_sclk_time_start(
 642	struct msm_timer_sync_data_t *data)
 643{
 644	/* approx 2 seconds */
 645	uint32_t delta = data->clock->freq << data->clock->shift << 1;
 646	data->timeout = msm_read_timer_count(data->clock, LOCAL_TIMER) + delta;
 647}
 648
 649/*
 650 * Callback function that checks the timeout.
 651 */
 652static bool msm_timer_sync_to_sclk_time_expired(
 653	struct msm_timer_sync_data_t *data)
 654{
 655	uint32_t delta = msm_read_timer_count(data->clock, LOCAL_TIMER) -
 656		data->timeout;
 657	return ((int32_t) delta) > 0;
 658}
 659
 660/*
 661 * Callback function that updates local clock from the specified source clock
 662 * value and frequency.
 663 */
 664static void msm_timer_sync_update(struct msm_timer_sync_data_t *data,
 665	uint32_t src_clk_val, uint32_t src_clk_freq)
 666{
 667	struct msm_clock *dst_clk = data->clock;
 668	struct msm_clock_percpu_data *dst_clk_state =
 669		&__get_cpu_var(msm_clocks_percpu)[dst_clk->index];
 670	uint32_t dst_clk_val = msm_read_timer_count(dst_clk, LOCAL_TIMER);
 671	uint32_t new_offset;
 672
 673	if ((dst_clk->freq << dst_clk->shift) == src_clk_freq) {
 674		new_offset = src_clk_val - dst_clk_val;
 675	} else {
 676		uint64_t temp;
 677
 678		/* separate multiplication and division steps to reduce
 679		   rounding error */
 680		temp = src_clk_val;
 681		temp *= dst_clk->freq << dst_clk->shift;
 682		do_div(temp, src_clk_freq);
 683
 684		new_offset = (uint32_t)(temp) - dst_clk_val;
 685	}
 686
 687	if (dst_clk_state->sleep_offset + dst_clk_state->non_sleep_offset !=
 688	    new_offset) {
 689		if (data->exit_sleep)
 690			dst_clk_state->sleep_offset =
 691				new_offset - dst_clk_state->non_sleep_offset;
 692		else
 693			dst_clk_state->non_sleep_offset =
 694				new_offset - dst_clk_state->sleep_offset;
 695
 696		if (msm_timer_debug_mask & MSM_TIMER_DEBUG_SYNC)
 697			printk(KERN_INFO "sync clock %s: "
 698				"src %u, new offset %u + %u\n",
 699				dst_clk->clocksource.name, src_clk_val,
 700				dst_clk_state->sleep_offset,
 701				dst_clk_state->non_sleep_offset);
 702	}
 703}
 704
 705/*
 706 * Synchronize GPT clock with sclk.
 707 */
 708static void msm_timer_sync_gpt_to_sclk(int exit_sleep)
 709{
 710	struct msm_clock *gpt_clk = &msm_clocks[MSM_CLOCK_GPT];
 711	struct msm_clock_percpu_data *gpt_clk_state =
 712		&__get_cpu_var(msm_clocks_percpu)[MSM_CLOCK_GPT];
 713	struct msm_timer_sync_data_t data;
 714	uint32_t ret;
 715
 716	if (gpt_clk_state->in_sync)
 717		return;
 718
 719	data.clock = gpt_clk;
 720	data.timeout = 0;
 721	data.exit_sleep = exit_sleep;
 722
 723	ret = msm_timer_do_sync_to_sclk(
 724		msm_timer_sync_to_sclk_time_start,
 725		msm_timer_sync_to_sclk_time_expired,
 726		msm_timer_sync_update,
 727		&data);
 728
 729	if (ret)
 730		gpt_clk_state->in_sync = 1;
 731}
 732
 733/*
 734 * Synchronize clock with GPT clock.
 735 */
 736static void msm_timer_sync_to_gpt(struct msm_clock *clock, int exit_sleep)
 737{
 738	struct msm_clock *gpt_clk = &msm_clocks[MSM_CLOCK_GPT];
 739	struct msm_clock_percpu_data *gpt_clk_state =
 740		&__get_cpu_var(msm_clocks_percpu)[MSM_CLOCK_GPT];
 741	struct msm_clock_percpu_data *clock_state =
 742		&__get_cpu_var(msm_clocks_percpu)[clock->index];
 743	struct msm_timer_sync_data_t data;
 744	uint32_t gpt_clk_val;
 745	u64 gpt_period = (1ULL << 32) * HZ / GPT_HZ;
 746	u64 now = get_jiffies_64();
 747
 748	BUG_ON(clock == gpt_clk);
 749
 750	if (clock_state->in_sync &&
 751		(now - clock_state->last_sync_jiffies < (gpt_period >> 1)))
 752		return;
 753
 754	gpt_clk_val = msm_read_timer_count(gpt_clk, LOCAL_TIMER)
 755		+ gpt_clk_state->sleep_offset + gpt_clk_state->non_sleep_offset;
 756
 757	if (exit_sleep && gpt_clk_val < clock_state->last_sync_gpt)
 758		clock_state->non_sleep_offset -= clock->rollover_offset;
 759
 760	data.clock = clock;
 761	data.timeout = 0;
 762	data.exit_sleep = exit_sleep;
 763
 764	msm_timer_sync_update(&data, gpt_clk_val, GPT_HZ);
 765
 766	clock_state->in_sync = 1;
 767	clock_state->last_sync_gpt = gpt_clk_val;
 768	clock_state->last_sync_jiffies = now;
 769}
 770
 771static void msm_timer_reactivate_alarm(struct msm_clock *clock)
 772{
 773	struct msm_clock_percpu_data *clock_state =
 774		&__get_cpu_var(msm_clocks_percpu)[clock->index];
 775	long alarm_delta = clock_state->alarm_vtime -
 776		clock_state->sleep_offset -
 777		msm_read_timer_count(clock, LOCAL_TIMER);
 778	alarm_delta >>= clock->shift;
 779	if (alarm_delta < (long)clock->write_delay + 4)
 780		alarm_delta = clock->write_delay + 4;
 781	while (msm_timer_set_next_event(alarm_delta, &clock->clockevent))
 782		;
 783}
 784
 785int64_t msm_timer_enter_idle(void)
 786{
 787	struct msm_clock *gpt_clk = &msm_clocks[MSM_CLOCK_GPT];
 788	struct msm_clock *clock = __get_cpu_var(msm_active_clock);
 789	struct msm_clock_percpu_data *clock_state =
 790		&__get_cpu_var(msm_clocks_percpu)[clock->index];
 791	uint32_t alarm;
 792	uint32_t count;
 793	int32_t delta;
 794
 795	BUG_ON(clock != &msm_clocks[MSM_CLOCK_GPT] &&
 796		clock != &msm_clocks[MSM_CLOCK_DGT]);
 797
 798	msm_timer_sync_gpt_to_sclk(0);
 799	if (clock != gpt_clk)
 800		msm_timer_sync_to_gpt(clock, 0);
 801
 802	count = msm_read_timer_count(clock, LOCAL_TIMER);
 803	if (clock_state->stopped++ == 0)
 804		clock_state->stopped_tick = count + clock_state->sleep_offset;
 805	alarm = clock_state->alarm;
 806	delta = alarm - count;
 807	if (delta <= -(int32_t)((clock->freq << clock->shift) >> 10)) {
 808		/* timer should have triggered 1ms ago */
 809		printk(KERN_ERR "msm_timer_enter_idle: timer late %d, "
 810			"reprogram it\n", delta);
 811		msm_timer_reactivate_alarm(clock);
 812	}
 813	if (delta <= 0)
 814		return 0;
 815	return clocksource_cyc2ns((alarm - count) >> clock->shift,
 816		      clock->clocksource.mult,
 817		      clock->clocksource.shift);
 818}
 819
 820void msm_timer_exit_idle(int low_power)
 821{
 822	struct msm_clock *gpt_clk = &msm_clocks[MSM_CLOCK_GPT];
 823	struct msm_clock *clock = __get_cpu_var(msm_active_clock);
 824	struct msm_clock_percpu_data *gpt_clk_state =
 825		&__get_cpu_var(msm_clocks_percpu)[MSM_CLOCK_GPT];
 826	struct msm_clock_percpu_data *clock_state =
 827		&__get_cpu_var(msm_clocks_percpu)[clock->index];
 828	uint32_t enabled;
 829
 830	BUG_ON(clock != &msm_clocks[MSM_CLOCK_GPT] &&
 831		clock != &msm_clocks[MSM_CLOCK_DGT]);
 832
 833	if (!low_power)
 834		goto exit_idle_exit;
 835
 836	enabled = readl(gpt_clk->regbase + TIMER_ENABLE) & TIMER_ENABLE_EN;
 837	if (!enabled)
 838		writel(TIMER_ENABLE_EN, gpt_clk->regbase + TIMER_ENABLE);
 839
 840#if defined(CONFIG_ARCH_MSM_SCORPION) || defined(CONFIG_ARCH_MSM_SCORPIONMP)
 841	gpt_clk_state->in_sync = 0;
 842#else
 843	gpt_clk_state->in_sync = gpt_clk_state->in_sync && enabled;
 844#endif
 845	msm_timer_sync_gpt_to_sclk(1);
 846
 847	if (clock == gpt_clk)
 848		goto exit_idle_alarm;
 849
 850	enabled = readl(clock->regbase + TIMER_ENABLE) & TIMER_ENABLE_EN;
 851	if (!enabled)
 852		writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
 853
 854#if defined(CONFIG_ARCH_MSM_SCORPION) || defined(CONFIG_ARCH_MSM_SCORPIONMP)
 855	clock_state->in_sync = 0;
 856#else
 857	clock_state->in_sync = clock_state->in_sync && enabled;
 858#endif
 859	msm_timer_sync_to_gpt(clock, 1);
 860
 861exit_idle_alarm:
 862	msm_timer_reactivate_alarm(clock);
 863
 864exit_idle_exit:
 865	clock_state->stopped--;
 866}
 867
 868/*
 869 * Callback function that initializes the timeout value.
 870 */
 871static void msm_timer_get_sclk_time_start(
 872	struct msm_timer_sync_data_t *data)
 873{
 874	data->timeout = 200000;
 875}
 876
 877/*
 878 * Callback function that checks the timeout.
 879 */
 880static bool msm_timer_get_sclk_time_expired(
 881	struct msm_timer_sync_data_t *data)
 882{
 883	udelay(10);
 884	return --data->timeout <= 0;
 885}
 886
 887/*
 888 * Retrieve the cycle count from the sclk and convert it into
 889 * nanoseconds.
 890 *
 891 * On exit, if period is not NULL, it contains the period of the
 892 * sclk in nanoseconds, i.e. how long the cycle count wraps around.
 893 *
 894 * Return value:
 895 *      0: the operation failed; period is not set either
 896 *      >0: time in nanoseconds
 897 */
 898int64_t msm_timer_get_sclk_time(int64_t *period)
 899{
 900	struct msm_timer_sync_data_t data;
 901	uint32_t clock_value;
 902	int64_t tmp;
 903
 904	memset(&data, 0, sizeof(data));
 905	clock_value = msm_timer_do_sync_to_sclk(
 906		msm_timer_get_sclk_time_start,
 907		msm_timer_get_sclk_time_expired,
 908		NULL,
 909		&data);
 910
 911	if (!clock_value)
 912		return 0;
 913
 914	if (period) {
 915		tmp = 1LL << 32;
 916		tmp = tmp * NSEC_PER_SEC / SCLK_HZ;
 917		*period = tmp;
 918	}
 919
 920	tmp = (int64_t)clock_value;
 921	tmp = tmp * NSEC_PER_SEC / SCLK_HZ;
 922	return tmp;
 923}
 924
 925int __init msm_timer_init_time_sync(void (*timeout)(void))
 926{
 927#if defined(CONFIG_MSM_N_WAY_SMSM)
 928	int ret = smsm_change_intr_mask(SMSM_TIME_MASTER_DEM, 0xFFFFFFFF, 0);
 929
 930	if (ret) {
 931		printk(KERN_ERR	"%s: failed to clear interrupt mask, %d\n",
 932			__func__, ret);
 933		return ret;
 934	}
 935
 936	smsm_change_state(SMSM_APPS_DEM,
 937		SLAVE_TIME_REQUEST | SLAVE_TIME_POLL, SLAVE_TIME_INIT);
 938#endif
 939
 940	BUG_ON(timeout == NULL);
 941	msm_timer_sync_timeout = timeout;
 942
 943	return 0;
 944}
 945
 946
 947unsigned long long sched_clock(void)
 948{
 949	static cycle_t last_ticks;
 950	static unsigned long long last_ns;
 951	static DEFINE_SPINLOCK(msm_timer_sched_clock_lock);
 952
 953	struct msm_clock *clock;
 954	struct clocksource *cs;
 955	cycle_t ticks, delta;
 956	unsigned long irq_flags;
 957
 958	clock = &msm_clocks[MSM_GLOBAL_TIMER];
 959	cs = &clock->clocksource;
 960
 961	ticks  = cs->read(cs);
 962
 963	spin_lock_irqsave(&msm_timer_sched_clock_lock, irq_flags);
 964	delta = (ticks - last_ticks) & cs->mask;
 965
 966	if (delta < cs->mask/2) {
 967		last_ticks += delta;
 968		last_ns += clocksource_cyc2ns(delta, cs->mult, cs->shift);
 969	}
 970
 971	ticks = last_ticks;
 972	spin_unlock_irqrestore(&msm_timer_sched_clock_lock, irq_flags);
 973
 974	return last_ns;
 975}
 976
 977#ifdef CONFIG_ARCH_MSM_SCORPIONMP
 978int read_current_timer(unsigned long *timer_val)
 979{
 980	struct msm_clock *dgt = &msm_clocks[MSM_CLOCK_DGT];
 981	*timer_val = msm_read_timer_count(dgt, GLOBAL_TIMER);
 982	return 0;
 983}
 984#endif
 985
 986static void __init msm_timer_init(void)
 987{
 988	int i;
 989	int res;
 990
 991#ifdef CONFIG_ARCH_MSM8X60
 992	writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
 993#endif
 994
 995	for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
 996		struct msm_clock *clock = &msm_clocks[i];
 997		struct clock_event_device *ce = &clock->clockevent;
 998		struct clocksource *cs = &clock->clocksource;
 999		writel(0, clock->regbase + TIMER_ENABLE);
1000		writel(1, clock->regbase + TIMER_CLEAR);
1001		writel(0, clock->regbase + TIMER_COUNT_VAL);
1002		writel(~0, clock->regbase + TIMER_MATCH_VAL);
1003
1004		if ((clock->freq << clock->shift) == GPT_HZ) {
1005			clock->rollover_offset = 0;
1006		} else {
1007			uint64_t temp;
1008
1009			temp = clock->freq << clock->shift;
1010			temp <<= 32;
1011			temp /= GPT_HZ;
1012
1013			clock->rollover_offset = (uint32_t) temp;
1014		}
1015
1016		ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
1017		/* allow at least 10 seconds to notice that the timer wrapped */
1018		ce->max_delta_ns =
1019			clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
1020		/* ticks gets rounded down by one */
1021		ce->min_delta_ns =
1022			clockevent_delta2ns(clock->write_delay + 4, ce);
1023		ce->cpumask = cpumask_of(0);
1024
1025		cs->mult = clocksource_hz2mult(clock->freq, cs->shift);
1026		res = clocksource_register(cs);
1027		if (res)
1028			printk(KERN_ERR "msm_timer_init: clocksource_register "
1029			       "failed for %s\n", cs->name);
1030
1031		res = setup_irq(clock->irq.irq, &clock->irq);
1032		if (res)
1033			printk(KERN_ERR "msm_timer_init: setup_irq "
1034			       "failed for %s\n", cs->name);
1035
1036		clockevents_register_device(ce);
1037	}
1038#ifdef CONFIG_ARCH_MSM_SCORPIONMP
1039	writel(1, msm_clocks[MSM_CLOCK_DGT].regbase + TIMER_ENABLE);
1040	set_delay_fn(read_current_timer_delay_loop);
1041#endif
1042}
1043
1044#ifdef CONFIG_SMP
1045void local_timer_setup(struct clock_event_device *evt)
1046{
1047	unsigned long flags;
1048	struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
1049
1050#ifdef CONFIG_ARCH_MSM8X60
1051	writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
1052#endif
1053
1054	if (!local_clock_event) {
1055		writel(0, clock->regbase  + TIMER_ENABLE);
1056		writel(1, clock->regbase + TIMER_CLEAR);
1057		writel(0, clock->regbase + TIMER_COUNT_VAL);
1058		writel(~0, clock->regbase + TIMER_MATCH_VAL);
1059		__get_cpu_var(msm_clocks_percpu)[clock->index].alarm = ~0;
1060	}
1061	evt->irq = clock->irq.irq;
1062	evt->name = "local_timer";
1063	evt->features = CLOCK_EVT_FEAT_ONESHOT;
1064	evt->rating = clock->clockevent.rating;
1065	evt->set_mode = msm_timer_set_mode;
1066	evt->set_next_event = msm_timer_set_next_event;
1067	evt->shift = clock->clockevent.shift;
1068	evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift);
1069	evt->max_delta_ns =
1070		clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
1071	evt->min_delta_ns = clockevent_delta2ns(clock->write_delay + 4, evt);
1072	evt->cpumask = cpumask_of(smp_processor_id());
1073
1074	local_clock_event = evt;
1075
1076	local_irq_save(flags);
1077	gic_clear_spi_pending(clock->irq.irq);
1078	get_irq_chip(clock->irq.irq)->unmask(clock->irq.irq);
1079	local_irq_restore(flags);
1080
1081	clockevents_register_device(evt);
1082}
1083
1084int local_timer_ack(void)
1085{
1086	return 1;
1087}
1088#endif
1089
1090#ifdef CONFIG_HOTPLUG_CPU
1091void __cpuexit local_timer_stop(void)
1092{
1093	local_clock_event->set_mode(CLOCK_EVT_MODE_SHUTDOWN, local_clock_event);
1094	get_irq_chip(local_clock_event->irq)->mask(local_clock_event->irq);
1095	local_clock_event = NULL;
1096}
1097#endif
1098
1099struct sys_timer msm_timer = {
1100	.init = msm_timer_init
1101};