/arch/arm/mach-msm/timer.c

https://bitbucket.org/sammyz/iscream_thunderc-2.6.35-rebase · C · 1101 lines · 875 code · 149 blank · 77 comment · 121 complexity · dc426bf05f38ddede69a655a793e823c MD5 · raw file

  1. /*
  2. * Copyright (C) 2007 Google, Inc.
  3. * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
  4. *
  5. * This software is licensed under the terms of the GNU General Public
  6. * License version 2, as published by the Free Software Foundation, and
  7. * may be copied, distributed, and modified under those terms.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. */
  15. #include <linux/init.h>
  16. #include <linux/time.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/irq.h>
  19. #include <linux/clk.h>
  20. #include <linux/clockchips.h>
  21. #include <linux/delay.h>
  22. #include <linux/io.h>
  23. #include <linux/percpu.h>
  24. #include <asm/mach/time.h>
  25. #include <mach/msm_iomap.h>
  26. #include <mach/irqs.h>
  27. #if defined(CONFIG_MSM_SMD)
  28. #include "smd_private.h"
  29. #endif
  30. #include "timer.h"
  31. #include "clock-8x60.h"
  32. enum {
  33. MSM_TIMER_DEBUG_SYNC = 1U << 0,
  34. };
  35. static int msm_timer_debug_mask;
  36. module_param_named(debug_mask, msm_timer_debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);
  37. #if defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60)
  38. #define MSM_GPT_BASE (MSM_TMR_BASE + 0x4)
  39. #define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
  40. #else
  41. #define MSM_GPT_BASE MSM_TMR_BASE
  42. #define MSM_DGT_BASE (MSM_TMR_BASE + 0x10)
  43. #endif
  44. #ifdef CONFIG_MSM7X00A_USE_GP_TIMER
  45. #define DG_TIMER_RATING 100
  46. #define MSM_GLOBAL_TIMER MSM_CLOCK_GPT
  47. #else
  48. #define DG_TIMER_RATING 300
  49. #define MSM_GLOBAL_TIMER MSM_CLOCK_DGT
  50. #endif
  51. #if defined(CONFIG_ARCH_MSM_ARM11)
  52. #define MSM_DGT_SHIFT (5)
  53. #else
  54. #define MSM_DGT_SHIFT (0)
  55. #endif
  56. #define TIMER_MATCH_VAL 0x0000
  57. #define TIMER_COUNT_VAL 0x0004
  58. #define TIMER_ENABLE 0x0008
  59. #define TIMER_CLEAR 0x000C
  60. #define DGT_CLK_CTL 0x0034
  61. enum {
  62. DGT_CLK_CTL_DIV_1 = 0,
  63. DGT_CLK_CTL_DIV_2 = 1,
  64. DGT_CLK_CTL_DIV_3 = 2,
  65. DGT_CLK_CTL_DIV_4 = 3,
  66. };
  67. #define TIMER_ENABLE_EN 1
  68. #define TIMER_ENABLE_CLR_ON_MATCH_EN 2
  69. #define LOCAL_TIMER 0
  70. #define GLOBAL_TIMER 1
  71. /*
  72. * MSM_TMR_GLOBAL is added to the regbase of a timer to force the memory access
  73. * to come from the CPU0 region.
  74. */
  75. #ifdef MSM_TMR0_BASE
  76. #define MSM_TMR_GLOBAL (MSM_TMR0_BASE - MSM_TMR_BASE)
  77. #else
  78. #define MSM_TMR_GLOBAL 0
  79. #endif
  80. #if defined(CONFIG_MSM_DIRECT_SCLK_ACCESS)
  81. #define MPM_SCLK_COUNT_VAL 0x0024
  82. #endif
  83. #define NR_TIMERS ARRAY_SIZE(msm_clocks)
  84. #if defined(CONFIG_ARCH_QSD8X50)
  85. #define DGT_HZ 4800000 /* Uses TCXO/4 (19.2 MHz / 4) */
  86. #elif defined(CONFIG_ARCH_MSM7X30)
  87. #define DGT_HZ 6144000 /* Uses LPXO/4 (24.576 MHz / 4) */
  88. #elif defined(CONFIG_ARCH_MSM8X60)
  89. /* Uses PXO/4 (24.576 MHz / 4) on V1, (27 MHz / 4) on V2 */
  90. #define DGT_HZ 6750000
  91. #else
  92. #define DGT_HZ 19200000 /* Uses TCXO (19.2 MHz) */
  93. #endif
  94. #define GPT_HZ 32768
  95. #define SCLK_HZ 32768
  96. #if defined(CONFIG_MSM_N_WAY_SMSM)
  97. /* Time Master State Bits */
  98. #define MASTER_BITS_PER_CPU 1
  99. #define MASTER_TIME_PENDING \
  100. (0x01UL << (MASTER_BITS_PER_CPU * SMSM_APPS_STATE))
  101. /* Time Slave State Bits */
  102. #define SLAVE_TIME_REQUEST 0x0400
  103. #define SLAVE_TIME_POLL 0x0800
  104. #define SLAVE_TIME_INIT 0x1000
  105. #endif
  106. static irqreturn_t msm_timer_interrupt(int irq, void *dev_id);
  107. static cycle_t msm_gpt_read(struct clocksource *cs);
  108. static cycle_t msm_dgt_read(struct clocksource *cs);
  109. static void msm_timer_set_mode(enum clock_event_mode mode,
  110. struct clock_event_device *evt);
  111. static int msm_timer_set_next_event(unsigned long cycles,
  112. struct clock_event_device *evt);
  113. enum {
  114. MSM_CLOCK_FLAGS_UNSTABLE_COUNT = 1U << 0,
  115. MSM_CLOCK_FLAGS_ODD_MATCH_WRITE = 1U << 1,
  116. MSM_CLOCK_FLAGS_DELAYED_WRITE_POST = 1U << 2,
  117. };
  118. struct msm_clock {
  119. struct clock_event_device clockevent;
  120. struct clocksource clocksource;
  121. struct irqaction irq;
  122. void __iomem *regbase;
  123. uint32_t freq;
  124. uint32_t shift;
  125. uint32_t flags;
  126. uint32_t write_delay;
  127. uint32_t rollover_offset;
  128. uint32_t index;
  129. };
  130. enum {
  131. MSM_CLOCK_GPT,
  132. MSM_CLOCK_DGT,
  133. };
  134. struct msm_clock_percpu_data {
  135. uint32_t last_set;
  136. uint32_t sleep_offset;
  137. uint32_t alarm_vtime;
  138. uint32_t alarm;
  139. uint32_t non_sleep_offset;
  140. uint32_t in_sync;
  141. cycle_t stopped_tick;
  142. int stopped;
  143. uint32_t last_sync_gpt;
  144. u64 last_sync_jiffies;
  145. };
  146. struct msm_timer_sync_data_t {
  147. struct msm_clock *clock;
  148. uint32_t timeout;
  149. int exit_sleep;
  150. };
  151. static struct msm_clock msm_clocks[] = {
  152. [MSM_CLOCK_GPT] = {
  153. .clockevent = {
  154. .name = "gp_timer",
  155. .features = CLOCK_EVT_FEAT_ONESHOT,
  156. .shift = 32,
  157. .rating = 200,
  158. .set_next_event = msm_timer_set_next_event,
  159. .set_mode = msm_timer_set_mode,
  160. },
  161. .clocksource = {
  162. .name = "gp_timer",
  163. .rating = 200,
  164. .read = msm_gpt_read,
  165. .mask = CLOCKSOURCE_MASK(32),
  166. .shift = 17,
  167. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  168. },
  169. .irq = {
  170. .name = "gp_timer",
  171. .flags = IRQF_DISABLED | IRQF_TIMER |
  172. IRQF_TRIGGER_RISING,
  173. .handler = msm_timer_interrupt,
  174. .dev_id = &msm_clocks[0].clockevent,
  175. .irq = INT_GP_TIMER_EXP
  176. },
  177. .regbase = MSM_GPT_BASE,
  178. .freq = GPT_HZ,
  179. .index = MSM_CLOCK_GPT,
  180. .flags =
  181. MSM_CLOCK_FLAGS_UNSTABLE_COUNT |
  182. MSM_CLOCK_FLAGS_ODD_MATCH_WRITE |
  183. MSM_CLOCK_FLAGS_DELAYED_WRITE_POST,
  184. .write_delay = 9,
  185. },
  186. [MSM_CLOCK_DGT] = {
  187. .clockevent = {
  188. .name = "dg_timer",
  189. .features = CLOCK_EVT_FEAT_ONESHOT,
  190. .shift = 32 + MSM_DGT_SHIFT,
  191. .rating = DG_TIMER_RATING,
  192. .set_next_event = msm_timer_set_next_event,
  193. .set_mode = msm_timer_set_mode,
  194. },
  195. .clocksource = {
  196. .name = "dg_timer",
  197. .rating = DG_TIMER_RATING,
  198. .read = msm_dgt_read,
  199. .mask = CLOCKSOURCE_MASK((32-MSM_DGT_SHIFT)),
  200. .shift = 24 - MSM_DGT_SHIFT,
  201. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  202. },
  203. .irq = {
  204. .name = "dg_timer",
  205. .flags = IRQF_DISABLED | IRQF_TIMER |
  206. IRQF_TRIGGER_RISING,
  207. .handler = msm_timer_interrupt,
  208. .dev_id = &msm_clocks[1].clockevent,
  209. .irq = INT_DEBUG_TIMER_EXP
  210. },
  211. .regbase = MSM_DGT_BASE,
  212. .freq = DGT_HZ >> MSM_DGT_SHIFT,
  213. .index = MSM_CLOCK_DGT,
  214. .shift = MSM_DGT_SHIFT,
  215. .write_delay = 2,
  216. }
  217. };
  218. static struct clock_event_device *local_clock_event;
  219. static DEFINE_PER_CPU(struct msm_clock_percpu_data[NR_TIMERS],
  220. msm_clocks_percpu);
  221. static DEFINE_PER_CPU(struct msm_clock *, msm_active_clock);
  222. static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
  223. {
  224. struct clock_event_device *evt = dev_id;
  225. if (smp_processor_id() != 0)
  226. evt = local_clock_event;
  227. if (evt->event_handler == NULL)
  228. return IRQ_HANDLED;
  229. evt->event_handler(evt);
  230. return IRQ_HANDLED;
  231. }
  232. static uint32_t msm_read_timer_count(struct msm_clock *clock, int global)
  233. {
  234. uint32_t t1, t2;
  235. int loop_count = 0;
  236. if (global)
  237. t1 = readl(clock->regbase + TIMER_COUNT_VAL + MSM_TMR_GLOBAL);
  238. else
  239. t1 = readl(clock->regbase + TIMER_COUNT_VAL);
  240. if (!(clock->flags & MSM_CLOCK_FLAGS_UNSTABLE_COUNT))
  241. return t1;
  242. while (1) {
  243. if (global)
  244. t2 = readl(clock->regbase + TIMER_COUNT_VAL +
  245. MSM_TMR_GLOBAL);
  246. else
  247. t2 = readl(clock->regbase + TIMER_COUNT_VAL);
  248. if (t1 == t2)
  249. return t1;
  250. if (loop_count++ > 10) {
  251. printk(KERN_ERR "msm_read_timer_count timer %s did not"
  252. "stabilize %u != %u\n", clock->clockevent.name,
  253. t2, t1);
  254. return t2;
  255. }
  256. t1 = t2;
  257. }
  258. }
  259. static cycle_t msm_gpt_read(struct clocksource *cs)
  260. {
  261. struct msm_clock *clock = &msm_clocks[MSM_CLOCK_GPT];
  262. struct msm_clock_percpu_data *clock_state =
  263. &per_cpu(msm_clocks_percpu, 0)[MSM_CLOCK_GPT];
  264. if (clock_state->stopped)
  265. return clock_state->stopped_tick;
  266. return msm_read_timer_count(clock, GLOBAL_TIMER) +
  267. clock_state->sleep_offset;
  268. }
  269. static cycle_t msm_dgt_read(struct clocksource *cs)
  270. {
  271. struct msm_clock *clock = &msm_clocks[MSM_CLOCK_DGT];
  272. struct msm_clock_percpu_data *clock_state =
  273. &per_cpu(msm_clocks_percpu, 0)[MSM_CLOCK_DGT];
  274. if (clock_state->stopped)
  275. return clock_state->stopped_tick >> MSM_DGT_SHIFT;
  276. return (msm_read_timer_count(clock, GLOBAL_TIMER) +
  277. clock_state->sleep_offset) >> MSM_DGT_SHIFT;
  278. }
  279. #ifdef CONFIG_SMP
  280. static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt)
  281. {
  282. int i;
  283. for (i = 0; i < NR_TIMERS; i++)
  284. if (evt == &(msm_clocks[i].clockevent))
  285. return &msm_clocks[i];
  286. return &msm_clocks[MSM_GLOBAL_TIMER];
  287. }
  288. #endif
  289. static int msm_timer_set_next_event(unsigned long cycles,
  290. struct clock_event_device *evt)
  291. {
  292. int i;
  293. struct msm_clock *clock;
  294. struct msm_clock_percpu_data *clock_state;
  295. uint32_t now;
  296. uint32_t alarm;
  297. int late;
  298. #ifdef CONFIG_SMP
  299. clock = clockevent_to_clock(evt);
  300. #else
  301. clock = container_of(evt, struct msm_clock, clockevent);
  302. #endif
  303. clock_state = &__get_cpu_var(msm_clocks_percpu)[clock->index];
  304. if (clock_state->stopped)
  305. return 0;
  306. now = msm_read_timer_count(clock, LOCAL_TIMER);
  307. alarm = now + (cycles << clock->shift);
  308. if (clock->flags & MSM_CLOCK_FLAGS_ODD_MATCH_WRITE)
  309. while (now == clock_state->last_set)
  310. now = msm_read_timer_count(clock, LOCAL_TIMER);
  311. clock_state->alarm = alarm;
  312. writel(alarm, clock->regbase + TIMER_MATCH_VAL);
  313. if (clock->flags & MSM_CLOCK_FLAGS_DELAYED_WRITE_POST) {
  314. /* read the counter four extra times to make sure write posts
  315. before reading the time */
  316. for (i = 0; i < 4; i++)
  317. readl(clock->regbase + TIMER_COUNT_VAL);
  318. }
  319. now = msm_read_timer_count(clock, LOCAL_TIMER);
  320. clock_state->last_set = now;
  321. clock_state->alarm_vtime = alarm + clock_state->sleep_offset;
  322. late = now - alarm;
  323. if (late >= (int)(-clock->write_delay << clock->shift) && late < DGT_HZ*5) {
  324. static int print_limit = 10;
  325. if (print_limit > 0) {
  326. print_limit--;
  327. printk(KERN_NOTICE "msm_timer_set_next_event(%lu) "
  328. "clock %s, alarm already expired, now %x, "
  329. "alarm %x, late %d%s\n",
  330. cycles, clock->clockevent.name, now, alarm, late,
  331. print_limit ? "" : " stop printing");
  332. }
  333. return -ETIME;
  334. }
  335. return 0;
  336. }
  337. static void msm_timer_set_mode(enum clock_event_mode mode,
  338. struct clock_event_device *evt)
  339. {
  340. struct msm_clock *clock;
  341. struct msm_clock_percpu_data *clock_state, *gpt_state;
  342. unsigned long irq_flags;
  343. #ifdef CONFIG_SMP
  344. clock = clockevent_to_clock(evt);
  345. #else
  346. clock = container_of(evt, struct msm_clock, clockevent);
  347. #endif
  348. clock_state = &__get_cpu_var(msm_clocks_percpu)[clock->index];
  349. gpt_state = &__get_cpu_var(msm_clocks_percpu)[MSM_CLOCK_GPT];
  350. local_irq_save(irq_flags);
  351. switch (mode) {
  352. case CLOCK_EVT_MODE_RESUME:
  353. case CLOCK_EVT_MODE_PERIODIC:
  354. break;
  355. case CLOCK_EVT_MODE_ONESHOT:
  356. clock_state->stopped = 0;
  357. clock_state->sleep_offset =
  358. -msm_read_timer_count(clock, LOCAL_TIMER) +
  359. clock_state->stopped_tick;
  360. get_cpu_var(msm_active_clock) = clock;
  361. put_cpu_var(msm_active_clock);
  362. writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
  363. if (clock != &msm_clocks[MSM_CLOCK_GPT])
  364. writel(TIMER_ENABLE_EN,
  365. msm_clocks[MSM_CLOCK_GPT].regbase +
  366. TIMER_ENABLE);
  367. break;
  368. case CLOCK_EVT_MODE_UNUSED:
  369. case CLOCK_EVT_MODE_SHUTDOWN:
  370. get_cpu_var(msm_active_clock) = NULL;
  371. put_cpu_var(msm_active_clock);
  372. clock_state->in_sync = 0;
  373. clock_state->stopped = 1;
  374. clock_state->stopped_tick =
  375. msm_read_timer_count(clock, LOCAL_TIMER) +
  376. clock_state->sleep_offset;
  377. writel(0, clock->regbase + TIMER_MATCH_VAL);
  378. #ifdef CONFIG_ARCH_MSM_SCORPIONMP
  379. if (clock != &msm_clocks[MSM_CLOCK_DGT] || smp_processor_id())
  380. #endif
  381. writel(0, clock->regbase + TIMER_ENABLE);
  382. if (clock != &msm_clocks[MSM_CLOCK_GPT]) {
  383. gpt_state->in_sync = 0;
  384. writel(0, msm_clocks[MSM_CLOCK_GPT].regbase +
  385. TIMER_ENABLE);
  386. }
  387. break;
  388. }
  389. local_irq_restore(irq_flags);
  390. }
  391. /*
  392. * Retrieve the cycle count from sclk and optionally synchronize local clock
  393. * with the sclk value.
  394. *
  395. * time_start and time_expired are callbacks that must be specified. The
  396. * protocol uses them to detect timeout. The update callback is optional.
  397. * If not NULL, update will be called so that it can update local clock.
  398. *
  399. * The function does not use the argument data directly; it passes data to
  400. * the callbacks.
  401. *
  402. * Return value:
  403. * 0: the operation failed
  404. * >0: the slow clock value after time-sync
  405. */
  406. static void (*msm_timer_sync_timeout)(void);
  407. #if defined(CONFIG_MSM_DIRECT_SCLK_ACCESS)
  408. static uint32_t msm_timer_do_sync_to_sclk(
  409. void (*time_start)(struct msm_timer_sync_data_t *data),
  410. bool (*time_expired)(struct msm_timer_sync_data_t *data),
  411. void (*update)(struct msm_timer_sync_data_t *, uint32_t, uint32_t),
  412. struct msm_timer_sync_data_t *data)
  413. {
  414. uint32_t t1, t2;
  415. int loop_count = 10;
  416. int loop_zero_count = 3;
  417. int tmp = USEC_PER_SEC/SCLK_HZ/(loop_zero_count-1);
  418. while (loop_zero_count--) {
  419. t1 = readl(MSM_RPM_MPM_BASE + MPM_SCLK_COUNT_VAL);
  420. do {
  421. udelay(1);
  422. t2 = t1;
  423. t1 = readl(MSM_RPM_MPM_BASE + MPM_SCLK_COUNT_VAL);
  424. } while ((t2 != t1) && --loop_count);
  425. if (!loop_count) {
  426. printk(KERN_EMERG "SCLK did not stabilize\n");
  427. return 0;
  428. }
  429. if (t1)
  430. break;
  431. udelay(tmp);
  432. }
  433. if (!loop_zero_count) {
  434. printk(KERN_EMERG "SCLK reads zero\n");
  435. return 0;
  436. }
  437. if (update != NULL)
  438. update(data, t1, SCLK_HZ);
  439. return t1;
  440. }
  441. #elif defined(CONFIG_MSM_N_WAY_SMSM)
  442. static uint32_t msm_timer_do_sync_to_sclk(
  443. void (*time_start)(struct msm_timer_sync_data_t *data),
  444. bool (*time_expired)(struct msm_timer_sync_data_t *data),
  445. void (*update)(struct msm_timer_sync_data_t *, uint32_t, uint32_t),
  446. struct msm_timer_sync_data_t *data)
  447. {
  448. uint32_t *smem_clock;
  449. uint32_t smem_clock_val;
  450. uint32_t state;
  451. smem_clock = smem_alloc(SMEM_SMEM_SLOW_CLOCK_VALUE, sizeof(uint32_t));
  452. if (smem_clock == NULL) {
  453. printk(KERN_ERR "no smem clock\n");
  454. return 0;
  455. }
  456. state = smsm_get_state(SMSM_MODEM_STATE);
  457. if ((state & SMSM_INIT) == 0) {
  458. printk(KERN_ERR "smsm not initialized\n");
  459. return 0;
  460. }
  461. time_start(data);
  462. while ((state = smsm_get_state(SMSM_TIME_MASTER_DEM)) &
  463. MASTER_TIME_PENDING) {
  464. if (time_expired(data)) {
  465. printk(KERN_EMERG "get_smem_clock: timeout 1 still "
  466. "invalid state %x\n", state);
  467. msm_timer_sync_timeout();
  468. }
  469. }
  470. smsm_change_state(SMSM_APPS_DEM, SLAVE_TIME_POLL | SLAVE_TIME_INIT,
  471. SLAVE_TIME_REQUEST);
  472. time_start(data);
  473. while (!((state = smsm_get_state(SMSM_TIME_MASTER_DEM)) &
  474. MASTER_TIME_PENDING)) {
  475. if (time_expired(data)) {
  476. printk(KERN_EMERG "get_smem_clock: timeout 2 still "
  477. "invalid state %x\n", state);
  478. msm_timer_sync_timeout();
  479. }
  480. }
  481. smsm_change_state(SMSM_APPS_DEM, SLAVE_TIME_REQUEST, SLAVE_TIME_POLL);
  482. time_start(data);
  483. do {
  484. smem_clock_val = *smem_clock;
  485. } while (smem_clock_val == 0 && !time_expired(data));
  486. state = smsm_get_state(SMSM_TIME_MASTER_DEM);
  487. if (smem_clock_val) {
  488. if (update != NULL)
  489. update(data, smem_clock_val, SCLK_HZ);
  490. if (msm_timer_debug_mask & MSM_TIMER_DEBUG_SYNC)
  491. printk(KERN_INFO
  492. "get_smem_clock: state %x clock %u\n",
  493. state, smem_clock_val);
  494. } else {
  495. printk(KERN_EMERG
  496. "get_smem_clock: timeout state %x clock %u\n",
  497. state, smem_clock_val);
  498. msm_timer_sync_timeout();
  499. }
  500. smsm_change_state(SMSM_APPS_DEM, SLAVE_TIME_REQUEST | SLAVE_TIME_POLL,
  501. SLAVE_TIME_INIT);
  502. return smem_clock_val;
  503. }
  504. #else /* CONFIG_MSM_N_WAY_SMSM */
  505. static uint32_t msm_timer_do_sync_to_sclk(
  506. void (*time_start)(struct msm_timer_sync_data_t *data),
  507. bool (*time_expired)(struct msm_timer_sync_data_t *data),
  508. void (*update)(struct msm_timer_sync_data_t *, uint32_t, uint32_t),
  509. struct msm_timer_sync_data_t *data)
  510. {
  511. uint32_t *smem_clock;
  512. uint32_t smem_clock_val;
  513. uint32_t last_state;
  514. uint32_t state;
  515. smem_clock = smem_alloc(SMEM_SMEM_SLOW_CLOCK_VALUE,
  516. sizeof(uint32_t));
  517. if (smem_clock == NULL) {
  518. printk(KERN_ERR "no smem clock\n");
  519. return 0;
  520. }
  521. last_state = state = smsm_get_state(SMSM_MODEM_STATE);
  522. smem_clock_val = *smem_clock;
  523. if (smem_clock_val) {
  524. printk(KERN_INFO "get_smem_clock: invalid start state %x "
  525. "clock %u\n", state, smem_clock_val);
  526. smsm_change_state(SMSM_APPS_STATE,
  527. SMSM_TIMEWAIT, SMSM_TIMEINIT);
  528. time_start(data);
  529. while (*smem_clock != 0 && !time_expired(data))
  530. ;
  531. smem_clock_val = *smem_clock;
  532. if (smem_clock_val) {
  533. printk(KERN_EMERG "get_smem_clock: timeout still "
  534. "invalid state %x clock %u\n",
  535. state, smem_clock_val);
  536. msm_timer_sync_timeout();
  537. }
  538. }
  539. time_start(data);
  540. smsm_change_state(SMSM_APPS_STATE, SMSM_TIMEINIT, SMSM_TIMEWAIT);
  541. do {
  542. smem_clock_val = *smem_clock;
  543. state = smsm_get_state(SMSM_MODEM_STATE);
  544. if (state != last_state) {
  545. last_state = state;
  546. if (msm_timer_debug_mask & MSM_TIMER_DEBUG_SYNC)
  547. printk(KERN_INFO
  548. "get_smem_clock: state %x clock %u\n",
  549. state, smem_clock_val);
  550. }
  551. } while (smem_clock_val == 0 && !time_expired(data));
  552. if (smem_clock_val) {
  553. if (update != NULL)
  554. update(data, smem_clock_val, SCLK_HZ);
  555. } else {
  556. printk(KERN_EMERG
  557. "get_smem_clock: timeout state %x clock %u\n",
  558. state, smem_clock_val);
  559. msm_timer_sync_timeout();
  560. }
  561. smsm_change_state(SMSM_APPS_STATE, SMSM_TIMEWAIT, SMSM_TIMEINIT);
  562. return smem_clock_val;
  563. }
  564. #endif /* CONFIG_MSM_N_WAY_SMSM */
  565. /*
  566. * Callback function that initializes the timeout value.
  567. */
  568. static void msm_timer_sync_to_sclk_time_start(
  569. struct msm_timer_sync_data_t *data)
  570. {
  571. /* approx 2 seconds */
  572. uint32_t delta = data->clock->freq << data->clock->shift << 1;
  573. data->timeout = msm_read_timer_count(data->clock, LOCAL_TIMER) + delta;
  574. }
  575. /*
  576. * Callback function that checks the timeout.
  577. */
  578. static bool msm_timer_sync_to_sclk_time_expired(
  579. struct msm_timer_sync_data_t *data)
  580. {
  581. uint32_t delta = msm_read_timer_count(data->clock, LOCAL_TIMER) -
  582. data->timeout;
  583. return ((int32_t) delta) > 0;
  584. }
  585. /*
  586. * Callback function that updates local clock from the specified source clock
  587. * value and frequency.
  588. */
  589. static void msm_timer_sync_update(struct msm_timer_sync_data_t *data,
  590. uint32_t src_clk_val, uint32_t src_clk_freq)
  591. {
  592. struct msm_clock *dst_clk = data->clock;
  593. struct msm_clock_percpu_data *dst_clk_state =
  594. &__get_cpu_var(msm_clocks_percpu)[dst_clk->index];
  595. uint32_t dst_clk_val = msm_read_timer_count(dst_clk, LOCAL_TIMER);
  596. uint32_t new_offset;
  597. if ((dst_clk->freq << dst_clk->shift) == src_clk_freq) {
  598. new_offset = src_clk_val - dst_clk_val;
  599. } else {
  600. uint64_t temp;
  601. /* separate multiplication and division steps to reduce
  602. rounding error */
  603. temp = src_clk_val;
  604. temp *= dst_clk->freq << dst_clk->shift;
  605. do_div(temp, src_clk_freq);
  606. new_offset = (uint32_t)(temp) - dst_clk_val;
  607. }
  608. if (dst_clk_state->sleep_offset + dst_clk_state->non_sleep_offset !=
  609. new_offset) {
  610. if (data->exit_sleep)
  611. dst_clk_state->sleep_offset =
  612. new_offset - dst_clk_state->non_sleep_offset;
  613. else
  614. dst_clk_state->non_sleep_offset =
  615. new_offset - dst_clk_state->sleep_offset;
  616. if (msm_timer_debug_mask & MSM_TIMER_DEBUG_SYNC)
  617. printk(KERN_INFO "sync clock %s: "
  618. "src %u, new offset %u + %u\n",
  619. dst_clk->clocksource.name, src_clk_val,
  620. dst_clk_state->sleep_offset,
  621. dst_clk_state->non_sleep_offset);
  622. }
  623. }
  624. /*
  625. * Synchronize GPT clock with sclk.
  626. */
  627. static void msm_timer_sync_gpt_to_sclk(int exit_sleep)
  628. {
  629. struct msm_clock *gpt_clk = &msm_clocks[MSM_CLOCK_GPT];
  630. struct msm_clock_percpu_data *gpt_clk_state =
  631. &__get_cpu_var(msm_clocks_percpu)[MSM_CLOCK_GPT];
  632. struct msm_timer_sync_data_t data;
  633. uint32_t ret;
  634. if (gpt_clk_state->in_sync)
  635. return;
  636. data.clock = gpt_clk;
  637. data.timeout = 0;
  638. data.exit_sleep = exit_sleep;
  639. ret = msm_timer_do_sync_to_sclk(
  640. msm_timer_sync_to_sclk_time_start,
  641. msm_timer_sync_to_sclk_time_expired,
  642. msm_timer_sync_update,
  643. &data);
  644. if (ret)
  645. gpt_clk_state->in_sync = 1;
  646. }
  647. /*
  648. * Synchronize clock with GPT clock.
  649. */
  650. static void msm_timer_sync_to_gpt(struct msm_clock *clock, int exit_sleep)
  651. {
  652. struct msm_clock *gpt_clk = &msm_clocks[MSM_CLOCK_GPT];
  653. struct msm_clock_percpu_data *gpt_clk_state =
  654. &__get_cpu_var(msm_clocks_percpu)[MSM_CLOCK_GPT];
  655. struct msm_clock_percpu_data *clock_state =
  656. &__get_cpu_var(msm_clocks_percpu)[clock->index];
  657. struct msm_timer_sync_data_t data;
  658. uint32_t gpt_clk_val;
  659. u64 gpt_period = (1ULL << 32) * HZ / GPT_HZ;
  660. u64 now = get_jiffies_64();
  661. BUG_ON(clock == gpt_clk);
  662. if (clock_state->in_sync &&
  663. (now - clock_state->last_sync_jiffies < (gpt_period >> 1)))
  664. return;
  665. gpt_clk_val = msm_read_timer_count(gpt_clk, LOCAL_TIMER)
  666. + gpt_clk_state->sleep_offset + gpt_clk_state->non_sleep_offset;
  667. if (exit_sleep && gpt_clk_val < clock_state->last_sync_gpt)
  668. clock_state->non_sleep_offset -= clock->rollover_offset;
  669. data.clock = clock;
  670. data.timeout = 0;
  671. data.exit_sleep = exit_sleep;
  672. msm_timer_sync_update(&data, gpt_clk_val, GPT_HZ);
  673. clock_state->in_sync = 1;
  674. clock_state->last_sync_gpt = gpt_clk_val;
  675. clock_state->last_sync_jiffies = now;
  676. }
  677. static void msm_timer_reactivate_alarm(struct msm_clock *clock)
  678. {
  679. struct msm_clock_percpu_data *clock_state =
  680. &__get_cpu_var(msm_clocks_percpu)[clock->index];
  681. long alarm_delta = clock_state->alarm_vtime -
  682. clock_state->sleep_offset -
  683. msm_read_timer_count(clock, LOCAL_TIMER);
  684. alarm_delta >>= clock->shift;
  685. if (alarm_delta < (long)clock->write_delay + 4)
  686. alarm_delta = clock->write_delay + 4;
  687. while (msm_timer_set_next_event(alarm_delta, &clock->clockevent))
  688. ;
  689. }
  690. int64_t msm_timer_enter_idle(void)
  691. {
  692. struct msm_clock *gpt_clk = &msm_clocks[MSM_CLOCK_GPT];
  693. struct msm_clock *clock = __get_cpu_var(msm_active_clock);
  694. struct msm_clock_percpu_data *clock_state =
  695. &__get_cpu_var(msm_clocks_percpu)[clock->index];
  696. uint32_t alarm;
  697. uint32_t count;
  698. int32_t delta;
  699. BUG_ON(clock != &msm_clocks[MSM_CLOCK_GPT] &&
  700. clock != &msm_clocks[MSM_CLOCK_DGT]);
  701. msm_timer_sync_gpt_to_sclk(0);
  702. if (clock != gpt_clk)
  703. msm_timer_sync_to_gpt(clock, 0);
  704. count = msm_read_timer_count(clock, LOCAL_TIMER);
  705. if (clock_state->stopped++ == 0)
  706. clock_state->stopped_tick = count + clock_state->sleep_offset;
  707. alarm = clock_state->alarm;
  708. delta = alarm - count;
  709. if (delta <= -(int32_t)((clock->freq << clock->shift) >> 10)) {
  710. /* timer should have triggered 1ms ago */
  711. printk(KERN_ERR "msm_timer_enter_idle: timer late %d, "
  712. "reprogram it\n", delta);
  713. msm_timer_reactivate_alarm(clock);
  714. }
  715. if (delta <= 0)
  716. return 0;
  717. return clocksource_cyc2ns((alarm - count) >> clock->shift,
  718. clock->clocksource.mult,
  719. clock->clocksource.shift);
  720. }
  721. void msm_timer_exit_idle(int low_power)
  722. {
  723. struct msm_clock *gpt_clk = &msm_clocks[MSM_CLOCK_GPT];
  724. struct msm_clock *clock = __get_cpu_var(msm_active_clock);
  725. struct msm_clock_percpu_data *gpt_clk_state =
  726. &__get_cpu_var(msm_clocks_percpu)[MSM_CLOCK_GPT];
  727. struct msm_clock_percpu_data *clock_state =
  728. &__get_cpu_var(msm_clocks_percpu)[clock->index];
  729. uint32_t enabled;
  730. BUG_ON(clock != &msm_clocks[MSM_CLOCK_GPT] &&
  731. clock != &msm_clocks[MSM_CLOCK_DGT]);
  732. if (!low_power)
  733. goto exit_idle_exit;
  734. enabled = readl(gpt_clk->regbase + TIMER_ENABLE) & TIMER_ENABLE_EN;
  735. if (!enabled)
  736. writel(TIMER_ENABLE_EN, gpt_clk->regbase + TIMER_ENABLE);
  737. #if defined(CONFIG_ARCH_MSM_SCORPION) || defined(CONFIG_ARCH_MSM_SCORPIONMP)
  738. gpt_clk_state->in_sync = 0;
  739. #else
  740. gpt_clk_state->in_sync = gpt_clk_state->in_sync && enabled;
  741. #endif
  742. msm_timer_sync_gpt_to_sclk(1);
  743. if (clock == gpt_clk)
  744. goto exit_idle_alarm;
  745. enabled = readl(clock->regbase + TIMER_ENABLE) & TIMER_ENABLE_EN;
  746. if (!enabled)
  747. writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
  748. #if defined(CONFIG_ARCH_MSM_SCORPION) || defined(CONFIG_ARCH_MSM_SCORPIONMP)
  749. clock_state->in_sync = 0;
  750. #else
  751. clock_state->in_sync = clock_state->in_sync && enabled;
  752. #endif
  753. msm_timer_sync_to_gpt(clock, 1);
  754. exit_idle_alarm:
  755. msm_timer_reactivate_alarm(clock);
  756. exit_idle_exit:
  757. clock_state->stopped--;
  758. }
  759. /*
  760. * Callback function that initializes the timeout value.
  761. */
  762. static void msm_timer_get_sclk_time_start(
  763. struct msm_timer_sync_data_t *data)
  764. {
  765. data->timeout = 200000;
  766. }
  767. /*
  768. * Callback function that checks the timeout.
  769. */
  770. static bool msm_timer_get_sclk_time_expired(
  771. struct msm_timer_sync_data_t *data)
  772. {
  773. udelay(10);
  774. return --data->timeout <= 0;
  775. }
  776. /*
  777. * Retrieve the cycle count from the sclk and convert it into
  778. * nanoseconds.
  779. *
  780. * On exit, if period is not NULL, it contains the period of the
  781. * sclk in nanoseconds, i.e. how long the cycle count wraps around.
  782. *
  783. * Return value:
  784. * 0: the operation failed; period is not set either
  785. * >0: time in nanoseconds
  786. */
  787. int64_t msm_timer_get_sclk_time(int64_t *period)
  788. {
  789. struct msm_timer_sync_data_t data;
  790. uint32_t clock_value;
  791. int64_t tmp;
  792. memset(&data, 0, sizeof(data));
  793. clock_value = msm_timer_do_sync_to_sclk(
  794. msm_timer_get_sclk_time_start,
  795. msm_timer_get_sclk_time_expired,
  796. NULL,
  797. &data);
  798. if (!clock_value)
  799. return 0;
  800. if (period) {
  801. tmp = 1LL << 32;
  802. tmp = tmp * NSEC_PER_SEC / SCLK_HZ;
  803. *period = tmp;
  804. }
  805. tmp = (int64_t)clock_value;
  806. tmp = tmp * NSEC_PER_SEC / SCLK_HZ;
  807. return tmp;
  808. }
  809. int __init msm_timer_init_time_sync(void (*timeout)(void))
  810. {
  811. #if defined(CONFIG_MSM_N_WAY_SMSM)
  812. int ret = smsm_change_intr_mask(SMSM_TIME_MASTER_DEM, 0xFFFFFFFF, 0);
  813. if (ret) {
  814. printk(KERN_ERR "%s: failed to clear interrupt mask, %d\n",
  815. __func__, ret);
  816. return ret;
  817. }
  818. smsm_change_state(SMSM_APPS_DEM,
  819. SLAVE_TIME_REQUEST | SLAVE_TIME_POLL, SLAVE_TIME_INIT);
  820. #endif
  821. BUG_ON(timeout == NULL);
  822. msm_timer_sync_timeout = timeout;
  823. return 0;
  824. }
  825. unsigned long long sched_clock(void)
  826. {
  827. static cycle_t last_ticks;
  828. static unsigned long long last_ns;
  829. static DEFINE_SPINLOCK(msm_timer_sched_clock_lock);
  830. struct msm_clock *clock;
  831. struct clocksource *cs;
  832. cycle_t ticks, delta;
  833. unsigned long irq_flags;
  834. clock = &msm_clocks[MSM_GLOBAL_TIMER];
  835. cs = &clock->clocksource;
  836. ticks = cs->read(cs);
  837. spin_lock_irqsave(&msm_timer_sched_clock_lock, irq_flags);
  838. delta = (ticks - last_ticks) & cs->mask;
  839. if (delta < cs->mask/2) {
  840. last_ticks += delta;
  841. last_ns += clocksource_cyc2ns(delta, cs->mult, cs->shift);
  842. }
  843. ticks = last_ticks;
  844. spin_unlock_irqrestore(&msm_timer_sched_clock_lock, irq_flags);
  845. return last_ns;
  846. }
  847. #ifdef CONFIG_ARCH_MSM_SCORPIONMP
  848. int read_current_timer(unsigned long *timer_val)
  849. {
  850. struct msm_clock *dgt = &msm_clocks[MSM_CLOCK_DGT];
  851. *timer_val = msm_read_timer_count(dgt, GLOBAL_TIMER);
  852. return 0;
  853. }
  854. #endif
  855. static void __init msm_timer_init(void)
  856. {
  857. int i;
  858. int res;
  859. #ifdef CONFIG_ARCH_MSM8X60
  860. writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
  861. #endif
  862. for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
  863. struct msm_clock *clock = &msm_clocks[i];
  864. struct clock_event_device *ce = &clock->clockevent;
  865. struct clocksource *cs = &clock->clocksource;
  866. writel(0, clock->regbase + TIMER_ENABLE);
  867. writel(1, clock->regbase + TIMER_CLEAR);
  868. writel(0, clock->regbase + TIMER_COUNT_VAL);
  869. writel(~0, clock->regbase + TIMER_MATCH_VAL);
  870. if ((clock->freq << clock->shift) == GPT_HZ) {
  871. clock->rollover_offset = 0;
  872. } else {
  873. uint64_t temp;
  874. temp = clock->freq << clock->shift;
  875. temp <<= 32;
  876. temp /= GPT_HZ;
  877. clock->rollover_offset = (uint32_t) temp;
  878. }
  879. ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
  880. /* allow at least 10 seconds to notice that the timer wrapped */
  881. ce->max_delta_ns =
  882. clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
  883. /* ticks gets rounded down by one */
  884. ce->min_delta_ns =
  885. clockevent_delta2ns(clock->write_delay + 4, ce);
  886. ce->cpumask = cpumask_of(0);
  887. cs->mult = clocksource_hz2mult(clock->freq, cs->shift);
  888. res = clocksource_register(cs);
  889. if (res)
  890. printk(KERN_ERR "msm_timer_init: clocksource_register "
  891. "failed for %s\n", cs->name);
  892. res = setup_irq(clock->irq.irq, &clock->irq);
  893. if (res)
  894. printk(KERN_ERR "msm_timer_init: setup_irq "
  895. "failed for %s\n", cs->name);
  896. clockevents_register_device(ce);
  897. }
  898. #ifdef CONFIG_ARCH_MSM_SCORPIONMP
  899. writel(1, msm_clocks[MSM_CLOCK_DGT].regbase + TIMER_ENABLE);
  900. set_delay_fn(read_current_timer_delay_loop);
  901. #endif
  902. }
  903. #ifdef CONFIG_SMP
  904. void local_timer_setup(struct clock_event_device *evt)
  905. {
  906. unsigned long flags;
  907. struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
  908. #ifdef CONFIG_ARCH_MSM8X60
  909. writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
  910. #endif
  911. if (!local_clock_event) {
  912. writel(0, clock->regbase + TIMER_ENABLE);
  913. writel(1, clock->regbase + TIMER_CLEAR);
  914. writel(0, clock->regbase + TIMER_COUNT_VAL);
  915. writel(~0, clock->regbase + TIMER_MATCH_VAL);
  916. __get_cpu_var(msm_clocks_percpu)[clock->index].alarm = ~0;
  917. }
  918. evt->irq = clock->irq.irq;
  919. evt->name = "local_timer";
  920. evt->features = CLOCK_EVT_FEAT_ONESHOT;
  921. evt->rating = clock->clockevent.rating;
  922. evt->set_mode = msm_timer_set_mode;
  923. evt->set_next_event = msm_timer_set_next_event;
  924. evt->shift = clock->clockevent.shift;
  925. evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift);
  926. evt->max_delta_ns =
  927. clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
  928. evt->min_delta_ns = clockevent_delta2ns(clock->write_delay + 4, evt);
  929. evt->cpumask = cpumask_of(smp_processor_id());
  930. local_clock_event = evt;
  931. local_irq_save(flags);
  932. gic_clear_spi_pending(clock->irq.irq);
  933. get_irq_chip(clock->irq.irq)->unmask(clock->irq.irq);
  934. local_irq_restore(flags);
  935. clockevents_register_device(evt);
  936. }
  937. int local_timer_ack(void)
  938. {
  939. return 1;
  940. }
  941. #endif
  942. #ifdef CONFIG_HOTPLUG_CPU
  943. void __cpuexit local_timer_stop(void)
  944. {
  945. local_clock_event->set_mode(CLOCK_EVT_MODE_SHUTDOWN, local_clock_event);
  946. get_irq_chip(local_clock_event->irq)->mask(local_clock_event->irq);
  947. local_clock_event = NULL;
  948. }
  949. #endif
  950. struct sys_timer msm_timer = {
  951. .init = msm_timer_init
  952. };