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/arch/arm/mach-msm/gpio.c

https://bitbucket.org/sammyz/iscream_thunderc-2.6.35-rebase
C | 623 lines | 525 code | 69 blank | 29 comment | 47 complexity | d8240debaabc0bd8ba12381a05e0ad54 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /* linux/arch/arm/mach-msm/gpio.c
  2. *
  3. * Copyright (C) 2007 Google, Inc.
  4. * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
  5. *
  6. * This software is licensed under the terms of the GNU General Public
  7. * License version 2, as published by the Free Software Foundation, and
  8. * may be copied, distributed, and modified under those terms.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. */
  16. #include <linux/bitops.h>
  17. #include <linux/gpio.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/io.h>
  20. #include <linux/irq.h>
  21. #include <linux/module.h>
  22. #include "gpio_hw.h"
  23. #include "gpiomux.h"
  24. #include "proc_comm.h"
  25. #include "smd_private.h"
  26. enum {
  27. GPIO_DEBUG_SLEEP = 1U << 0,
  28. };
  29. static int msm_gpio_debug_mask;
  30. module_param_named(debug_mask, msm_gpio_debug_mask, int,
  31. S_IRUGO | S_IWUSR | S_IWGRP);
  32. #define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0)
  33. #define MSM_GPIO_BANK(bank, first, last) \
  34. { \
  35. .regs = { \
  36. .out = MSM_GPIO_OUT_##bank, \
  37. .in = MSM_GPIO_IN_##bank, \
  38. .int_status = MSM_GPIO_INT_STATUS_##bank, \
  39. .int_clear = MSM_GPIO_INT_CLEAR_##bank, \
  40. .int_en = MSM_GPIO_INT_EN_##bank, \
  41. .int_edge = MSM_GPIO_INT_EDGE_##bank, \
  42. .int_pos = MSM_GPIO_INT_POS_##bank, \
  43. .oe = MSM_GPIO_OE_##bank, \
  44. }, \
  45. .chip = { \
  46. .base = (first), \
  47. .ngpio = (last) - (first) + 1, \
  48. .get = msm_gpio_get, \
  49. .set = msm_gpio_set, \
  50. .direction_input = msm_gpio_direction_input, \
  51. .direction_output = msm_gpio_direction_output, \
  52. .to_irq = msm_gpio_to_irq, \
  53. .request = msm_gpio_request, \
  54. .free = msm_gpio_free, \
  55. } \
  56. }
  57. #define MSM_GPIO_BROKEN_INT_CLEAR 1
  58. struct msm_gpio_regs {
  59. void __iomem *out;
  60. void __iomem *in;
  61. void __iomem *int_status;
  62. void __iomem *int_clear;
  63. void __iomem *int_en;
  64. void __iomem *int_edge;
  65. void __iomem *int_pos;
  66. void __iomem *oe;
  67. };
  68. struct msm_gpio_chip {
  69. spinlock_t lock;
  70. struct gpio_chip chip;
  71. struct msm_gpio_regs regs;
  72. #if MSM_GPIO_BROKEN_INT_CLEAR
  73. unsigned int_status_copy;
  74. #endif
  75. unsigned int both_edge_detect;
  76. unsigned int int_enable[2]; /* 0: awake, 1: sleep */
  77. };
  78. static int msm_gpio_write(struct msm_gpio_chip *msm_chip,
  79. unsigned offset, unsigned on)
  80. {
  81. unsigned mask = BIT(offset);
  82. unsigned val;
  83. val = readl(msm_chip->regs.out);
  84. if (on)
  85. writel(val | mask, msm_chip->regs.out);
  86. else
  87. writel(val & ~mask, msm_chip->regs.out);
  88. return 0;
  89. }
  90. static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip)
  91. {
  92. int loop_limit = 100;
  93. unsigned pol, val, val2, intstat;
  94. do {
  95. val = readl(msm_chip->regs.in);
  96. pol = readl(msm_chip->regs.int_pos);
  97. pol = (pol & ~msm_chip->both_edge_detect) |
  98. (~val & msm_chip->both_edge_detect);
  99. writel(pol, msm_chip->regs.int_pos);
  100. intstat = readl(msm_chip->regs.int_status);
  101. val2 = readl(msm_chip->regs.in);
  102. if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0)
  103. return;
  104. } while (loop_limit-- > 0);
  105. printk(KERN_ERR "msm_gpio_update_both_edge_detect, "
  106. "failed to reach stable state %x != %x\n", val, val2);
  107. }
  108. static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip,
  109. unsigned offset)
  110. {
  111. unsigned bit = BIT(offset);
  112. #if MSM_GPIO_BROKEN_INT_CLEAR
  113. /* Save interrupts that already triggered before we loose them. */
  114. /* Any interrupt that triggers between the read of int_status */
  115. /* and the write to int_clear will still be lost though. */
  116. msm_chip->int_status_copy |= readl(msm_chip->regs.int_status);
  117. msm_chip->int_status_copy &= ~bit;
  118. #endif
  119. writel(bit, msm_chip->regs.int_clear);
  120. msm_gpio_update_both_edge_detect(msm_chip);
  121. return 0;
  122. }
  123. static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  124. {
  125. struct msm_gpio_chip *msm_chip;
  126. unsigned long irq_flags;
  127. msm_chip = container_of(chip, struct msm_gpio_chip, chip);
  128. spin_lock_irqsave(&msm_chip->lock, irq_flags);
  129. writel(readl(msm_chip->regs.oe) & ~BIT(offset), msm_chip->regs.oe);
  130. spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
  131. return 0;
  132. }
  133. static int
  134. msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
  135. {
  136. struct msm_gpio_chip *msm_chip;
  137. unsigned long irq_flags;
  138. msm_chip = container_of(chip, struct msm_gpio_chip, chip);
  139. spin_lock_irqsave(&msm_chip->lock, irq_flags);
  140. msm_gpio_write(msm_chip, offset, value);
  141. writel(readl(msm_chip->regs.oe) | BIT(offset), msm_chip->regs.oe);
  142. spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
  143. return 0;
  144. }
  145. static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
  146. {
  147. struct msm_gpio_chip *msm_chip;
  148. msm_chip = container_of(chip, struct msm_gpio_chip, chip);
  149. return (readl(msm_chip->regs.in) & (1U << offset)) ? 1 : 0;
  150. }
  151. static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  152. {
  153. struct msm_gpio_chip *msm_chip;
  154. unsigned long irq_flags;
  155. msm_chip = container_of(chip, struct msm_gpio_chip, chip);
  156. spin_lock_irqsave(&msm_chip->lock, irq_flags);
  157. msm_gpio_write(msm_chip, offset, value);
  158. spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
  159. }
  160. static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
  161. {
  162. return MSM_GPIO_TO_INT(chip->base + offset);
  163. }
  164. #ifdef CONFIG_MSM_GPIOMUX
  165. static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
  166. {
  167. return msm_gpiomux_get(chip->base + offset);
  168. }
  169. static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
  170. {
  171. msm_gpiomux_put(chip->base + offset);
  172. }
  173. #else
  174. #define msm_gpio_request NULL
  175. #define msm_gpio_free NULL
  176. #endif
  177. struct msm_gpio_chip msm_gpio_chips[] = {
  178. #if defined(CONFIG_ARCH_MSM7X00A)
  179. MSM_GPIO_BANK(0, 0, 15),
  180. MSM_GPIO_BANK(1, 16, 42),
  181. MSM_GPIO_BANK(2, 43, 67),
  182. MSM_GPIO_BANK(3, 68, 94),
  183. MSM_GPIO_BANK(4, 95, 106),
  184. MSM_GPIO_BANK(5, 107, 121),
  185. #elif defined(CONFIG_ARCH_MSM7X25) || defined(CONFIG_ARCH_MSM7X27)
  186. MSM_GPIO_BANK(0, 0, 15),
  187. MSM_GPIO_BANK(1, 16, 42),
  188. MSM_GPIO_BANK(2, 43, 67),
  189. MSM_GPIO_BANK(3, 68, 94),
  190. MSM_GPIO_BANK(4, 95, 106),
  191. MSM_GPIO_BANK(5, 107, 132),
  192. #elif defined(CONFIG_ARCH_MSM7X30)
  193. MSM_GPIO_BANK(0, 0, 15),
  194. MSM_GPIO_BANK(1, 16, 43),
  195. MSM_GPIO_BANK(2, 44, 67),
  196. MSM_GPIO_BANK(3, 68, 94),
  197. MSM_GPIO_BANK(4, 95, 106),
  198. MSM_GPIO_BANK(5, 107, 133),
  199. MSM_GPIO_BANK(6, 134, 150),
  200. MSM_GPIO_BANK(7, 151, 181),
  201. #elif defined(CONFIG_ARCH_QSD8X50)
  202. MSM_GPIO_BANK(0, 0, 15),
  203. MSM_GPIO_BANK(1, 16, 42),
  204. MSM_GPIO_BANK(2, 43, 67),
  205. MSM_GPIO_BANK(3, 68, 94),
  206. MSM_GPIO_BANK(4, 95, 103),
  207. MSM_GPIO_BANK(5, 104, 121),
  208. MSM_GPIO_BANK(6, 122, 152),
  209. MSM_GPIO_BANK(7, 153, 164),
  210. #endif
  211. };
  212. static void msm_gpio_irq_ack(unsigned int irq)
  213. {
  214. unsigned long irq_flags;
  215. struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
  216. spin_lock_irqsave(&msm_chip->lock, irq_flags);
  217. msm_gpio_clear_detect_status(msm_chip,
  218. irq - gpio_to_irq(msm_chip->chip.base));
  219. spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
  220. }
  221. static void msm_gpio_irq_mask(unsigned int irq)
  222. {
  223. unsigned long irq_flags;
  224. struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
  225. unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
  226. spin_lock_irqsave(&msm_chip->lock, irq_flags);
  227. /* level triggered interrupts are also latched */
  228. if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
  229. msm_gpio_clear_detect_status(msm_chip, offset);
  230. msm_chip->int_enable[0] &= ~BIT(offset);
  231. writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
  232. spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
  233. }
  234. static void msm_gpio_irq_unmask(unsigned int irq)
  235. {
  236. unsigned long irq_flags;
  237. struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
  238. unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
  239. spin_lock_irqsave(&msm_chip->lock, irq_flags);
  240. /* level triggered interrupts are also latched */
  241. if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
  242. msm_gpio_clear_detect_status(msm_chip, offset);
  243. msm_chip->int_enable[0] |= BIT(offset);
  244. writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
  245. spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
  246. }
  247. static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
  248. {
  249. unsigned long irq_flags;
  250. struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
  251. unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
  252. spin_lock_irqsave(&msm_chip->lock, irq_flags);
  253. if (on)
  254. msm_chip->int_enable[1] |= BIT(offset);
  255. else
  256. msm_chip->int_enable[1] &= ~BIT(offset);
  257. spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
  258. return 0;
  259. }
  260. static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
  261. {
  262. unsigned long irq_flags;
  263. struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
  264. unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
  265. unsigned val, mask = BIT(offset);
  266. spin_lock_irqsave(&msm_chip->lock, irq_flags);
  267. val = readl(msm_chip->regs.int_edge);
  268. if (flow_type & IRQ_TYPE_EDGE_BOTH) {
  269. writel(val | mask, msm_chip->regs.int_edge);
  270. irq_desc[irq].handle_irq = handle_edge_irq;
  271. } else {
  272. writel(val & ~mask, msm_chip->regs.int_edge);
  273. irq_desc[irq].handle_irq = handle_level_irq;
  274. }
  275. if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
  276. msm_chip->both_edge_detect |= mask;
  277. msm_gpio_update_both_edge_detect(msm_chip);
  278. } else {
  279. msm_chip->both_edge_detect &= ~mask;
  280. val = readl(msm_chip->regs.int_pos);
  281. if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
  282. writel(val | mask, msm_chip->regs.int_pos);
  283. else
  284. writel(val & ~mask, msm_chip->regs.int_pos);
  285. }
  286. spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
  287. return 0;
  288. }
  289. static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
  290. {
  291. int i, j, mask;
  292. unsigned val;
  293. for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
  294. struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i];
  295. val = readl(msm_chip->regs.int_status);
  296. val &= msm_chip->int_enable[0];
  297. while (val) {
  298. mask = val & -val;
  299. j = fls(mask) - 1;
  300. /* printk("%s %08x %08x bit %d gpio %d irq %d\n",
  301. __func__, v, m, j, msm_chip->chip.start + j,
  302. FIRST_GPIO_IRQ + msm_chip->chip.start + j); */
  303. val &= ~mask;
  304. generic_handle_irq(FIRST_GPIO_IRQ +
  305. msm_chip->chip.base + j);
  306. }
  307. }
  308. desc->chip->ack(irq);
  309. }
  310. static struct irq_chip msm_gpio_irq_chip = {
  311. .name = "msmgpio",
  312. .ack = msm_gpio_irq_ack,
  313. .mask = msm_gpio_irq_mask,
  314. .unmask = msm_gpio_irq_unmask,
  315. .set_wake = msm_gpio_irq_set_wake,
  316. .set_type = msm_gpio_irq_set_type,
  317. };
  318. #define NUM_GPIO_SMEM_BANKS 6
  319. #define GPIO_SMEM_NUM_GROUPS 2
  320. #define GPIO_SMEM_MAX_PC_INTERRUPTS 8
  321. struct tramp_gpio_smem {
  322. uint16_t num_fired[GPIO_SMEM_NUM_GROUPS];
  323. uint16_t fired[GPIO_SMEM_NUM_GROUPS][GPIO_SMEM_MAX_PC_INTERRUPTS];
  324. uint32_t enabled[NUM_GPIO_SMEM_BANKS];
  325. uint32_t detection[NUM_GPIO_SMEM_BANKS];
  326. uint32_t polarity[NUM_GPIO_SMEM_BANKS];
  327. };
  328. static void msm_gpio_sleep_int(unsigned long arg)
  329. {
  330. int i, j;
  331. struct tramp_gpio_smem *smem_gpio;
  332. BUILD_BUG_ON(NR_GPIO_IRQS > NUM_GPIO_SMEM_BANKS * 32);
  333. smem_gpio = smem_alloc(SMEM_GPIO_INT, sizeof(*smem_gpio));
  334. if (smem_gpio == NULL)
  335. return;
  336. local_irq_disable();
  337. for (i = 0; i < GPIO_SMEM_NUM_GROUPS; i++) {
  338. int count = smem_gpio->num_fired[i];
  339. for (j = 0; j < count; j++) {
  340. /* TODO: Check mask */
  341. generic_handle_irq(
  342. MSM_GPIO_TO_INT(smem_gpio->fired[i][j]));
  343. }
  344. }
  345. local_irq_enable();
  346. }
  347. static DECLARE_TASKLET(msm_gpio_sleep_int_tasklet, msm_gpio_sleep_int, 0);
  348. void msm_gpio_enter_sleep(int from_idle)
  349. {
  350. int i;
  351. struct tramp_gpio_smem *smem_gpio;
  352. smem_gpio = smem_alloc(SMEM_GPIO_INT, sizeof(*smem_gpio));
  353. if (smem_gpio) {
  354. for (i = 0; i < ARRAY_SIZE(smem_gpio->enabled); i++) {
  355. smem_gpio->enabled[i] = 0;
  356. smem_gpio->detection[i] = 0;
  357. smem_gpio->polarity[i] = 0;
  358. }
  359. }
  360. for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
  361. writel(msm_gpio_chips[i].int_enable[!from_idle],
  362. msm_gpio_chips[i].regs.int_en);
  363. if (smem_gpio) {
  364. uint32_t tmp;
  365. int start, index, shiftl, shiftr;
  366. start = msm_gpio_chips[i].chip.base;
  367. index = start / 32;
  368. shiftl = start % 32;
  369. shiftr = 32 - shiftl;
  370. tmp = msm_gpio_chips[i].int_enable[!from_idle];
  371. smem_gpio->enabled[index] |= tmp << shiftl;
  372. smem_gpio->enabled[index+1] |= tmp >> shiftr;
  373. smem_gpio->detection[index] |=
  374. readl(msm_gpio_chips[i].regs.int_edge) <<
  375. shiftl;
  376. smem_gpio->detection[index+1] |=
  377. readl(msm_gpio_chips[i].regs.int_edge) >>
  378. shiftr;
  379. smem_gpio->polarity[index] |=
  380. readl(msm_gpio_chips[i].regs.int_pos) << shiftl;
  381. smem_gpio->polarity[index+1] |=
  382. readl(msm_gpio_chips[i].regs.int_pos) >> shiftr;
  383. }
  384. }
  385. if (smem_gpio) {
  386. if (msm_gpio_debug_mask & GPIO_DEBUG_SLEEP)
  387. for (i = 0; i < ARRAY_SIZE(smem_gpio->enabled); i++) {
  388. printk("msm_gpio_enter_sleep gpio %d-%d: enable"
  389. " %08x, edge %08x, polarity %08x\n",
  390. i * 32, i * 32 + 31,
  391. smem_gpio->enabled[i],
  392. smem_gpio->detection[i],
  393. smem_gpio->polarity[i]);
  394. }
  395. for (i = 0; i < GPIO_SMEM_NUM_GROUPS; i++)
  396. smem_gpio->num_fired[i] = 0;
  397. }
  398. }
  399. void msm_gpio_exit_sleep(void)
  400. {
  401. int i;
  402. struct tramp_gpio_smem *smem_gpio;
  403. smem_gpio = smem_alloc(SMEM_GPIO_INT, sizeof(*smem_gpio));
  404. for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
  405. writel(msm_gpio_chips[i].int_enable[0],
  406. msm_gpio_chips[i].regs.int_en);
  407. }
  408. if (smem_gpio && (smem_gpio->num_fired[0] || smem_gpio->num_fired[1])) {
  409. if (msm_gpio_debug_mask & GPIO_DEBUG_SLEEP)
  410. printk(KERN_INFO "gpio: fired %x %x\n",
  411. smem_gpio->num_fired[0], smem_gpio->num_fired[1]);
  412. tasklet_schedule(&msm_gpio_sleep_int_tasklet);
  413. }
  414. }
  415. static int __init msm_init_gpio(void)
  416. {
  417. int i, j = 0;
  418. for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) {
  419. if (i - FIRST_GPIO_IRQ >=
  420. msm_gpio_chips[j].chip.base +
  421. msm_gpio_chips[j].chip.ngpio)
  422. j++;
  423. set_irq_chip_data(i, &msm_gpio_chips[j]);
  424. set_irq_chip(i, &msm_gpio_irq_chip);
  425. set_irq_handler(i, handle_edge_irq);
  426. set_irq_flags(i, IRQF_VALID);
  427. }
  428. for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
  429. spin_lock_init(&msm_gpio_chips[i].lock);
  430. writel(0, msm_gpio_chips[i].regs.int_en);
  431. gpiochip_add(&msm_gpio_chips[i].chip);
  432. }
  433. set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
  434. set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
  435. set_irq_wake(INT_GPIO_GROUP1, 1);
  436. set_irq_wake(INT_GPIO_GROUP2, 2);
  437. return 0;
  438. }
  439. postcore_initcall(msm_init_gpio);
  440. int gpio_tlmm_config(unsigned config, unsigned disable)
  441. {
  442. return msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, &disable);
  443. }
  444. EXPORT_SYMBOL(gpio_tlmm_config);
  445. int msm_gpios_request_enable(const struct msm_gpio *table, int size)
  446. {
  447. int rc = msm_gpios_request(table, size);
  448. if (rc)
  449. return rc;
  450. rc = msm_gpios_enable(table, size);
  451. if (rc)
  452. msm_gpios_free(table, size);
  453. return rc;
  454. }
  455. EXPORT_SYMBOL(msm_gpios_request_enable);
  456. void msm_gpios_disable_free(const struct msm_gpio *table, int size)
  457. {
  458. msm_gpios_disable(table, size);
  459. msm_gpios_free(table, size);
  460. }
  461. EXPORT_SYMBOL(msm_gpios_disable_free);
  462. int msm_gpios_request(const struct msm_gpio *table, int size)
  463. {
  464. int rc;
  465. int i;
  466. const struct msm_gpio *g;
  467. for (i = 0; i < size; i++) {
  468. g = table + i;
  469. rc = gpio_request(GPIO_PIN(g->gpio_cfg), g->label);
  470. if (rc) {
  471. pr_err("gpio_request(%d) <%s> failed: %d\n",
  472. GPIO_PIN(g->gpio_cfg), g->label ?: "?", rc);
  473. goto err;
  474. }
  475. }
  476. return 0;
  477. err:
  478. msm_gpios_free(table, i);
  479. return rc;
  480. }
  481. EXPORT_SYMBOL(msm_gpios_request);
  482. void msm_gpios_free(const struct msm_gpio *table, int size)
  483. {
  484. int i;
  485. const struct msm_gpio *g;
  486. for (i = size-1; i >= 0; i--) {
  487. g = table + i;
  488. gpio_free(GPIO_PIN(g->gpio_cfg));
  489. }
  490. }
  491. EXPORT_SYMBOL(msm_gpios_free);
  492. int msm_gpios_enable(const struct msm_gpio *table, int size)
  493. {
  494. int rc;
  495. int i;
  496. const struct msm_gpio *g;
  497. for (i = 0; i < size; i++) {
  498. g = table + i;
  499. rc = gpio_tlmm_config(g->gpio_cfg, GPIO_CFG_ENABLE);
  500. if (rc) {
  501. pr_err("gpio_tlmm_config(0x%08x, GPIO_CFG_ENABLE)"
  502. " <%s> failed: %d\n",
  503. g->gpio_cfg, g->label ?: "?", rc);
  504. pr_err("pin %d func %d dir %d pull %d drvstr %d\n",
  505. GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg),
  506. GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg),
  507. GPIO_DRVSTR(g->gpio_cfg));
  508. goto err;
  509. }
  510. }
  511. return 0;
  512. err:
  513. msm_gpios_disable(table, i);
  514. return rc;
  515. }
  516. EXPORT_SYMBOL(msm_gpios_enable);
  517. int msm_gpios_disable(const struct msm_gpio *table, int size)
  518. {
  519. int rc = 0;
  520. int i;
  521. const struct msm_gpio *g;
  522. for (i = size-1; i >= 0; i--) {
  523. int tmp;
  524. g = table + i;
  525. tmp = gpio_tlmm_config(g->gpio_cfg, GPIO_CFG_DISABLE);
  526. if (tmp) {
  527. pr_err("gpio_tlmm_config(0x%08x, GPIO_CFG_DISABLE)"
  528. " <%s> failed: %d\n",
  529. g->gpio_cfg, g->label ?: "?", rc);
  530. pr_err("pin %d func %d dir %d pull %d drvstr %d\n",
  531. GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg),
  532. GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg),
  533. GPIO_DRVSTR(g->gpio_cfg));
  534. if (!rc)
  535. rc = tmp;
  536. }
  537. }
  538. return rc;
  539. }
  540. EXPORT_SYMBOL(msm_gpios_disable);
  541. /* Locate the GPIO_OUT register for the given GPIO and return its address
  542. * and the bit position of the gpio's bit within the register.
  543. *
  544. * This function is used by gpiomux-v1 in order to support output transitions.
  545. */
  546. void msm_gpio_find_out(const unsigned gpio, void __iomem **out,
  547. unsigned *offset)
  548. {
  549. struct msm_gpio_chip *msm_chip = msm_gpio_chips;
  550. while (gpio >= msm_chip->chip.base + msm_chip->chip.ngpio)
  551. ++msm_chip;
  552. *out = msm_chip->regs.out;
  553. *offset = gpio - msm_chip->chip.base;
  554. }