/arch/arm/mach-msm/clock-7x30.h

  1/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
  2 *
  3 * Redistribution and use in source and binary forms, with or without
  4 * modification, are permitted provided that the following conditions are
  5 * met:
  6 *     * Redistributions of source code must retain the above copyright
  7 *       notice, this list of conditions and the following disclaimer.
  8 *     * Redistributions in binary form must reproduce the above
  9 *       copyright notice, this list of conditions and the following
 10 *       disclaimer in the documentation and/or other materials provided
 11 *       with the distribution.
 12 *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
 13 *       contributors may be used to endorse or promote products derived
 14 *       from this software without specific prior written permission.
 15 *
 16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
 19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 27 *
 28 */
 29
 30#ifndef __ARCH_ARM_MACH_MSM_CLOCK_7X30_H
 31#define __ARCH_ARM_MACH_MSM_CLOCK_7X30_H
 32
 33enum {
 34	L_ADM_CLK,
 35	L_ADM_P_CLK,
 36	L_CE_CLK,
 37	L_I2C_CLK,
 38	L_I2C_2_CLK,
 39	L_QUP_I2C_CLK,
 40	L_UART1DM_CLK,
 41	L_UART1DM_P_CLK,
 42	L_UART2DM_CLK,
 43	L_UART2DM_P_CLK,
 44	L_EMDH_CLK,
 45	L_EMDH_P_CLK,
 46	L_PMDH_CLK,
 47	L_PMDH_P_CLK,
 48	L_GRP_2D_CLK,
 49	L_GRP_2D_P_CLK,
 50	L_GRP_3D_SRC_CLK,
 51	L_GRP_3D_CLK,
 52	L_GRP_3D_P_CLK,
 53	L_IMEM_CLK,
 54	L_SDC1_CLK,
 55	L_SDC1_P_CLK,
 56	L_SDC2_CLK,
 57	L_SDC2_P_CLK,
 58	L_SDC3_CLK,
 59	L_SDC3_P_CLK,
 60	L_SDC4_CLK,
 61	L_SDC4_P_CLK,
 62	L_MDP_CLK,
 63	L_MDP_P_CLK,
 64	L_MDP_LCDC_PCLK_CLK,
 65	L_MDP_LCDC_PAD_PCLK_CLK,
 66	L_MDP_VSYNC_CLK,
 67	L_MI2S_CODEC_RX_M_CLK,
 68	L_MI2S_CODEC_RX_S_CLK,
 69	L_MI2S_CODEC_TX_M_CLK,
 70	L_MI2S_CODEC_TX_S_CLK,
 71	L_MI2S_M_CLK,
 72	L_MI2S_S_CLK,
 73	L_LPA_CODEC_CLK,
 74	L_LPA_CORE_CLK,
 75	L_LPA_P_CLK,
 76	L_MIDI_CLK,
 77	L_MDC_CLK,
 78	L_ROTATOR_IMEM_CLK,
 79	L_ROTATOR_P_CLK,
 80	L_SDAC_M_CLK,
 81	L_SDAC_CLK,
 82	L_UART1_CLK,
 83	L_UART2_CLK,
 84	L_UART3_CLK,
 85	L_TV_CLK,
 86	L_TV_DAC_CLK,
 87	L_TV_ENC_CLK,
 88	L_HDMI_CLK,
 89	L_TSIF_REF_CLK,
 90	L_TSIF_P_CLK,
 91	L_USB_HS_SRC_CLK,
 92	L_USB_HS_CLK,
 93	L_USB_HS_CORE_CLK,
 94	L_USB_HS_P_CLK,
 95	L_USB_HS2_CLK,
 96	L_USB_HS2_CORE_CLK,
 97	L_USB_HS2_P_CLK,
 98	L_USB_HS3_CLK,
 99	L_USB_HS3_CORE_CLK,
100	L_USB_HS3_P_CLK,
101	L_VFE_CLK,
102	L_VFE_P_CLK,
103	L_VFE_MDC_CLK,
104	L_VFE_CAMIF_CLK,
105	L_CAMIF_PAD_P_CLK,
106	L_CAM_M_CLK,
107	L_JPEG_CLK,
108	L_JPEG_P_CLK,
109	L_VPE_CLK,
110	L_MFC_CLK,
111	L_MFC_DIV2_CLK,
112	L_MFC_P_CLK,
113	L_SPI_CLK,
114	L_SPI_P_CLK,
115	L_CSI0_CLK,
116	L_CSI0_VFE_CLK,
117	L_CSI0_P_CLK,
118	L_CSI1_CLK,
119	L_CSI1_VFE_CLK,
120	L_CSI1_P_CLK,
121	L_GLBL_ROOT_CLK,
122
123	L_AXI_LI_VG_CLK,
124	L_AXI_LI_GRP_CLK,
125	L_AXI_LI_JPEG_CLK,
126	L_AXI_GRP_2D_CLK,
127	L_AXI_MFC_CLK,
128	L_AXI_VPE_CLK,
129	L_AXI_LI_VFE_CLK,
130	L_AXI_LI_APPS_CLK,
131	L_AXI_MDP_CLK,
132	L_AXI_IMEM_CLK,
133	L_AXI_LI_ADSP_A_CLK,
134	L_AXI_ROTATOR_CLK,
135
136	L_NR_CLKS
137};
138
139enum clk_sources {
140	PLL_0 = 0,
141	PLL_1,
142	PLL_2,
143	PLL_3,
144	PLL_4,
145	PLL_5,
146	PLL_6,
147	AXI,
148	LPXO,
149	TCXO,
150	NUM_SRC
151};
152
153extern int internal_pwr_rail_ctl_auto(unsigned rail_id, bool enable);
154
155extern struct clk_ops soc_clk_ops_7x30;
156#define CLK_7X30(clk_name, clk_id, clk_dev, clk_flags) {	\
157	.con_id = clk_name, \
158	.dev_id = clk_dev, \
159	.clk = &(struct clk){ \
160		.id = L_##clk_id, \
161		.remote_id = P_##clk_id, \
162		.flags = clk_flags, \
163		.dbg_name = #clk_id, \
164	}, \
165	}
166
167#define CLK_7X30S(clk_name, l_id, r_id, clk_dev, clk_flags) {	\
168	.con_id = clk_name, \
169	.dev_id = clk_dev, \
170	.clk = &(struct clk){ \
171		.id = L_##l_id, \
172		.remote_id = P_##r_id, \
173		.flags = clk_flags, \
174		.dbg_name = #l_id, \
175	}, \
176	}
177
178#define CLK_7X30L(clk_name, l_id, clk_dev, clk_flags) {	\
179	.con_id = clk_name, \
180	.dev_id = clk_dev, \
181	.clk = &(struct clk){ \
182		.id = L_##l_id, \
183		.flags = clk_flags, \
184		.dbg_name = #l_id, \
185		.ops = &soc_clk_ops_7x30, \
186	}, \
187	}
188
189#endif