/arch/arm/mach-msm/board-sapphire.h

https://bitbucket.org/sammyz/iscream_thunderc-2.6.35-rebase · C++ Header · 224 lines · 141 code · 46 blank · 37 comment · 0 complexity · 09af0aa2b4e16abcc207e3462da91036 MD5 · raw file 

    

  1. /* linux/arch/arm/mach-msm/board-sapphire.h
    2. 

  2.  * Copyright (C) 2007-2009 HTC Corporation.
    3. 

  3.  * Author: Thomas Tsai <thomas_tsai@htc.com>
    4. 

  4.  *
    5. 

  5.  * This software is licensed under the terms of the GNU General Public
    6. 

  6.  * License version 2, as published by the Free Software Foundation, and
    7. 

  7.  * may be copied, distributed, and modified under those terms.
    8. 

  8.  *
    9. 

  9.  * This program is distributed in the hope that it will be useful,
    10. 

  10.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    11. 

  11.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    12. 

  12.  * GNU General Public License for more details.
    13. 

  13. */
    14. 

  14. #ifndef __ARCH_ARM_MACH_MSM_BOARD_SAPPHIRE_H
    15. 

  15. #define __ARCH_ARM_MACH_MSM_BOARD_SAPPHIRE_H
    16. 

  16. 

  17. #include <mach/board.h>
    18. 

  18. 

  19. #define MSM_SMI_BASE		0x00000000
    20. 

  20. #define MSM_SMI_SIZE		0x00800000
    21. 

  21. 

  22. #define MSM_EBI_BASE		0x10000000
    23. 

  23. #define MSM_EBI_SIZE		0x07100000
    24. 

  24. 

  25. #define MSM_PMEM_GPU0_BASE	0x00000000
    26. 

  26. #define MSM_PMEM_GPU0_SIZE	0x00700000
    27. 

  27. 

  28. #define SMI64_MSM_PMEM_MDP_BASE	0x15900000
    29. 

  29. #define SMI64_MSM_PMEM_MDP_SIZE	0x00800000
    30. 

  30. 

  31. #define SMI64_MSM_PMEM_ADSP_BASE	0x16100000
    32. 

  32. #define SMI64_MSM_PMEM_ADSP_SIZE	0x00800000
    33. 

  33. 

  34. #define SMI64_MSM_PMEM_CAMERA_BASE	0x15400000
    35. 

  35. #define SMI64_MSM_PMEM_CAMERA_SIZE	0x00500000
    36. 

  36. 

  37. #define SMI64_MSM_FB_BASE		0x00700000
    38. 

  38. #define SMI64_MSM_FB_SIZE		0x00100000
    39. 

  39. 

  40. #define SMI64_MSM_LINUX_BASE		MSM_EBI_BASE
    41. 

  41. #define SMI64_MSM_LINUX_SIZE		0x068e0000
    42. 

  42. 

  43. #define SMI64_MSM_LINUX_BASE_1		0x02000000
    44. 

  44. #define SMI64_MSM_LINUX_SIZE_1		0x02000000
    45. 

  45. 

  46. #define SMI64_MSM_LINUX_BASE_2		MSM_EBI_BASE
    47. 

  47. #define SMI64_MSM_LINUX_SIZE_2		0x05400000
    48. 

  48. 

  49. #define SMI32_MSM_LINUX_BASE		MSM_EBI_BASE
    50. 

  50. #define SMI32_MSM_LINUX_SIZE		0x5400000
    51. 

  51. 

  52. #define SMI32_MSM_PMEM_MDP_BASE	SMI32_MSM_LINUX_BASE + SMI32_MSM_LINUX_SIZE
    53. 

  53. #define SMI32_MSM_PMEM_MDP_SIZE	0x800000
    54. 

  54. 

  55. #define SMI32_MSM_PMEM_ADSP_BASE	SMI32_MSM_PMEM_MDP_BASE + SMI32_MSM_PMEM_MDP_SIZE
    56. 

  56. #define SMI32_MSM_PMEM_ADSP_SIZE	0x800000
    57. 

  57. 

  58. #define SMI32_MSM_FB_BASE		SMI32_MSM_PMEM_ADSP_BASE + SMI32_MSM_PMEM_ADSP_SIZE
    59. 

  59. #define SMI32_MSM_FB_SIZE		0x9b000
    60. 

  60. 

  61. 

  62. #define MSM_PMEM_GPU1_SIZE	0x800000
    63. 

  63. #define MSM_PMEM_GPU1_BASE     (MSM_RAM_CONSOLE_BASE + MSM_RAM_CONSOLE_SIZE)
    64. 

  64. 

  65. #define MSM_RAM_CONSOLE_BASE	0x169E0000
    66. 

  66. #define MSM_RAM_CONSOLE_SIZE	128 * SZ_1K
    67. 

  67. 

  68. #if (SMI32_MSM_FB_BASE + SMI32_MSM_FB_SIZE) >= (MSM_PMEM_GPU1_BASE)
    69. 

  69. #error invalid memory map
    70. 

  70. #endif
    71. 

  71. 

  72. #if (SMI64_MSM_FB_BASE + SMI64_MSM_FB_SIZE) >= (MSM_PMEM_GPU1_BASE)
    73. 

  73. #error invalid memory map
    74. 

  74. #endif
    75. 

  75. 

  76. #define DECLARE_MSM_IOMAP
    77. 

  77. #include <mach/msm_iomap.h>
    78. 

  78. 

  79. /*
    80. 

  80. ** SOC GPIO
    81. 

  81. */
    82. 

  82. #define SAPPHIRE_BALL_UP_0     94
    83. 

  83. #define SAPPHIRE_BALL_LEFT_0   18
    84. 

  84. #define SAPPHIRE_BALL_DOWN_0   49
    85. 

  85. #define SAPPHIRE_BALL_RIGHT_0  19
    86. 

  86. 

  87. #define SAPPHIRE_POWER_KEY     20
    88. 

  88. #define SAPPHIRE_VOLUME_UP     36
    89. 

  89. #define SAPPHIRE_VOLUME_DOWN   39
    90. 

  90. 

  91. #define SAPPHIRE_GPIO_PS_HOLD   (25)
    92. 

  92. #define SAPPHIRE_MDDI_1V5_EN	(28)
    93. 

  93. #define SAPPHIRE_BL_PWM			(27)
    94. 

  94. #define SAPPHIRE_TP_LS_EN    	(1)
    95. 

  95. #define SAPPHIRE20_TP_LS_EN			(88)
    96. 

  96. 

  97. /* H2W */
    98. 

  98. #define SAPPHIRE_GPIO_CABLE_IN1		(83)
    99. 

  99. #define SAPPHIRE_GPIO_CABLE_IN2		(37)
    100. 

  100. #define SAPPHIRE_GPIO_UART3_RX		(86)
    101. 

  101. #define SAPPHIRE_GPIO_UART3_TX		(87)
    102. 

  102. #define SAPPHIRE_GPIO_H2W_DATA		(86)
    103. 

  103. #define SAPPHIRE_GPIO_H2W_CLK		(87)
    104. 

  104. 

  105. #define SAPPHIRE_GPIO_UART1_RTS		(43)
    106. 

  106. #define SAPPHIRE_GPIO_UART1_CTS		(44)
    107. 

  107. 

  108. /*
    109. 

  109. ** CPLD GPIO
    110. 

  110. **
    111. 

  111. ** Sapphire Altera CPLD can keep the registers value and
    112. 

  112. ** doesn't need a shadow to backup.
    113. 

  113. **/
    114. 

  114. #define SAPPHIRE_CPLD_BASE   0xFA000000	/* VA */
    115. 

  115. #define SAPPHIRE_CPLD_START  0x98000000	/* PA */
    116. 

  116. #define SAPPHIRE_CPLD_SIZE   SZ_4K
    117. 

  117. 

  118. #define SAPPHIRE_GPIO_START (128)				/* Pseudo GPIO number */
    119. 

  119. 

  120. /* Sapphire has one INT BANK only. */
    121. 

  121. #define SAPPHIRE_GPIO_INT_B0_MASK_REG           (0x0c)	/*INT3 MASK*/
    122. 

  122. #define SAPPHIRE_GPIO_INT_B0_STAT_REG           (0x0e)	/*INT1 STATUS*/
    123. 

  123. 

  124. /* LED control register */
    125. 

  125. #define SAPPHIRE_CPLD_LED_BASE									(SAPPHIRE_CPLD_BASE + 0x10)		/* VA */
    126. 

  126. #define SAPPHIRE_CPLD_LED_START									(SAPPHIRE_CPLD_START + 0x10)	/* PA */
    127. 

  127. #define SAPPHIRE_CPLD_LED_SIZE									0x08
    128. 

  128. 

  129. /* MISCn: GPO pin to Enable/Disable some functions. */
    130. 

  130. #define SAPPHIRE_GPIO_MISC1_BASE               	(SAPPHIRE_GPIO_START + 0x00)
    131. 

  131. #define SAPPHIRE_GPIO_MISC2_BASE               	(SAPPHIRE_GPIO_START + 0x08)
    132. 

  132. #define SAPPHIRE_GPIO_MISC3_BASE               	(SAPPHIRE_GPIO_START + 0x10)
    133. 

  133. #define SAPPHIRE_GPIO_MISC4_BASE               	(SAPPHIRE_GPIO_START + 0x18)
    134. 

  134. #define SAPPHIRE_GPIO_MISC5_BASE               	(SAPPHIRE_GPIO_START + 0x20)
    135. 

  135. 

  136. /* INT BANK0: INT1: int status, INT2: int level, INT3: int Mask */
    137. 

  137. #define SAPPHIRE_GPIO_INT_B0_BASE              	(SAPPHIRE_GPIO_START + 0x28)
    138. 

  138. 

  139. /* MISCn GPIO: */
    140. 

  140. #define SAPPHIRE_GPIO_CPLD128_VER_0            	(SAPPHIRE_GPIO_MISC1_BASE + 4)
    141. 

  141. #define SAPPHIRE_GPIO_CPLD128_VER_1            	(SAPPHIRE_GPIO_MISC1_BASE + 5)
    142. 

  142. #define SAPPHIRE_GPIO_CPLD128_VER_2            	(SAPPHIRE_GPIO_MISC1_BASE + 6)
    143. 

  143. #define SAPPHIRE_GPIO_CPLD128_VER_3            	(SAPPHIRE_GPIO_MISC1_BASE + 7)
    144. 

  144. 

  145. #define SAPPHIRE_GPIO_H2W_DAT_DIR              	(SAPPHIRE_GPIO_MISC2_BASE + 2)
    146. 

  146. #define SAPPHIRE_GPIO_H2W_CLK_DIR              	(SAPPHIRE_GPIO_MISC2_BASE + 3)
    147. 

  147. #define SAPPHIRE_GPIO_H2W_SEL0                 	(SAPPHIRE_GPIO_MISC2_BASE + 6)
    148. 

  148. #define SAPPHIRE_GPIO_H2W_SEL1                 	(SAPPHIRE_GPIO_MISC2_BASE + 7)
    149. 

  149. 

  150. #define SAPPHIRE_GPIO_I2C_PULL                 	(SAPPHIRE_GPIO_MISC3_BASE + 2)
    151. 

  151. #define SAPPHIRE_GPIO_TP_EN                    	(SAPPHIRE_GPIO_MISC3_BASE + 4)
    152. 

  152. #define SAPPHIRE_GPIO_JOG_EN                   	(SAPPHIRE_GPIO_MISC3_BASE + 5)
    153. 

  153. #define SAPPHIRE_GPIO_JOG_LED_EN               	(SAPPHIRE_GPIO_MISC3_BASE + 6)
    154. 

  154. #define SAPPHIRE_GPIO_APKEY_LED_EN             	(SAPPHIRE_GPIO_MISC3_BASE + 7)
    155. 

  155. 

  156. #define SAPPHIRE_GPIO_VCM_PWDN                 	(SAPPHIRE_GPIO_MISC4_BASE + 0)
    157. 

  157. #define SAPPHIRE_GPIO_USB_H2W_SW               	(SAPPHIRE_GPIO_MISC4_BASE + 1)
    158. 

  158. #define SAPPHIRE_GPIO_COMPASS_RST_N            	(SAPPHIRE_GPIO_MISC4_BASE + 2)
    159. 

  159. #define SAPPHIRE_GPIO_USB_PHY_RST_N            	(SAPPHIRE_GPIO_MISC4_BASE + 5)
    160. 

  160. #define SAPPHIRE_GPIO_WIFI_PA_RESETX           	(SAPPHIRE_GPIO_MISC4_BASE + 6)
    161. 

  161. #define SAPPHIRE_GPIO_WIFI_EN                  	(SAPPHIRE_GPIO_MISC4_BASE + 7)
    162. 

  162. 

  163. #define SAPPHIRE_GPIO_BT_32K_EN                	(SAPPHIRE_GPIO_MISC5_BASE + 0)
    164. 

  164. #define SAPPHIRE_GPIO_MAC_32K_EN               	(SAPPHIRE_GPIO_MISC5_BASE + 1)
    165. 

  165. #define SAPPHIRE_GPIO_MDDI_32K_EN              	(SAPPHIRE_GPIO_MISC5_BASE + 2)
    166. 

  166. #define SAPPHIRE_GPIO_COMPASS_32K_EN           	(SAPPHIRE_GPIO_MISC5_BASE + 3)
    167. 

  167. 

  168. /* INT STATUS/LEVEL/MASK : INT GPIO should be the last. */
    169. 

  169. #define SAPPHIRE_GPIO_NAVI_ACT_N           		(SAPPHIRE_GPIO_INT_B0_BASE + 0)
    170. 

  170. #define SAPPHIRE_GPIO_COMPASS_IRQ         		(SAPPHIRE_GPIO_INT_B0_BASE + 1)
    171. 

  171. #define SAPPHIRE_GPIO_SEARCH_ACT_N			(SAPPHIRE_GPIO_INT_B0_BASE + 2)
    172. 

  172. #define SAPPHIRE_GPIO_AUD_HSMIC_DET_N      		(SAPPHIRE_GPIO_INT_B0_BASE + 3)
    173. 

  173. #define SAPPHIRE_GPIO_SDMC_CD_N      			(SAPPHIRE_GPIO_INT_B0_BASE + 4)
    174. 

  174. #define SAPPHIRE_GPIO_CAM_BTN_STEP1_N          	(SAPPHIRE_GPIO_INT_B0_BASE + 5)
    175. 

  175. #define SAPPHIRE_GPIO_CAM_BTN_STEP2_N          	(SAPPHIRE_GPIO_INT_B0_BASE + 6)
    176. 

  176. #define SAPPHIRE_GPIO_TP_ATT_N            		(SAPPHIRE_GPIO_INT_B0_BASE + 7)
    177. 

  177. 

  178. #define	SAPPHIRE_GPIO_END						SAPPHIRE_GPIO_TP_ATT_N
    179. 

  179. #define	SAPPHIRE_GPIO_LAST_INT					(SAPPHIRE_GPIO_TP_ATT_N)
    180. 

  180. 

  181. /* Bit position in the CPLD MISCn by the CPLD GPIOn: only bit0-7 is used. */
    182. 

  182. #define	CPLD_GPIO_BIT_POS_MASK(n)		(1U << ((n) & 7))
    183. 

  183. #define	CPLD_GPIO_REG_OFFSET(n)			_g_CPLD_MISCn_Offset[((n)-SAPPHIRE_GPIO_START) >> 3]
    184. 

  184. #define	CPLD_GPIO_REG(n)				(CPLD_GPIO_REG_OFFSET(n) + SAPPHIRE_CPLD_BASE)
    185. 

  185. 

  186. /*
    187. 

  187. ** CPLD INT Start
    188. 

  188. */
    189. 

  189. #define SAPPHIRE_INT_START 					(NR_MSM_IRQS + NR_GPIO_IRQS)	/* pseudo number for CPLD INT */
    190. 

  190. /* Using INT status/Bank0 for GPIO to INT */
    191. 

  191. #define	SAPPHIRE_GPIO_TO_INT(n)				((n-SAPPHIRE_GPIO_INT_B0_BASE) + SAPPHIRE_INT_START)
    192. 

  192. #define SAPPHIRE_INT_END 					(SAPPHIRE_GPIO_TO_INT(SAPPHIRE_GPIO_END))
    193. 

  193. 

  194. /* get the INT reg by GPIO number */
    195. 

  195. #define	CPLD_INT_GPIO_TO_BANK(n)			(((n)-SAPPHIRE_GPIO_INT_B0_BASE) >> 3)
    196. 

  196. #define	CPLD_INT_STATUS_REG_OFFSET_G(n)		_g_INT_BANK_Offset[CPLD_INT_GPIO_TO_BANK(n)][0]
    197. 

  197. #define	CPLD_INT_LEVEL_REG_OFFSET_G(n)		_g_INT_BANK_Offset[CPLD_INT_GPIO_TO_BANK(n)][1]
    198. 

  198. #define	CPLD_INT_MASK_REG_OFFSET_G(n)		_g_INT_BANK_Offset[CPLD_INT_GPIO_TO_BANK(n)][2]
    199. 

  199. #define	CPLD_INT_STATUS_REG_G(n)			(SAPPHIRE_CPLD_BASE + CPLD_INT_STATUS_REG_OFFSET_G(n))
    200. 

  200. #define	CPLD_INT_LEVEL_REG_G(n)				(SAPPHIRE_CPLD_BASE + CPLD_INT_LEVEL_REG_OFFSET_G(n))
    201. 

  201. #define	CPLD_INT_MASK_REG_G(n)				(SAPPHIRE_CPLD_BASE + CPLD_INT_MASK_REG_OFFSET_G(n))
    202. 

  202. 

  203. /* get the INT reg by INT number */
    204. 

  204. #define	CPLD_INT_TO_BANK(i)					((i-SAPPHIRE_INT_START) >> 3)
    205. 

  205. #define	CPLD_INT_STATUS_REG_OFFSET(i)		_g_INT_BANK_Offset[CPLD_INT_TO_BANK(i)][0]
    206. 

  206. #define	CPLD_INT_LEVEL_REG_OFFSET(i)		_g_INT_BANK_Offset[CPLD_INT_TO_BANK(i)][1]
    207. 

  207. #define	CPLD_INT_MASK_REG_OFFSET(i)			_g_INT_BANK_Offset[CPLD_INT_TO_BANK(i)][2]
    208. 

  208. #define	CPLD_INT_STATUS_REG(i)				(SAPPHIRE_CPLD_BASE + CPLD_INT_STATUS_REG_OFFSET(i))
    209. 

  209. #define	CPLD_INT_LEVEL_REG(i)				(SAPPHIRE_CPLD_BASE + CPLD_INT_LEVEL_REG_OFFSET(i))
    210. 

  210. #define	CPLD_INT_MASK_REG(i)				(SAPPHIRE_CPLD_BASE + CPLD_INT_MASK_REG_OFFSET(i) )
    211. 

  211. 

  212. /* return the bit mask by INT number */
    213. 

  213. #define SAPPHIRE_INT_BIT_MASK(i) 			(1U << ((i - SAPPHIRE_INT_START) & 7))
    214. 

  214. 

  215. void config_sapphire_camera_on_gpios(void);
    216. 

  216. void config_sapphire_camera_off_gpios(void);
    217. 

  217. int sapphire_get_smi_size(void);
    218. 

  218. unsigned int sapphire_get_hwid(void);
    219. 

  219. unsigned int sapphire_get_skuid(void);
    220. 

  220. unsigned int is_12pin_camera(void);
    221. 

  221. int sapphire_is_5M_camera(void);
    222. 

  222. int sapphire_gpio_write(struct gpio_chip *chip, unsigned n, unsigned on);
    223. 

  223. 

  224. #endif /* GUARD */
    225.