/arch/arm/mach-msm/board-sapphire.h

https://bitbucket.org/sammyz/iscream_thunderc-2.6.35-rebase · C++ Header · 224 lines · 141 code · 46 blank · 37 comment · 0 complexity · 09af0aa2b4e16abcc207e3462da91036 MD5 · raw file

  1. /* linux/arch/arm/mach-msm/board-sapphire.h
  2. * Copyright (C) 2007-2009 HTC Corporation.
  3. * Author: Thomas Tsai <thomas_tsai@htc.com>
  4. *
  5. * This software is licensed under the terms of the GNU General Public
  6. * License version 2, as published by the Free Software Foundation, and
  7. * may be copied, distributed, and modified under those terms.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #ifndef __ARCH_ARM_MACH_MSM_BOARD_SAPPHIRE_H
  15. #define __ARCH_ARM_MACH_MSM_BOARD_SAPPHIRE_H
  16. #include <mach/board.h>
  17. #define MSM_SMI_BASE 0x00000000
  18. #define MSM_SMI_SIZE 0x00800000
  19. #define MSM_EBI_BASE 0x10000000
  20. #define MSM_EBI_SIZE 0x07100000
  21. #define MSM_PMEM_GPU0_BASE 0x00000000
  22. #define MSM_PMEM_GPU0_SIZE 0x00700000
  23. #define SMI64_MSM_PMEM_MDP_BASE 0x15900000
  24. #define SMI64_MSM_PMEM_MDP_SIZE 0x00800000
  25. #define SMI64_MSM_PMEM_ADSP_BASE 0x16100000
  26. #define SMI64_MSM_PMEM_ADSP_SIZE 0x00800000
  27. #define SMI64_MSM_PMEM_CAMERA_BASE 0x15400000
  28. #define SMI64_MSM_PMEM_CAMERA_SIZE 0x00500000
  29. #define SMI64_MSM_FB_BASE 0x00700000
  30. #define SMI64_MSM_FB_SIZE 0x00100000
  31. #define SMI64_MSM_LINUX_BASE MSM_EBI_BASE
  32. #define SMI64_MSM_LINUX_SIZE 0x068e0000
  33. #define SMI64_MSM_LINUX_BASE_1 0x02000000
  34. #define SMI64_MSM_LINUX_SIZE_1 0x02000000
  35. #define SMI64_MSM_LINUX_BASE_2 MSM_EBI_BASE
  36. #define SMI64_MSM_LINUX_SIZE_2 0x05400000
  37. #define SMI32_MSM_LINUX_BASE MSM_EBI_BASE
  38. #define SMI32_MSM_LINUX_SIZE 0x5400000
  39. #define SMI32_MSM_PMEM_MDP_BASE SMI32_MSM_LINUX_BASE + SMI32_MSM_LINUX_SIZE
  40. #define SMI32_MSM_PMEM_MDP_SIZE 0x800000
  41. #define SMI32_MSM_PMEM_ADSP_BASE SMI32_MSM_PMEM_MDP_BASE + SMI32_MSM_PMEM_MDP_SIZE
  42. #define SMI32_MSM_PMEM_ADSP_SIZE 0x800000
  43. #define SMI32_MSM_FB_BASE SMI32_MSM_PMEM_ADSP_BASE + SMI32_MSM_PMEM_ADSP_SIZE
  44. #define SMI32_MSM_FB_SIZE 0x9b000
  45. #define MSM_PMEM_GPU1_SIZE 0x800000
  46. #define MSM_PMEM_GPU1_BASE (MSM_RAM_CONSOLE_BASE + MSM_RAM_CONSOLE_SIZE)
  47. #define MSM_RAM_CONSOLE_BASE 0x169E0000
  48. #define MSM_RAM_CONSOLE_SIZE 128 * SZ_1K
  49. #if (SMI32_MSM_FB_BASE + SMI32_MSM_FB_SIZE) >= (MSM_PMEM_GPU1_BASE)
  50. #error invalid memory map
  51. #endif
  52. #if (SMI64_MSM_FB_BASE + SMI64_MSM_FB_SIZE) >= (MSM_PMEM_GPU1_BASE)
  53. #error invalid memory map
  54. #endif
  55. #define DECLARE_MSM_IOMAP
  56. #include <mach/msm_iomap.h>
  57. /*
  58. ** SOC GPIO
  59. */
  60. #define SAPPHIRE_BALL_UP_0 94
  61. #define SAPPHIRE_BALL_LEFT_0 18
  62. #define SAPPHIRE_BALL_DOWN_0 49
  63. #define SAPPHIRE_BALL_RIGHT_0 19
  64. #define SAPPHIRE_POWER_KEY 20
  65. #define SAPPHIRE_VOLUME_UP 36
  66. #define SAPPHIRE_VOLUME_DOWN 39
  67. #define SAPPHIRE_GPIO_PS_HOLD (25)
  68. #define SAPPHIRE_MDDI_1V5_EN (28)
  69. #define SAPPHIRE_BL_PWM (27)
  70. #define SAPPHIRE_TP_LS_EN (1)
  71. #define SAPPHIRE20_TP_LS_EN (88)
  72. /* H2W */
  73. #define SAPPHIRE_GPIO_CABLE_IN1 (83)
  74. #define SAPPHIRE_GPIO_CABLE_IN2 (37)
  75. #define SAPPHIRE_GPIO_UART3_RX (86)
  76. #define SAPPHIRE_GPIO_UART3_TX (87)
  77. #define SAPPHIRE_GPIO_H2W_DATA (86)
  78. #define SAPPHIRE_GPIO_H2W_CLK (87)
  79. #define SAPPHIRE_GPIO_UART1_RTS (43)
  80. #define SAPPHIRE_GPIO_UART1_CTS (44)
  81. /*
  82. ** CPLD GPIO
  83. **
  84. ** Sapphire Altera CPLD can keep the registers value and
  85. ** doesn't need a shadow to backup.
  86. **/
  87. #define SAPPHIRE_CPLD_BASE 0xFA000000 /* VA */
  88. #define SAPPHIRE_CPLD_START 0x98000000 /* PA */
  89. #define SAPPHIRE_CPLD_SIZE SZ_4K
  90. #define SAPPHIRE_GPIO_START (128) /* Pseudo GPIO number */
  91. /* Sapphire has one INT BANK only. */
  92. #define SAPPHIRE_GPIO_INT_B0_MASK_REG (0x0c) /*INT3 MASK*/
  93. #define SAPPHIRE_GPIO_INT_B0_STAT_REG (0x0e) /*INT1 STATUS*/
  94. /* LED control register */
  95. #define SAPPHIRE_CPLD_LED_BASE (SAPPHIRE_CPLD_BASE + 0x10) /* VA */
  96. #define SAPPHIRE_CPLD_LED_START (SAPPHIRE_CPLD_START + 0x10) /* PA */
  97. #define SAPPHIRE_CPLD_LED_SIZE 0x08
  98. /* MISCn: GPO pin to Enable/Disable some functions. */
  99. #define SAPPHIRE_GPIO_MISC1_BASE (SAPPHIRE_GPIO_START + 0x00)
  100. #define SAPPHIRE_GPIO_MISC2_BASE (SAPPHIRE_GPIO_START + 0x08)
  101. #define SAPPHIRE_GPIO_MISC3_BASE (SAPPHIRE_GPIO_START + 0x10)
  102. #define SAPPHIRE_GPIO_MISC4_BASE (SAPPHIRE_GPIO_START + 0x18)
  103. #define SAPPHIRE_GPIO_MISC5_BASE (SAPPHIRE_GPIO_START + 0x20)
  104. /* INT BANK0: INT1: int status, INT2: int level, INT3: int Mask */
  105. #define SAPPHIRE_GPIO_INT_B0_BASE (SAPPHIRE_GPIO_START + 0x28)
  106. /* MISCn GPIO: */
  107. #define SAPPHIRE_GPIO_CPLD128_VER_0 (SAPPHIRE_GPIO_MISC1_BASE + 4)
  108. #define SAPPHIRE_GPIO_CPLD128_VER_1 (SAPPHIRE_GPIO_MISC1_BASE + 5)
  109. #define SAPPHIRE_GPIO_CPLD128_VER_2 (SAPPHIRE_GPIO_MISC1_BASE + 6)
  110. #define SAPPHIRE_GPIO_CPLD128_VER_3 (SAPPHIRE_GPIO_MISC1_BASE + 7)
  111. #define SAPPHIRE_GPIO_H2W_DAT_DIR (SAPPHIRE_GPIO_MISC2_BASE + 2)
  112. #define SAPPHIRE_GPIO_H2W_CLK_DIR (SAPPHIRE_GPIO_MISC2_BASE + 3)
  113. #define SAPPHIRE_GPIO_H2W_SEL0 (SAPPHIRE_GPIO_MISC2_BASE + 6)
  114. #define SAPPHIRE_GPIO_H2W_SEL1 (SAPPHIRE_GPIO_MISC2_BASE + 7)
  115. #define SAPPHIRE_GPIO_I2C_PULL (SAPPHIRE_GPIO_MISC3_BASE + 2)
  116. #define SAPPHIRE_GPIO_TP_EN (SAPPHIRE_GPIO_MISC3_BASE + 4)
  117. #define SAPPHIRE_GPIO_JOG_EN (SAPPHIRE_GPIO_MISC3_BASE + 5)
  118. #define SAPPHIRE_GPIO_JOG_LED_EN (SAPPHIRE_GPIO_MISC3_BASE + 6)
  119. #define SAPPHIRE_GPIO_APKEY_LED_EN (SAPPHIRE_GPIO_MISC3_BASE + 7)
  120. #define SAPPHIRE_GPIO_VCM_PWDN (SAPPHIRE_GPIO_MISC4_BASE + 0)
  121. #define SAPPHIRE_GPIO_USB_H2W_SW (SAPPHIRE_GPIO_MISC4_BASE + 1)
  122. #define SAPPHIRE_GPIO_COMPASS_RST_N (SAPPHIRE_GPIO_MISC4_BASE + 2)
  123. #define SAPPHIRE_GPIO_USB_PHY_RST_N (SAPPHIRE_GPIO_MISC4_BASE + 5)
  124. #define SAPPHIRE_GPIO_WIFI_PA_RESETX (SAPPHIRE_GPIO_MISC4_BASE + 6)
  125. #define SAPPHIRE_GPIO_WIFI_EN (SAPPHIRE_GPIO_MISC4_BASE + 7)
  126. #define SAPPHIRE_GPIO_BT_32K_EN (SAPPHIRE_GPIO_MISC5_BASE + 0)
  127. #define SAPPHIRE_GPIO_MAC_32K_EN (SAPPHIRE_GPIO_MISC5_BASE + 1)
  128. #define SAPPHIRE_GPIO_MDDI_32K_EN (SAPPHIRE_GPIO_MISC5_BASE + 2)
  129. #define SAPPHIRE_GPIO_COMPASS_32K_EN (SAPPHIRE_GPIO_MISC5_BASE + 3)
  130. /* INT STATUS/LEVEL/MASK : INT GPIO should be the last. */
  131. #define SAPPHIRE_GPIO_NAVI_ACT_N (SAPPHIRE_GPIO_INT_B0_BASE + 0)
  132. #define SAPPHIRE_GPIO_COMPASS_IRQ (SAPPHIRE_GPIO_INT_B0_BASE + 1)
  133. #define SAPPHIRE_GPIO_SEARCH_ACT_N (SAPPHIRE_GPIO_INT_B0_BASE + 2)
  134. #define SAPPHIRE_GPIO_AUD_HSMIC_DET_N (SAPPHIRE_GPIO_INT_B0_BASE + 3)
  135. #define SAPPHIRE_GPIO_SDMC_CD_N (SAPPHIRE_GPIO_INT_B0_BASE + 4)
  136. #define SAPPHIRE_GPIO_CAM_BTN_STEP1_N (SAPPHIRE_GPIO_INT_B0_BASE + 5)
  137. #define SAPPHIRE_GPIO_CAM_BTN_STEP2_N (SAPPHIRE_GPIO_INT_B0_BASE + 6)
  138. #define SAPPHIRE_GPIO_TP_ATT_N (SAPPHIRE_GPIO_INT_B0_BASE + 7)
  139. #define SAPPHIRE_GPIO_END SAPPHIRE_GPIO_TP_ATT_N
  140. #define SAPPHIRE_GPIO_LAST_INT (SAPPHIRE_GPIO_TP_ATT_N)
  141. /* Bit position in the CPLD MISCn by the CPLD GPIOn: only bit0-7 is used. */
  142. #define CPLD_GPIO_BIT_POS_MASK(n) (1U << ((n) & 7))
  143. #define CPLD_GPIO_REG_OFFSET(n) _g_CPLD_MISCn_Offset[((n)-SAPPHIRE_GPIO_START) >> 3]
  144. #define CPLD_GPIO_REG(n) (CPLD_GPIO_REG_OFFSET(n) + SAPPHIRE_CPLD_BASE)
  145. /*
  146. ** CPLD INT Start
  147. */
  148. #define SAPPHIRE_INT_START (NR_MSM_IRQS + NR_GPIO_IRQS) /* pseudo number for CPLD INT */
  149. /* Using INT status/Bank0 for GPIO to INT */
  150. #define SAPPHIRE_GPIO_TO_INT(n) ((n-SAPPHIRE_GPIO_INT_B0_BASE) + SAPPHIRE_INT_START)
  151. #define SAPPHIRE_INT_END (SAPPHIRE_GPIO_TO_INT(SAPPHIRE_GPIO_END))
  152. /* get the INT reg by GPIO number */
  153. #define CPLD_INT_GPIO_TO_BANK(n) (((n)-SAPPHIRE_GPIO_INT_B0_BASE) >> 3)
  154. #define CPLD_INT_STATUS_REG_OFFSET_G(n) _g_INT_BANK_Offset[CPLD_INT_GPIO_TO_BANK(n)][0]
  155. #define CPLD_INT_LEVEL_REG_OFFSET_G(n) _g_INT_BANK_Offset[CPLD_INT_GPIO_TO_BANK(n)][1]
  156. #define CPLD_INT_MASK_REG_OFFSET_G(n) _g_INT_BANK_Offset[CPLD_INT_GPIO_TO_BANK(n)][2]
  157. #define CPLD_INT_STATUS_REG_G(n) (SAPPHIRE_CPLD_BASE + CPLD_INT_STATUS_REG_OFFSET_G(n))
  158. #define CPLD_INT_LEVEL_REG_G(n) (SAPPHIRE_CPLD_BASE + CPLD_INT_LEVEL_REG_OFFSET_G(n))
  159. #define CPLD_INT_MASK_REG_G(n) (SAPPHIRE_CPLD_BASE + CPLD_INT_MASK_REG_OFFSET_G(n))
  160. /* get the INT reg by INT number */
  161. #define CPLD_INT_TO_BANK(i) ((i-SAPPHIRE_INT_START) >> 3)
  162. #define CPLD_INT_STATUS_REG_OFFSET(i) _g_INT_BANK_Offset[CPLD_INT_TO_BANK(i)][0]
  163. #define CPLD_INT_LEVEL_REG_OFFSET(i) _g_INT_BANK_Offset[CPLD_INT_TO_BANK(i)][1]
  164. #define CPLD_INT_MASK_REG_OFFSET(i) _g_INT_BANK_Offset[CPLD_INT_TO_BANK(i)][2]
  165. #define CPLD_INT_STATUS_REG(i) (SAPPHIRE_CPLD_BASE + CPLD_INT_STATUS_REG_OFFSET(i))
  166. #define CPLD_INT_LEVEL_REG(i) (SAPPHIRE_CPLD_BASE + CPLD_INT_LEVEL_REG_OFFSET(i))
  167. #define CPLD_INT_MASK_REG(i) (SAPPHIRE_CPLD_BASE + CPLD_INT_MASK_REG_OFFSET(i) )
  168. /* return the bit mask by INT number */
  169. #define SAPPHIRE_INT_BIT_MASK(i) (1U << ((i - SAPPHIRE_INT_START) & 7))
  170. void config_sapphire_camera_on_gpios(void);
  171. void config_sapphire_camera_off_gpios(void);
  172. int sapphire_get_smi_size(void);
  173. unsigned int sapphire_get_hwid(void);
  174. unsigned int sapphire_get_skuid(void);
  175. unsigned int is_12pin_camera(void);
  176. int sapphire_is_5M_camera(void);
  177. int sapphire_gpio_write(struct gpio_chip *chip, unsigned n, unsigned on);
  178. #endif /* GUARD */