/arch/arm/mach-msm/board-qrdc.c
C | 4213 lines | 3554 code | 458 blank | 201 comment | 246 complexity | 89f1b7783fc1bdce4c6c17cc22a92312 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
Large files files are truncated, but you can click here to view the full file
1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18
19#include <linux/kernel.h>
20#include <linux/platform_device.h>
21#include <linux/gpio.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24#include <linux/mfd/pmic8058.h>
25#include <linux/mfd/bahama.h>
26#include <linux/input/pmic8058-keypad.h>
27#include <linux/pmic8058-pwrkey.h>
28#include <linux/pmic8058-vibrator.h>
29#include <linux/leds.h>
30#include <linux/pmic8058-othc.h>
31#include <linux/mfd/pmic8901.h>
32#include <linux/regulator/pmic8901-regulator.h>
33#include <linux/bootmem.h>
34#include <linux/pwm.h>
35#include <linux/pmic8058-pwm.h>
36#include <linux/leds-pmic8058.h>
37#include <linux/mfd/marimba.h>
38#include <linux/i2c.h>
39#include <linux/i2c/sx150x.h>
40#include <linux/smsc911x.h>
41#include <linux/spi/spi.h>
42#include <linux/input/tdisc_shinetsu.h>
43#include <linux/input/cy8c_ts.h>
44#include <linux/input/qci_kbd.h>
45#include <linux/mfd/wm8994/core.h>
46#include <linux/mfd/wm8994/pdata.h>
47
48#ifdef CONFIG_ANDROID_PMEM
49#include <linux/android_pmem.h>
50#endif
51
52#include <asm/mach-types.h>
53#include <asm/mach/arch.h>
54#include <asm/setup.h>
55
56#include <mach/mpp.h>
57#include <mach/board.h>
58#include <mach/irqs.h>
59#include <mach/msm_spi.h>
60#include <mach/msm_serial_hs.h>
61#include <mach/msm_iomap.h>
62#include <asm/mach/mmc.h>
63#include <mach/msm_battery.h>
64#include <mach/msm_hsusb.h>
65#include <mach/msm_xo.h>
66#include <mach/msm_bus_board.h>
67#include <mach/tpm_st_i2c.h>
68#include <mach/socinfo.h>
69#ifdef CONFIG_USB_ANDROID
70#include <linux/usb/android_composite.h>
71#endif
72#include <linux/regulator/consumer.h>
73#include <linux/regulator/machine.h>
74
75#include "devices.h"
76#include "devices-msm8x60.h"
77#include "cpuidle.h"
78#include "pm.h"
79#include "rpm.h"
80#include "mpm.h"
81#include "spm.h"
82#include "rpm_log.h"
83#include "timer.h"
84#include "saw-regulator.h"
85#include "rpm-regulator.h"
86#include "gpiomux.h"
87#include "gpiomux-8x60.h"
88
89#define MSM_SHARED_RAM_PHYS 0x40000000
90
91/* Macros assume PMIC GPIOs start at 0 */
92#define PM8058_GPIO_BASE NR_MSM_GPIOS
93#define PM8058_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + PM8058_GPIO_BASE)
94#define PM8058_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - PM8058_GPIO_BASE)
95#define PM8058_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS)
96
97#define PM8901_GPIO_BASE (PM8058_GPIO_BASE + \
98 PM8058_GPIOS + PM8058_MPPS)
99#define PM8901_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + PM8901_GPIO_BASE)
100#define PM8901_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - PM901_GPIO_BASE)
101#define PM8901_IRQ_BASE (PM8058_IRQ_BASE + \
102 NR_PMIC8058_IRQS)
103
104#define GPIO_EXPANDER_GPIO_BASE \
105 (PM8901_GPIO_BASE + PM8901_MPPS)
106#define GPIO_EXPANDER_IRQ_BASE (PM8901_IRQ_BASE + NR_PMIC8901_IRQS)
107
108/*
109 * The UI_INTx_N lines are pmic gpio lines which connect i2c
110 * gpio expanders to the pm8058.
111 */
112#define UI_INT1_N 25
113#define UI_INT2_N 34
114#define UI_INT3_N 14
115
116static struct msm_spm_platform_data msm_spm_data[] __initdata = {
117 [0] = {
118 .reg_base_addr = MSM_SAW0_BASE,
119
120 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x0F,
121 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
122 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0xFFFFFFFF,
123 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFFFFFFFF,
124
125 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
126 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
127 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
128
129 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
130 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
131 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
132
133 .awake_vlevel = 0x9C,
134 .retention_vlevel = 0x81,
135 .collapse_vlevel = 0x20,
136 .retention_mid_vlevel = 0x94,
137 .collapse_mid_vlevel = 0x8C,
138
139 .vctl_timeout_us = 50,
140 },
141
142 [1] = {
143 .reg_base_addr = MSM_SAW1_BASE,
144
145 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x0F,
146 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
147 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0xFFFFFFFF,
148 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFFFFFFFF,
149
150 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x13,
151 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
152 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
153
154 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
155 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
156 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
157
158 .awake_vlevel = 0x9C,
159 .retention_vlevel = 0x81,
160 .collapse_vlevel = 0x20,
161 .retention_mid_vlevel = 0x94,
162 .collapse_mid_vlevel = 0x8C,
163
164 .vctl_timeout_us = 50,
165 },
166};
167
168static struct msm_acpu_clock_platform_data msm8x60_acpu_clock_data = {
169};
170
171static struct regulator_consumer_supply saw_s0_supply =
172 REGULATOR_SUPPLY("8901_s0", NULL);
173static struct regulator_consumer_supply saw_s1_supply =
174 REGULATOR_SUPPLY("8901_s1", NULL);
175
176static struct regulator_init_data saw_s0_init_data = {
177 .constraints = {
178 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
179 .min_uV = 840000,
180 .max_uV = 1200000,
181 },
182 .num_consumer_supplies = 1,
183 .consumer_supplies = &saw_s0_supply,
184};
185
186static struct regulator_init_data saw_s1_init_data = {
187 .constraints = {
188 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
189 .min_uV = 840000,
190 .max_uV = 1200000,
191 },
192 .num_consumer_supplies = 1,
193 .consumer_supplies = &saw_s1_supply,
194};
195
196static struct platform_device msm_device_saw_s0 = {
197 .name = "saw-regulator",
198 .id = SAW_VREG_ID_S0,
199 .dev = {
200 .platform_data = &saw_s0_init_data,
201 },
202};
203
204static struct platform_device msm_device_saw_s1 = {
205 .name = "saw-regulator",
206 .id = SAW_VREG_ID_S1,
207 .dev = {
208 .platform_data = &saw_s1_init_data,
209 },
210};
211
212static struct resource smsc911x_resources[] = {
213 [0] = {
214 .flags = IORESOURCE_MEM,
215 .start = 0x1b800000,
216 .end = 0x1b8000ff
217 },
218 [1] = {
219 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
220 },
221};
222
223static struct smsc911x_platform_config smsc911x_config = {
224 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
225 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
226 .flags = SMSC911X_USE_16BIT
227};
228
229static struct platform_device smsc911x_device = {
230 .name = "smsc911x",
231 .id = 0,
232 .num_resources = ARRAY_SIZE(smsc911x_resources),
233 .resource = smsc911x_resources,
234 .dev = {
235 .platform_data = &smsc911x_config
236 }
237};
238
239static struct msm_pm_platform_data msm_pm_data[MSM_PM_SLEEP_MODE_NR * 2] = {
240 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
241 .supported = 1,
242 .suspend_enabled = 0,
243 .idle_enabled = 0,
244 .latency = 4000,
245 .residency = 13000,
246 },
247
248 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
249 .supported = 1,
250 .suspend_enabled = 0,
251 .idle_enabled = 0,
252 .latency = 500,
253 .residency = 6000,
254 },
255
256 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
257 .supported = 1,
258 .suspend_enabled = 1,
259 .idle_enabled = 1,
260 .latency = 2,
261 .residency = 0,
262 },
263
264 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
265 .supported = 1,
266 .suspend_enabled = 0,
267 .idle_enabled = 0,
268 .latency = 600,
269 .residency = 7200,
270 },
271
272 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
273 .supported = 1,
274 .suspend_enabled = 0,
275 .idle_enabled = 0,
276 .latency = 500,
277 .residency = 6000,
278 },
279
280 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
281 .supported = 1,
282 .suspend_enabled = 1,
283 .idle_enabled = 1,
284 .latency = 2,
285 .residency = 0,
286 },
287};
288
289static struct msm_cpuidle_state msm_cstates[] __initdata = {
290 {0, 0, "C0", "WFI",
291 MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
292
293 {0, 1, "C1", "STANDALONE_POWER_COLLAPSE",
294 MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
295
296 {0, 2, "C2", "POWER_COLLAPSE",
297 MSM_PM_SLEEP_MODE_POWER_COLLAPSE},
298
299 {1, 0, "C0", "WFI",
300 MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
301
302 {1, 1, "C1", "STANDALONE_POWER_COLLAPSE",
303 MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
304};
305
306#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_MSM)
307static struct regulator *ldo6_3p3;
308static struct regulator *ldo7_1p8;
309static struct regulator *vdd_cx;
310static int msm_hsusb_ldo_init(int init)
311{
312 if (init) {
313 ldo6_3p3 = regulator_get(NULL, "8058_l6");
314 if (IS_ERR(ldo6_3p3))
315 return PTR_ERR(ldo6_3p3);
316
317 ldo7_1p8 = regulator_get(NULL, "8058_l7");
318 if (IS_ERR(ldo7_1p8)) {
319 regulator_put(ldo6_3p3);
320 return PTR_ERR(ldo7_1p8);
321 }
322 /*digital core voltage for usb phy*/
323 vdd_cx = regulator_get(NULL, "8058_s1");
324 if (IS_ERR(vdd_cx)) {
325 regulator_put(ldo6_3p3);
326 regulator_put(ldo7_1p8);
327 return PTR_ERR(vdd_cx);
328 }
329
330 regulator_set_voltage(vdd_cx, 1000000, 1200000);
331 regulator_set_voltage(ldo7_1p8, 1800000, 1800000);
332 regulator_set_voltage(ldo6_3p3, 3050000, 3050000);
333 } else {
334 regulator_put(ldo6_3p3);
335 regulator_put(ldo7_1p8);
336 regulator_put(vdd_cx);
337 }
338 return 0;
339}
340
341static int msm_hsusb_ldo_enable(int on)
342{
343 static int ldo_status;
344 int ret = 0;
345
346 if (!ldo7_1p8 || IS_ERR(ldo7_1p8)) {
347 pr_err("%s: ldo7_1p8 is not initialized\n", __func__);
348 return -ENODEV;
349 }
350
351 if (!ldo6_3p3 || IS_ERR(ldo6_3p3)) {
352 pr_err("%s: ldo6_3p3 is not initialized\n", __func__);
353 return -ENODEV;
354 }
355
356 if (!vdd_cx || IS_ERR(vdd_cx)) {
357 pr_err("%s: vdd_cx is not initialized\n", __func__);
358 return -ENODEV;
359 }
360 if (ldo_status == on)
361 return 0;
362
363 ldo_status = on;
364
365 if (on) {
366 ret = regulator_enable(ldo7_1p8);
367 if (ret) {
368 pr_err("%s: Unable to enable the regulator:"
369 "ldo7_1p8\n", __func__);
370 ldo_status = !on;
371 return ret;
372 }
373 ret = regulator_enable(ldo6_3p3);
374 if (ret) {
375 pr_err("%s: Unable to enable the regulator:"
376 "ldo6_3p3\n", __func__);
377 regulator_disable(ldo7_1p8);
378 ldo_status = !on;
379 return ret;
380 }
381 ret = regulator_enable(vdd_cx);
382 if (ret) {
383 pr_err("%s: Unable to enable VDDCX digital core:"
384 " vdd_dig\n", __func__);
385 regulator_disable(ldo6_3p3);
386 regulator_disable(ldo7_1p8);
387 ldo_status = !on;
388 return ret;
389 }
390 } else {
391 /* calling regulator_disable when its already disabled might
392 * * print WARN_ON. Trying to avoid it by regulator_is_enable
393 * * */
394 if (regulator_is_enabled(ldo6_3p3)) {
395 ret = regulator_disable(ldo6_3p3);
396 if (ret) {
397 pr_err("%s: Unable to disable the regulator:"
398 "ldo6_3p3\n", __func__);
399 ldo_status = !on;
400 return ret;
401 }
402 }
403
404 if (regulator_is_enabled(ldo7_1p8)) {
405 ret = regulator_disable(ldo7_1p8);
406 if (ret) {
407 pr_err("%s: Unable to enable the regulator:"
408 " ldo7_1p8\n", __func__);
409 ldo_status = !on;
410 return ret;
411 }
412 }
413
414 if (regulator_is_enabled(vdd_cx)) {
415 ret = regulator_disable(vdd_cx);
416 if (ret) {
417 pr_err("%s: Unable to enable the regulator:"
418 "vdd_cx\n", __func__);
419 ldo_status = !on;
420 return ret;
421 }
422 }
423 }
424
425 pr_debug("reg (%s)\n", on ? "ENABLED" : "DISABLED");
426 return 0;
427 }
428#endif
429#ifdef CONFIG_USB_EHCI_MSM
430static void msm_hsusb_vbus_power(unsigned phy_info, int on)
431{
432 static struct regulator *votg_5v_switch;
433 static struct regulator *ext_5v_reg;
434 static int vbus_is_on;
435
436 /* If VBUS is already on (or off), do nothing. */
437 if (on == vbus_is_on)
438 return;
439
440 if (!votg_5v_switch) {
441 votg_5v_switch = regulator_get(NULL, "8901_usb_otg");
442 if (IS_ERR(votg_5v_switch)) {
443 pr_err("%s: unable to get votg_5v_switch\n", __func__);
444 return;
445 }
446 }
447 if (!ext_5v_reg) {
448 ext_5v_reg = regulator_get(NULL, "8901_mpp0");
449 if (IS_ERR(ext_5v_reg)) {
450 pr_err("%s: unable to get ext_5v_reg\n", __func__);
451 return;
452 }
453 }
454 if (on) {
455 if (regulator_enable(ext_5v_reg)) {
456 pr_err("%s: Unable to enable the regulator:"
457 " ext_5v_reg\n", __func__);
458 return;
459 }
460 if (regulator_enable(votg_5v_switch)) {
461 pr_err("%s: Unable to enable the regulator:"
462 " votg_5v_switch\n", __func__);
463 return;
464 }
465 } else {
466 if (regulator_disable(votg_5v_switch))
467 pr_err("%s: Unable to enable the regulator:"
468 " votg_5v_switch\n", __func__);
469 if (regulator_disable(ext_5v_reg))
470 pr_err("%s: Unable to enable the regulator:"
471 " ext_5v_reg\n", __func__);
472 }
473
474 vbus_is_on = on;
475}
476
477static struct msm_usb_host_platform_data msm_usb_host_pdata = {
478 .phy_info = (USB_PHY_INTEGRATED | USB_PHY_MODEL_45NM),
479 .power_budget = 390,
480};
481#endif
482
483#if defined(CONFIG_BATTERY_MSM8X60) && !defined(CONFIG_USB_EHCI_MSM)
484static int msm_hsusb_pmic_vbus_notif_init(void (*callback)(int online),
485 int init)
486{
487 if (init) {
488 /* TBD: right API will get filled here as a part of
489 * PMIC chanrger patch and removes thsi comments.*/
490 } else {
491 /* TBD: right API will get filled here as a part of
492 * PMIC chanrger patch and removes thsi comments.*/
493 }
494 return 0;
495}
496#endif
497#define USB_SWITCH_EN_GPIO 132 /* !CS of analog switch */
498#define USB_SWITCH_CNTL_GPIO 131 /* 0: Host, 1: Peripheral */
499#define USB_HUB_RESET_GPIO 34 /* 0: HUB is RESET */
500
501static int msm_otg_init_analog_switch_gpio(int on)
502{
503 int rc = 0;
504
505 if (on) {
506 /* USB SWITCH ENABLE*/
507 rc = gpio_request(USB_SWITCH_EN_GPIO, "USB_SWITCH_ENABLE");
508 if (rc) {
509 pr_err("%s: SW_EN gpio %d request failed\n", __func__,
510 USB_SWITCH_EN_GPIO);
511 return rc;
512 }
513
514 /* USB SWITCH CONTROL */
515 rc = gpio_request(USB_SWITCH_CNTL_GPIO, "USB_SWITCH_CONTROL");
516 if (rc) {
517 pr_err("%s: SW_CNTL gpio %d request failed\n", __func__,
518 USB_SWITCH_CNTL_GPIO);
519 goto fail_gpio_usb_switch_en;
520 }
521
522 /* USB HUB RESET */
523 rc = gpio_request(USB_HUB_RESET_GPIO, "USB_HUB_RESET");
524 if (rc) {
525 pr_err("%s: HUB_RESET gpio %d request failed\n",
526 __func__, USB_HUB_RESET_GPIO);
527 goto fail_gpio_usb_switch_cntl;
528 }
529 /* Set direction of USB SWITCH ENABLE gpio */
530 rc = gpio_direction_output(USB_SWITCH_EN_GPIO, 0);
531 if (rc) {
532 pr_err("%s: gpio_direction_output failed for %d\n",
533 __func__, USB_SWITCH_EN_GPIO);
534 goto fail_gpio_usb_hub_reset;
535 }
536 /* Set direction of USB SWITCH CONTROL gpio */
537 rc = gpio_direction_output(USB_SWITCH_CNTL_GPIO, 0);
538 if (rc) {
539 pr_err("%s: gpio_direction_output failed for %d\n",
540 __func__, USB_SWITCH_CNTL_GPIO);
541 goto fail_gpio_usb_hub_reset;
542 }
543 /* Set direction of USB HUB RESET gpio */
544 rc = gpio_direction_output(USB_HUB_RESET_GPIO, 0);
545 if (rc) {
546 pr_err("%s: gpio_direction_output failed for %d\n",
547 __func__, USB_HUB_RESET_GPIO);
548 goto fail_gpio_usb_hub_reset;
549 }
550 return rc;
551 }
552
553fail_gpio_usb_hub_reset:
554 gpio_free(USB_HUB_RESET_GPIO);
555fail_gpio_usb_switch_cntl:
556 gpio_free(USB_SWITCH_CNTL_GPIO);
557fail_gpio_usb_switch_en:
558 gpio_free(USB_SWITCH_EN_GPIO);
559
560 return rc;
561}
562
563static void msm_otg_setup_analog_switch_gpio(enum usb_switch_control mode)
564{
565 switch (mode) {
566 case USB_SWITCH_HOST:
567 /* Configure analog switch as USB host. */
568 gpio_set_value(USB_SWITCH_EN_GPIO, 0);
569 gpio_set_value(USB_SWITCH_CNTL_GPIO, 0);
570 /* Bring HUB out of RESET */
571 gpio_set_value(USB_HUB_RESET_GPIO, 1);
572 break;
573
574 case USB_SWITCH_PERIPHERAL:
575 /* Configure analog switch as USB peripheral. */
576 gpio_set_value(USB_SWITCH_EN_GPIO, 0);
577 gpio_set_value(USB_SWITCH_CNTL_GPIO, 1);
578 gpio_set_value(USB_HUB_RESET_GPIO, 0);
579 break;
580
581 case USB_SWITCH_DISABLE:
582 default:
583 /* Disable Switch */
584 gpio_set_value(USB_SWITCH_EN_GPIO, 1);
585 gpio_set_value(USB_HUB_RESET_GPIO, 0);
586 }
587}
588#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_MSM)
589static struct msm_otg_platform_data msm_otg_pdata = {
590 /* if usb link is in sps there is no need for
591 * usb pclk as dayatona fabric clock will be
592 * used instead
593 */
594 .usb_in_sps = 1,
595 .pemp_level = PRE_EMPHASIS_WITH_20_PERCENT,
596 .cdr_autoreset = CDR_AUTO_RESET_DISABLE,
597 .se1_gating = SE1_GATING_DISABLE,
598 .init_gpio = msm_otg_init_analog_switch_gpio,
599 .setup_gpio = msm_otg_setup_analog_switch_gpio,
600#ifdef CONFIG_USB_EHCI_MSM
601 .vbus_power = msm_hsusb_vbus_power,
602#endif
603#if defined(CONFIG_BATTERY_MSM8X60) && !defined(CONFIG_USB_EHCI_MSM)
604 .pmic_vbus_notif_init = msm_hsusb_pmic_vbus_notif_init,
605#endif
606 .otg_mode = OTG_USER_CONTROL,
607 .usb_mode = USB_HOST_MODE,
608 .ldo_init = msm_hsusb_ldo_init,
609 .ldo_enable = msm_hsusb_ldo_enable,
610};
611#endif
612
613
614#ifdef CONFIG_USB_ANDROID
615static char *usb_functions_default[] = {
616 "diag",
617 "modem",
618 "nmea",
619 "rmnet",
620 "usb_mass_storage",
621};
622
623static char *usb_functions_default_adb[] = {
624 "diag",
625 "adb",
626 "modem",
627 "nmea",
628 "rmnet",
629 "usb_mass_storage",
630};
631
632static char *usb_functions_rndis[] = {
633 "rndis",
634};
635
636static char *usb_functions_rndis_adb[] = {
637 "rndis",
638 "adb",
639};
640
641static char *usb_functions_all[] = {
642#ifdef CONFIG_USB_ANDROID_RNDIS
643 "rndis",
644#endif
645#ifdef CONFIG_USB_ANDROID_DIAG
646 "diag",
647#endif
648 "adb",
649#ifdef CONFIG_USB_F_SERIAL
650 "modem",
651 "nmea",
652#endif
653#ifdef CONFIG_USB_ANDROID_RMNET
654 "rmnet",
655#endif
656 "usb_mass_storage",
657#ifdef CONFIG_USB_ANDROID_ACM
658 "acm",
659#endif
660};
661
662static struct android_usb_product usb_products[] = {
663 {
664 .product_id = 0x9026,
665 .num_functions = ARRAY_SIZE(usb_functions_default),
666 .functions = usb_functions_default,
667 },
668 {
669 .product_id = 0x9025,
670 .num_functions = ARRAY_SIZE(usb_functions_default_adb),
671 .functions = usb_functions_default_adb,
672 },
673 {
674 .product_id = 0xf00e,
675 .num_functions = ARRAY_SIZE(usb_functions_rndis),
676 .functions = usb_functions_rndis,
677 },
678 {
679 .product_id = 0x9024,
680 .num_functions = ARRAY_SIZE(usb_functions_rndis_adb),
681 .functions = usb_functions_rndis_adb,
682 },
683};
684static struct usb_mass_storage_platform_data mass_storage_pdata = {
685 .nluns = 1,
686 .vendor = "Qualcomm Incorporated",
687 .product = "Mass storage",
688};
689
690static struct platform_device usb_mass_storage_device = {
691 .name = "usb_mass_storage",
692 .id = -1,
693 .dev = {
694 .platform_data = &mass_storage_pdata,
695 },
696};
697
698static struct usb_ether_platform_data rndis_pdata = {
699 /* ethaddr is filled by board_serialno_setup */
700 .vendorID = 0x05C6,
701 .vendorDescr = "Qualcomm Incorporated",
702};
703
704static struct platform_device rndis_device = {
705 .name = "rndis",
706 .id = -1,
707 .dev = {
708 .platform_data = &rndis_pdata,
709 },
710};
711static struct android_usb_platform_data android_usb_pdata = {
712 .vendor_id = 0x05C6,
713 .product_id = 0x9026,
714 .version = 0x0100,
715 .product_name = "Qualcomm HSUSB Device",
716 .manufacturer_name = "Qualcomm Incorporated",
717 .num_products = ARRAY_SIZE(usb_products),
718 .products = usb_products,
719 .num_functions = ARRAY_SIZE(usb_functions_all),
720 .functions = usb_functions_all,
721 .serial_number = "1234567890ABCDEF",
722};
723static struct platform_device android_usb_device = {
724 .name = "android_usb",
725 .id = -1,
726 .dev = {
727 .platform_data = &android_usb_pdata,
728 },
729};
730
731static int __init board_serialno_setup(char *serialno)
732{
733 int i;
734 char *src = serialno;
735
736 /* create a fake MAC address from our serial number.
737 * first byte is 0x02 to signify locally administered.
738 */
739 rndis_pdata.ethaddr[0] = 0x02;
740 for (i = 0; *src; i++) {
741 /* XOR the USB serial across the remaining bytes */
742 rndis_pdata.ethaddr[i % (ETH_ALEN - 1) + 1] ^= *src++;
743 }
744
745 android_usb_pdata.serial_number = serialno;
746 return 1;
747}
748__setup("androidboot.serialno=", board_serialno_setup);
749#endif
750
751#ifdef CONFIG_MSM_VPE
752static struct resource msm_vpe_resources[] = {
753 {
754 .start = 0x05300000,
755 .end = 0x05300000 + SZ_1M - 1,
756 .flags = IORESOURCE_MEM,
757 },
758 {
759 .start = INT_VPE,
760 .end = INT_VPE,
761 .flags = IORESOURCE_IRQ,
762 },
763};
764
765static struct platform_device msm_vpe_device = {
766 .name = "msm_vpe",
767 .id = 0,
768 .num_resources = ARRAY_SIZE(msm_vpe_resources),
769 .resource = msm_vpe_resources,
770};
771#endif
772
773#ifdef CONFIG_MSM_GEMINI
774static struct resource msm_gemini_resources[] = {
775 {
776 .start = 0x04600000,
777 .end = 0x04600000 + SZ_1M - 1,
778 .flags = IORESOURCE_MEM,
779 },
780 {
781 .start = INT_JPEG,
782 .end = INT_JPEG,
783 .flags = IORESOURCE_IRQ,
784 },
785};
786
787static struct platform_device msm_gemini_device = {
788 .name = "msm_gemini",
789 .resource = msm_gemini_resources,
790 .num_resources = ARRAY_SIZE(msm_gemini_resources),
791};
792#endif
793
794#ifdef CONFIG_I2C_QUP
795static void gsbi_qup_i2c_gpio_config(int adap_id, int config_type)
796{
797}
798
799static struct msm_i2c_platform_data msm_gsbi3_qup_i2c_pdata = {
800 .clk_freq = 100000,
801 .src_clk_rate = 24000000,
802 .clk = "gsbi_qup_clk",
803 .pclk = "gsbi_pclk",
804 .use_gsbi_shared_mode = 1,
805 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
806};
807
808static struct msm_i2c_platform_data msm_gsbi4_qup_i2c_pdata = {
809 .clk_freq = 100000,
810 .src_clk_rate = 24000000,
811 .clk = "gsbi_qup_clk",
812 .pclk = "gsbi_pclk",
813 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
814};
815
816static struct msm_i2c_platform_data msm_gsbi7_qup_i2c_pdata = {
817 .clk_freq = 100000,
818 .src_clk_rate = 24000000,
819 .clk = "gsbi_qup_clk",
820 .pclk = "gsbi_pclk",
821 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
822};
823
824static struct msm_i2c_platform_data msm_gsbi8_qup_i2c_pdata = {
825 .clk_freq = 100000,
826 .src_clk_rate = 24000000,
827 .clk = "gsbi_qup_clk",
828 .pclk = "gsbi_pclk",
829 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
830};
831
832static struct msm_i2c_platform_data msm_gsbi9_qup_i2c_pdata = {
833 .clk_freq = 100000,
834 .src_clk_rate = 24000000,
835 .clk = "gsbi_qup_clk",
836 .pclk = "gsbi_pclk",
837 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
838};
839#endif
840
841#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
842static struct msm_spi_platform_data msm_gsbi1_qup_spi_pdata = {
843 .max_clock_speed = 24000000,
844 .clk_name = "gsbi_qup_clk",
845 .pclk_name = "gsbi_pclk",
846};
847#endif
848
849#ifdef CONFIG_I2C_SSBI
850/* PMIC SSBI */
851static struct msm_ssbi_platform_data msm_ssbi1_pdata = {
852 .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
853};
854
855/* PMIC SSBI */
856static struct msm_ssbi_platform_data msm_ssbi2_pdata = {
857 .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
858};
859
860/* CODEC/TSSC SSBI */
861static struct msm_ssbi_platform_data msm_ssbi3_pdata = {
862 .controller_type = MSM_SBI_CTRL_SSBI,
863};
864#endif
865
866#ifdef CONFIG_BATTERY_MSM
867/* Use basic value for fake MSM battery */
868static struct msm_psy_batt_pdata msm_psy_batt_data = {
869 .avail_chg_sources = AC_CHG,
870};
871
872static struct platform_device msm_batt_device = {
873 .name = "msm-battery",
874 .id = -1,
875 .dev.platform_data = &msm_psy_batt_data,
876};
877#endif
878
879#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
880/* prim = 1366 (rounds up to 1376) x 768 x 4(bpp) x 2(pages)
881 * hdmi = 1920 x 1080 x 2(bpp) x 1(page)
882 * Note: must be multiple of 4096 */
883#define MSM_FB_SIZE 0xC08000
884#else /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
885#define MSM_FB_SIZE 0x811000
886#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
887#define MSM_PMEM_SF_SIZE 0x1700000
888
889#define MSM_PMEM_KERNEL_EBI1_SIZE 0x600000
890#define MSM_PMEM_ADSP_SIZE 0x2000000
891
892#define MSM_SMI_BASE 0x38000000
893/* Kernel SMI PMEM Region for video core, used for Firmware */
894/* and encoder,decoder scratch buffers */
895/* Kernel SMI PMEM Region Should always precede the user space */
896/* SMI PMEM Region, as the video core will use offset address */
897/* from the Firmware base */
898#define PMEM_KERNEL_SMI_BASE (MSM_SMI_BASE)
899#define PMEM_KERNEL_SMI_SIZE 0x1000000
900/* User space SMI PMEM Region for video core*/
901/* used for encoder, decoder input & output buffers */
902#define MSM_PMEM_SMIPOOL_BASE (PMEM_KERNEL_SMI_BASE + PMEM_KERNEL_SMI_SIZE)
903#define MSM_PMEM_SMIPOOL_SIZE 0x2800000
904
905static unsigned fb_size = MSM_FB_SIZE;
906static int __init fb_size_setup(char *p)
907{
908 fb_size = memparse(p, NULL);
909 return 0;
910}
911early_param("fb_size", fb_size_setup);
912
913#ifdef CONFIG_KERNEL_PMEM_EBI_REGION
914static unsigned pmem_kernel_ebi1_size = MSM_PMEM_KERNEL_EBI1_SIZE;
915static int __init pmem_kernel_ebi1_size_setup(char *p)
916{
917 pmem_kernel_ebi1_size = memparse(p, NULL);
918 return 0;
919}
920early_param("pmem_kernel_ebi1_size", pmem_kernel_ebi1_size_setup);
921#endif
922
923#ifdef CONFIG_ANDROID_PMEM
924static unsigned pmem_sf_size = MSM_PMEM_SF_SIZE;
925static int __init pmem_sf_size_setup(char *p)
926{
927 pmem_sf_size = memparse(p, NULL);
928 return 0;
929}
930early_param("pmem_sf_size", pmem_sf_size_setup);
931
932static unsigned pmem_adsp_size = MSM_PMEM_ADSP_SIZE;
933
934static int __init pmem_adsp_size_setup(char *p)
935{
936 pmem_adsp_size = memparse(p, NULL);
937 return 0;
938}
939early_param("pmem_adsp_size", pmem_adsp_size_setup);
940#endif
941
942static struct resource msm_fb_resources[] = {
943 {
944 .flags = IORESOURCE_DMA,
945 }
946};
947
948static int msm_fb_detect_panel(const char *name)
949{
950#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
951 if (!strcmp(name, "hdmi_msm"))
952 return 0;
953#endif
954 if (!strcmp(name, "lcdc_qrdc"))
955 return 0;
956 pr_warning("%s: not supported '%s'", __func__, name);
957 return -ENODEV;
958}
959
960static void lcd_panel_power(int on);
961static int msm_fb_lcdc_gpio_config(int on);
962static int vga_enabled;
963static int vga_enable(int select_vga)
964{
965 int rc = 0;
966
967 vga_enabled = select_vga;
968 rc = msm_fb_lcdc_gpio_config(1);
969 if (rc)
970 return rc;
971 lcd_panel_power(1);
972
973 return 0;
974}
975
976static struct msm_panel_common_pdata lcdc_qrdc_panel_data = {
977 .vga_switch = vga_enable,
978};
979
980static struct platform_device lcdc_qrdc_panel_device = {
981 .name = "lcdc_qrdc",
982 .id = 0,
983 .dev = {
984 .platform_data = &lcdc_qrdc_panel_data,
985 }
986};
987
988static struct msm_fb_platform_data msm_fb_pdata = {
989 .detect_client = msm_fb_detect_panel,
990};
991
992static struct platform_device msm_fb_device = {
993 .name = "msm_fb",
994 .id = 0,
995 .num_resources = ARRAY_SIZE(msm_fb_resources),
996 .resource = msm_fb_resources,
997 .dev = {
998 .platform_data = &msm_fb_pdata,
999 }
1000};
1001
1002#ifdef CONFIG_KERNEL_PMEM_EBI_REGION
1003static struct android_pmem_platform_data android_pmem_kernel_ebi1_pdata = {
1004 .name = PMEM_KERNEL_EBI1_DATA_NAME,
1005 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
1006 .cached = 0,
1007};
1008
1009static struct platform_device android_pmem_kernel_ebi1_device = {
1010 .name = "android_pmem",
1011 .id = 1,
1012 .dev = { .platform_data = &android_pmem_kernel_ebi1_pdata },
1013};
1014#endif
1015
1016#ifdef CONFIG_KERNEL_PMEM_SMI_REGION
1017static struct android_pmem_platform_data android_pmem_kernel_smi_pdata = {
1018 .name = PMEM_KERNEL_SMI_DATA_NAME,
1019 /* defaults to bitmap don't edit */
1020 .cached = 0,
1021};
1022
1023static struct platform_device android_pmem_kernel_smi_device = {
1024 .name = "android_pmem",
1025 .id = 6,
1026 .dev = { .platform_data = &android_pmem_kernel_smi_pdata },
1027};
1028#endif
1029
1030#ifdef CONFIG_ANDROID_PMEM
1031static struct android_pmem_platform_data android_pmem_pdata = {
1032 .name = "pmem",
1033 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
1034 .cached = 0,
1035};
1036
1037static struct platform_device android_pmem_device = {
1038 .name = "android_pmem",
1039 .id = 0,
1040 .dev = {.platform_data = &android_pmem_pdata},
1041};
1042
1043static struct android_pmem_platform_data android_pmem_adsp_pdata = {
1044 .name = "pmem_adsp",
1045 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
1046 .cached = 0,
1047};
1048
1049static struct platform_device android_pmem_adsp_device = {
1050 .name = "android_pmem",
1051 .id = 2,
1052 .dev = { .platform_data = &android_pmem_adsp_pdata },
1053};
1054static struct android_pmem_platform_data android_pmem_smipool_pdata = {
1055 .name = "pmem_smipool",
1056 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
1057 .cached = 0,
1058};
1059static struct platform_device android_pmem_smipool_device = {
1060 .name = "android_pmem",
1061 .id = 7,
1062 .dev = { .platform_data = &android_pmem_smipool_pdata },
1063};
1064
1065#endif
1066
1067#define GPIO_BACKLIGHT_PWM0 0
1068#define GPIO_BACKLIGHT_PWM1 1
1069
1070static int pmic_backlight_gpio[2]
1071 = { GPIO_BACKLIGHT_PWM0, GPIO_BACKLIGHT_PWM1 };
1072static struct msm_panel_common_pdata lcdc_samsung_panel_data = {
1073 .gpio_num = pmic_backlight_gpio, /* two LPG CHANNELS for backlight */
1074};
1075
1076static struct platform_device lcdc_samsung_panel_device = {
1077 .name = "lcdc_samsung_wsvga",
1078 .id = 0,
1079 .dev = {
1080 .platform_data = &lcdc_samsung_panel_data,
1081 }
1082};
1083
1084#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
1085static struct resource hdmi_msm_resources[] = {
1086 {
1087 .name = "hdmi_msm_qfprom_addr",
1088 .start = 0x00700000,
1089 .end = 0x007060FF,
1090 .flags = IORESOURCE_MEM,
1091 },
1092 {
1093 .name = "hdmi_msm_hdmi_addr",
1094 .start = 0x04A00000,
1095 .end = 0x04A00FFF,
1096 .flags = IORESOURCE_MEM,
1097 },
1098 {
1099 .name = "hdmi_msm_irq",
1100 .start = HDMI_IRQ,
1101 .end = HDMI_IRQ,
1102 .flags = IORESOURCE_IRQ,
1103 },
1104};
1105
1106static int hdmi_enable_5v(int on);
1107static int hdmi_core_power(int on, int show);
1108static int hdmi_cec_power(int on);
1109
1110static struct msm_hdmi_platform_data hdmi_msm_data = {
1111 .irq = HDMI_IRQ,
1112 .enable_5v = hdmi_enable_5v,
1113 .core_power = hdmi_core_power,
1114 .cec_power = hdmi_cec_power,
1115};
1116
1117static struct platform_device hdmi_msm_device = {
1118 .name = "hdmi_msm",
1119 .id = 0,
1120 .num_resources = ARRAY_SIZE(hdmi_msm_resources),
1121 .resource = hdmi_msm_resources,
1122 .dev.platform_data = &hdmi_msm_data,
1123};
1124#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
1125
1126static struct platform_device mipi_dsi_video_toshiba_wvga_panel_device = {
1127 .name = "dsi_video_toshiba_wvga",
1128 .id = 0,
1129};
1130
1131static void __init msm8x60_allocate_memory_regions(void)
1132{
1133 void *addr;
1134 unsigned long size;
1135
1136 size = MSM_FB_SIZE;
1137 addr = alloc_bootmem(size);
1138 msm_fb_resources[0].start = __pa(addr);
1139 msm_fb_resources[0].end = msm_fb_resources[0].start + size - 1;
1140 pr_info("allocating %lu bytes at %p (%lx physical) for fb\n",
1141 size, addr, __pa(addr));
1142
1143#ifdef CONFIG_KERNEL_PMEM_EBI_REGION
1144 size = pmem_kernel_ebi1_size;
1145 if (size) {
1146 addr = alloc_bootmem_aligned(size, 0x100000);
1147 android_pmem_kernel_ebi1_pdata.start = __pa(addr);
1148 android_pmem_kernel_ebi1_pdata.size = size;
1149 pr_info("allocating %lu bytes at %p (%lx physical) for kernel"
1150 " ebi1 pmem arena\n", size, addr, __pa(addr));
1151 }
1152#endif
1153
1154#ifdef CONFIG_KERNEL_PMEM_SMI_REGION
1155 size = PMEM_KERNEL_SMI_SIZE;
1156 if (size) {
1157 android_pmem_kernel_smi_pdata.start = PMEM_KERNEL_SMI_BASE;
1158 android_pmem_kernel_smi_pdata.size = size;
1159 pr_info("allocating %lu bytes at %lx physical for kernel"
1160 " smi pmem arena\n", size,
1161 (unsigned long) PMEM_KERNEL_SMI_BASE);
1162 }
1163#endif
1164
1165#ifdef CONFIG_ANDROID_PMEM
1166 size = pmem_adsp_size;
1167 if (size) {
1168 addr = alloc_bootmem(size);
1169 android_pmem_adsp_pdata.start = __pa(addr);
1170 android_pmem_adsp_pdata.size = size;
1171 pr_info("allocating %lu bytes at %p (%lx physical) for adsp "
1172 "pmem arena\n", size, addr, __pa(addr));
1173 }
1174
1175 size = MSM_PMEM_SMIPOOL_SIZE;
1176 if (size) {
1177 android_pmem_smipool_pdata.start = MSM_PMEM_SMIPOOL_BASE;
1178 android_pmem_smipool_pdata.size = size;
1179 pr_info("allocating %lu bytes at %lx physical for user"
1180 " smi pmem arena\n", size,
1181 (unsigned long) MSM_PMEM_SMIPOOL_BASE);
1182 }
1183
1184 size = pmem_sf_size;
1185 if (size) {
1186 addr = alloc_bootmem(size);
1187 android_pmem_pdata.start = __pa(addr);
1188 android_pmem_pdata.size = size;
1189 pr_info("allocating %lu bytes at %p (%lx physical) for sf "
1190 "pmem arena\n", size, addr, __pa(addr));
1191 }
1192#endif
1193}
1194
1195#ifdef CONFIG_SERIAL_MSM_HS
1196static struct msm_serial_hs_platform_data msm_uart_dm1_pdata = {
1197 .inject_rx_on_wakeup = 1,
1198 .rx_to_inject = 0xFD,
1199};
1200#endif
1201
1202#if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
1203
1204static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
1205 .phys_addr_base = 0x00106000,
1206 .reg_offsets = {
1207 [MSM_RPM_LOG_PAGE_INDICES] = 0x00000C80,
1208 [MSM_RPM_LOG_PAGE_BUFFER] = 0x00000CA0,
1209 },
1210 .phys_size = SZ_8K,
1211 .log_len = 4096, /* log's buffer length in bytes */
1212 .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
1213};
1214static struct platform_device msm_rpm_log_device = {
1215 .name = "msm_rpm_log",
1216 .id = -1,
1217 .dev = {
1218 .platform_data = &msm_rpm_log_pdata,
1219 },
1220};
1221#endif
1222
1223static struct regulator_consumer_supply rpm_vreg_supply[RPM_VREG_ID_MAX] = {
1224 [RPM_VREG_ID_PM8058_L0] = REGULATOR_SUPPLY("8058_l0", NULL),
1225 [RPM_VREG_ID_PM8058_L1] = REGULATOR_SUPPLY("8058_l1", NULL),
1226 [RPM_VREG_ID_PM8058_L2] = REGULATOR_SUPPLY("8058_l2", NULL),
1227 [RPM_VREG_ID_PM8058_L3] = REGULATOR_SUPPLY("8058_l3", NULL),
1228 [RPM_VREG_ID_PM8058_L4] = REGULATOR_SUPPLY("8058_l4", NULL),
1229 [RPM_VREG_ID_PM8058_L5] = REGULATOR_SUPPLY("8058_l5", NULL),
1230 [RPM_VREG_ID_PM8058_L6] = REGULATOR_SUPPLY("8058_l6", NULL),
1231 [RPM_VREG_ID_PM8058_L7] = REGULATOR_SUPPLY("8058_l7", NULL),
1232 [RPM_VREG_ID_PM8058_L8] = REGULATOR_SUPPLY("8058_l8", NULL),
1233 [RPM_VREG_ID_PM8058_L9] = REGULATOR_SUPPLY("8058_l9", NULL),
1234 [RPM_VREG_ID_PM8058_L10] = REGULATOR_SUPPLY("8058_l10", NULL),
1235 [RPM_VREG_ID_PM8058_L11] = REGULATOR_SUPPLY("8058_l11", NULL),
1236 [RPM_VREG_ID_PM8058_L12] = REGULATOR_SUPPLY("8058_l12", NULL),
1237 [RPM_VREG_ID_PM8058_L13] = REGULATOR_SUPPLY("8058_l13", NULL),
1238 [RPM_VREG_ID_PM8058_L14] = REGULATOR_SUPPLY("8058_l14", NULL),
1239 [RPM_VREG_ID_PM8058_L15] = REGULATOR_SUPPLY("8058_l15", NULL),
1240 [RPM_VREG_ID_PM8058_L16] = REGULATOR_SUPPLY("8058_l16", NULL),
1241 [RPM_VREG_ID_PM8058_L17] = REGULATOR_SUPPLY("8058_l17", NULL),
1242 [RPM_VREG_ID_PM8058_L18] = REGULATOR_SUPPLY("8058_l18", NULL),
1243 [RPM_VREG_ID_PM8058_L19] = REGULATOR_SUPPLY("8058_l19", NULL),
1244 [RPM_VREG_ID_PM8058_L20] = REGULATOR_SUPPLY("8058_l20", NULL),
1245 [RPM_VREG_ID_PM8058_L21] = REGULATOR_SUPPLY("8058_l21", NULL),
1246 [RPM_VREG_ID_PM8058_L22] = REGULATOR_SUPPLY("8058_l22", NULL),
1247 [RPM_VREG_ID_PM8058_L23] = REGULATOR_SUPPLY("8058_l23", NULL),
1248 [RPM_VREG_ID_PM8058_L24] = REGULATOR_SUPPLY("8058_l24", NULL),
1249 [RPM_VREG_ID_PM8058_L25] = REGULATOR_SUPPLY("8058_l25", NULL),
1250
1251 [RPM_VREG_ID_PM8058_S0] = REGULATOR_SUPPLY("8058_s0", NULL),
1252 [RPM_VREG_ID_PM8058_S1] = REGULATOR_SUPPLY("8058_s1", NULL),
1253 [RPM_VREG_ID_PM8058_S2] = REGULATOR_SUPPLY("8058_s2", NULL),
1254 [RPM_VREG_ID_PM8058_S3] = REGULATOR_SUPPLY("8058_s3", NULL),
1255 [RPM_VREG_ID_PM8058_S4] = REGULATOR_SUPPLY("8058_s4", NULL),
1256
1257 [RPM_VREG_ID_PM8058_LVS0] = REGULATOR_SUPPLY("8058_lvs0", NULL),
1258 [RPM_VREG_ID_PM8058_LVS1] = REGULATOR_SUPPLY("8058_lvs1", NULL),
1259
1260 [RPM_VREG_ID_PM8058_NCP] = REGULATOR_SUPPLY("8058_ncp", NULL),
1261
1262 [RPM_VREG_ID_PM8901_L0] = REGULATOR_SUPPLY("8901_l0", NULL),
1263 [RPM_VREG_ID_PM8901_L1] = REGULATOR_SUPPLY("8901_l1", NULL),
1264 [RPM_VREG_ID_PM8901_L2] = REGULATOR_SUPPLY("8901_l2", NULL),
1265 [RPM_VREG_ID_PM8901_L3] = REGULATOR_SUPPLY("8901_l3", NULL),
1266 [RPM_VREG_ID_PM8901_L4] = REGULATOR_SUPPLY("8901_l4", NULL),
1267 [RPM_VREG_ID_PM8901_L5] = REGULATOR_SUPPLY("8901_l5", NULL),
1268 [RPM_VREG_ID_PM8901_L6] = REGULATOR_SUPPLY("8901_l6", NULL),
1269
1270 [RPM_VREG_ID_PM8901_S2] = REGULATOR_SUPPLY("8901_s2", NULL),
1271 [RPM_VREG_ID_PM8901_S3] = REGULATOR_SUPPLY("8901_s3", NULL),
1272 [RPM_VREG_ID_PM8901_S4] = REGULATOR_SUPPLY("8901_s4", NULL),
1273
1274 [RPM_VREG_ID_PM8901_LVS0] = REGULATOR_SUPPLY("8901_lvs0", NULL),
1275 [RPM_VREG_ID_PM8901_LVS1] = REGULATOR_SUPPLY("8901_lvs1", NULL),
1276 [RPM_VREG_ID_PM8901_LVS2] = REGULATOR_SUPPLY("8901_lvs2", NULL),
1277 [RPM_VREG_ID_PM8901_LVS3] = REGULATOR_SUPPLY("8901_lvs3", NULL),
1278 [RPM_VREG_ID_PM8901_MVS0] = REGULATOR_SUPPLY("8901_mvs0", NULL),
1279};
1280
1281#define RPM_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \
1282 _default_uV, _peak_uA, _avg_uA, _pull_down, _pin_ctrl, \
1283 _freq, _pin_fn, _rpm_mode, _state, _sleep_selectable, \
1284 _always_on) \
1285 [RPM_VREG_ID_##_id] = { \
1286 .init_data = { \
1287 .constraints = { \
1288 .valid_modes_mask = _modes, \
1289 .valid_ops_mask = _ops, \
1290 .min_uV = _min_uV, \
1291 .max_uV = _max_uV, \
1292 .input_uV = _min_uV, \
1293 .apply_uV = _apply_uV, \
1294 .always_on = _always_on, \
1295 }, \
1296 .num_consumer_supplies = 1, \
1297 .consumer_supplies = \
1298 &rpm_vreg_supply[RPM_VREG_ID_##_id], \
1299 }, \
1300 .default_uV = _default_uV, \
1301 .peak_uA = _peak_uA, \
1302 .avg_uA = _avg_uA, \
1303 .pull_down_enable = _pull_down, \
1304 .pin_ctrl = _pin_ctrl, \
1305 .freq = _freq, \
1306 .pin_fn = _pin_fn, \
1307 .mode = _rpm_mode, \
1308 .state = _state, \
1309 .sleep_selectable = _sleep_selectable, \
1310 }
1311
1312/*
1313 * The default LPM/HPM state of an RPM controlled regulator can be controlled
1314 * via the peak_uA value specified in the table below. If the value is less
1315 * than the low power threshold for the regulator, then the regulator will be
1316 * set to LPM. Otherwise, it will be set to HPM.
1317 *
1318 * This value can be further overridden by specifying an initial mode via
1319 * .init_data.constraints.initial_mode.
1320 */
1321
1322#define RPM_VREG_INIT_LDO(_id, _always_on, _pd, _sleep_selectable, _min_uV, \
1323 _max_uV, _init_peak_uA, _pin_ctrl) \
1324 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
1325 REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
1326 REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
1327 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
1328 REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
1329 _init_peak_uA, _pd, _pin_ctrl, RPM_VREG_FREQ_NONE, \
1330 RPM_VREG_PIN_FN_ENABLE, RPM_VREG_MODE_NONE, \
1331 RPM_VREG_STATE_OFF, _sleep_selectable, _always_on)
1332
1333#define RPM_VREG_INIT_LDO_PF(_id, _always_on, _pd, _sleep_selectable, _min_uV, \
1334 _max_uV, _init_peak_uA, _pin_ctrl, _pin_fn) \
1335 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
1336 REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
1337 REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
1338 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
1339 REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
1340 _init_peak_uA, _pd, _pin_ctrl, RPM_VREG_FREQ_NONE, \
1341 _pin_fn, RPM_VREG_MODE_NONE, RPM_VREG_STATE_OFF, \
1342 _sleep_selectable, _always_on)
1343
1344#define RPM_VREG_INIT_SMPS(_id, _always_on, _pd, _sleep_selectable, _min_uV, \
1345 _max_uV, _init_peak_uA, _pin_ctrl, _freq) \
1346 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
1347 REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
1348 REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
1349 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
1350 REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
1351 _init_peak_uA, _pd, _pin_ctrl, _freq, \
1352 RPM_VREG_PIN_FN_ENABLE, RPM_VREG_MODE_NONE, \
1353 RPM_VREG_STATE_OFF, _sleep_selectable, _always_on)
1354
1355#define RPM_VREG_INIT_VS(_id, _always_on, _pd, _sleep_selectable, _pin_ctrl) \
1356 RPM_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE, \
1357 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE, 0, 0, \
1358 1000, 1000, _pd, _pin_ctrl, RPM_VREG_FREQ_NONE, \
1359 RPM_VREG_PIN_FN_ENABLE, RPM_VREG_MODE_NONE, \
1360 RPM_VREG_STATE_OFF, _sleep_selectable, _always_on)
1361
1362#define RPM_VREG_INIT_NCP(_id, _always_on, _pd, _sleep_selectable, _min_uV, \
1363 _max_uV, _pin_ctrl) \
1364 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL, \
1365 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, 0, \
1366 _min_uV, 1000, 1000, _pd, _pin_ctrl, RPM_VREG_FREQ_NONE, \
1367 RPM_VREG_PIN_FN_ENABLE, RPM_VREG_MODE_NONE, \
1368 RPM_VREG_STATE_OFF, _sleep_selectable, _always_on)
1369
1370#define LDO50HMIN RPM_VREG_LDO_50_HPM_MIN_LOAD
1371#define LDO150HMIN RPM_VREG_LDO_150_HPM_MIN_LOAD
1372#define LDO300HMIN RPM_VREG_LDO_300_HPM_MIN_LOAD
1373#define SMPS_HMIN RPM_VREG_SMPS_HPM_MIN_LOAD
1374#define FTS_HMIN RPM_VREG_FTSMPS_HPM_MIN_LOAD
1375
1376static struct rpm_vreg_pdata rpm_vreg_init_pdata[RPM_VREG_ID_MAX] = {
1377 RPM_VREG_INIT_LDO_PF(PM8058_L0, 0, 1, 0, 1200000, 1200000, LDO150HMIN,
1378 RPM_VREG_PIN_CTRL_NONE, RPM_VREG_PIN_FN_SLEEP_B),
1379 RPM_VREG_INIT_LDO(PM8058_L1, 0, 1, 0, 1200000, 1200000, LDO300HMIN, 0),
1380 RPM_VREG_INIT_LDO(PM8058_L2, 0, 1, 0, 1800000, 2600000, LDO300HMIN, 0),
1381 RPM_VREG_INIT_LDO(PM8058_L3, 0, 1, 0, 1800000, 1800000, LDO150HMIN, 0),
1382 RPM_VREG_INIT_LDO(PM8058_L4, 0, 1, 0, 2850000, 2850000, LDO50HMIN, 0),
1383 RPM_VREG_INIT_LDO(PM8058_L5, 0, 1, 0, 2850000, 2850000, LDO300HMIN, 0),
1384 RPM_VREG_INIT_LDO(PM8058_L6, 0, 1, 0, 3000000, 3600000, LDO50HMIN, 0),
1385 RPM_VREG_INIT_LDO(PM8058_L7, 0, 1, 0, 1800000, 1800000, LDO50HMIN, 0),
1386 RPM_VREG_INIT_LDO(PM8058_L8, 0, 1, 0, 2900000, 3050000, LDO300HMIN, 0),
1387 RPM_VREG_INIT_LDO(PM8058_L9, 0, 1, 0, 1800000, 1800000, LDO300HMIN, 0),
1388 RPM_VREG_INIT_LDO(PM8058_L10, 0, 1, 0, 2600000, 2600000, LDO300HMIN, 0),
1389 RPM_VREG_INIT_LDO(PM8058_L11, 0, 1, 0, 1500000, 1500000, LDO150HMIN, 0),
1390 RPM_VREG_INIT_LDO(PM8058_L12, 0, 1, 0, 2900000, 2900000, LDO150HMIN, 0),
1391 RPM_VREG_INIT_LDO(PM8058_L13, 0, 1, 0, 2050000, 2050000, LDO300HMIN, 0),
1392 RPM_VREG_INIT_LDO(PM8058_L14, 0, 0, 0, 2850000, 2850000, LDO300HMIN, 0),
1393 RPM_VREG_INIT_LDO(PM8058_L15, 0, 1, 0, 2850000, 2850000, LDO300HMIN, 0),
1394 RPM_VREG_INIT_LDO(PM8058_L16, 1, 1, 1, 1800000, 1800000, LDO300HMIN, 0),
1395 RPM_VREG_INIT_LDO(PM8058_L17, 0, 1, 0, 2600000, 2600000, LDO150HMIN, 0),
1396 RPM_VREG_INIT_LDO(PM8058_L18, 0, 1, 1, 2200000, 2200000, LDO150HMIN, 0),
1397 RPM_VREG_INIT_LDO(PM8058_L19, 0, 1, 0, 2500000, 2500000, LDO150HMIN, 0),
1398 RPM_VREG_INIT_LDO(PM8058_L20, 0, 1, 0, 1800000, 1800000, LDO150HMIN, 0),
1399 RPM_VREG_INIT_LDO_PF(PM8058_L21, 1, 1, 0, 1200000, 1200000, LDO150HMIN,
1400 RPM_VREG_PIN_CTRL_NONE, RPM_VREG_PIN_FN_SLEEP_B),
1401 RPM_VREG_INIT_LDO(PM8058_L22, 0, 1, 0, 1200000, 1200000, LDO300HMIN, 0),
1402 RPM_VREG_INIT_LDO(PM8058_L23, 0, 1, 0, 1200000, 1200000, LDO300HMIN, 0),
1403 RPM_VREG_INIT_LDO(PM8058_L24, 0, 1, 0, 1200000, 1200000, LDO150HMIN, 0),
1404 RPM_VREG_INIT_LDO(PM8058_L25, 0, 1, 0, 1200000, 1200000, LDO150HMIN, 0),
1405
1406 RPM_VREG_INIT_SMPS(PM8058_S0, 0, 1, 1, 500000, 1200000, SMPS_HMIN, 0,
1407 RPM_VREG_FREQ_1p75),
1408 RPM_VREG_INIT_SMPS(PM8058_S1, 0, 1, 1, 500000, 1200000, SMPS_HMIN, 0,
1409 RPM_VREG_FREQ_1p75),
1410 RPM_VREG_INIT_SMPS(PM8058_S2, 0, 1, 0, 1200000, 1400000, SMPS_HMIN,
1411 RPM_VREG_PIN_CTRL_A0, RPM_VREG_FREQ_1p75),
1412 RPM_VREG_INIT_SMPS(PM8058_S3, 1, 1, 0, 1800000, 1800000, SMPS_HMIN, 0,
1413 RPM_VREG_FREQ_1p75),
1414 RPM_VREG_INIT_SMPS(PM8058_S4, 1, 1, 0, 2200000, 2200000, SMPS_HMIN, 0,
1415 RPM_VREG_FREQ_1p75),
1416
1417 RPM_VREG_INIT_VS(PM8058_LVS0, 0, 1, 0, 0),
1418 RPM_VREG_INIT_VS(PM8058_LVS1, 0, 1, 0, 0),
1419
1420 RPM_VREG_INIT_NCP(PM8058_NCP, 0, 1, 0, 1800000, 1800000, 0),
1421
1422 RPM_VREG_INIT_LDO(PM8901_L0, 0, 1, 0, 1200000, 1200000, LDO300HMIN,
1423 RPM_VREG_PIN_CTRL_A0),
1424 RPM_VREG_INIT_LDO(PM8901_L1, 0, 1, 0, 3300000, 3300000, LDO300HMIN, 0),
1425 RPM_VREG_INIT_LDO(PM8901_L2, 0, 1, 0, 2850000, 3300000, LDO300HMIN, 0),
1426 RPM_VREG_INIT_LDO(PM8901_L3, 0, 1, 0, 3300000, 3300000, LDO300HMIN, 0),
1427 RPM_VREG_INIT_LDO(PM8901_L4, 0, 1, 0, 2600000, 2600000, LDO300HMIN, 0),
1428 RPM_VREG_INIT_LDO(PM8901_L5, 0, 1, 0, 2850000, 2850000, LDO300HMIN, 0),
1429 RPM_VREG_INIT_LDO(PM8901_L6, 0, 1, 0, 2200000, 2200000, LDO300HMIN, 0),
1430
1431 RPM_VREG_INIT_SMPS(PM8901_S2, 0, 1, 0, 1300000, 1300000, FTS_HMIN, 0,
1432 RPM_VREG_FREQ_1p75),
1433 RPM_VREG_INIT_SMPS(PM8901_S3, 0, 1, 0, 1100000, 1100000, FTS_HMIN, 0,
1434 RPM_VREG_FREQ_1p75),
1435 RPM_VREG_INIT_SMPS(PM8901_S4, 0, 1, 0, 1225000, 1225000, FTS_HMIN,
1436 RPM_VREG_PIN_CTRL_A0, RPM_VREG_FREQ_1p75),
1437
1438 RPM_VREG_INIT_VS(PM8901_LVS0, 1, 1, 0, 0),
1439 RPM_VREG_INIT_VS(PM8901_LVS1, 0, 1, 0, 0),
1440 RPM_VREG_INIT_VS(PM8901_LVS2, 0, 1, 0, 0),
1441 RPM_VREG_INIT_VS(PM8901_LVS3, 0, 1, 0, 0),
1442 RPM_VREG_INIT_VS(PM8901_MVS0, 0, 1, 0, 0),
1443};
1444
1445#define RPM_VREG(_id) \
1446 [_id] = { \
1447 .name = "rpm-regulator", \
1448 .id = _id, \
1449 .dev = { \
1450 .platform_data = &rpm_vreg_init_pdata[_id], \
1451 }, \
1452 }
1453
1454static struct platform_device rpm_vreg_device[RPM_VREG_ID_MAX] = {
1455 RPM_VREG(RPM_VREG_ID_PM8058_L0),
1456 RPM_VREG(RPM_VREG_ID_PM8058_L1),
1457 RPM_VREG(RPM_VREG_ID_PM8058_L2),
1458 RPM_VREG(RPM_VREG_ID_PM8058_L3),
1459 RPM_VREG(RPM_VREG_ID_PM8058_L4),
1460 RPM_VREG(RPM_VREG_ID_PM8058_L5),
1461 RPM_VREG(RPM_VREG_ID_PM8058_L6),
1462 RPM_VREG(RPM_VREG_ID_PM8058_L7),
1463 RPM_VREG(RPM_VREG_ID_PM8058_L8),
1464 RPM_VREG(RPM_VREG_ID_PM8058_L9),
1465 RPM_VREG(RPM_VREG_ID_PM8058_L10),
1466 RPM_VREG(RPM_VREG_ID_PM8058_L11),
1467 RPM_VREG(RPM_VREG_ID_PM8058_L12),
1468 RPM_VREG(RPM_VREG_ID_PM8058_L13),
1469 RPM_VREG(RPM_VREG_ID_PM8058_L14),
1470 RPM_VREG(RPM_VREG_ID_PM8058_L15),
1471 RPM_VREG(RPM_VREG_ID_PM8058_L16),
1472 RPM_VREG(RPM_VREG_ID_PM8058_L17),
1473 RPM_VREG(RPM_VREG_ID_PM8058_L18),
1474 RPM_VREG(RPM_VREG_ID_PM8058_L19),
1475 RPM_VREG(RPM_VREG_ID_PM8058_L20),
1476 RPM_VREG(RPM_VREG_ID_PM8058_L21),
1477 RPM_VREG(RPM_VREG_ID_PM8058_L22),
1478 RPM_VREG(RPM_VREG_ID_PM8058_L23),
1479 RPM_VREG(RPM_VREG_ID_PM8058_L24),
1480 RPM_VREG(RPM_VREG_ID_PM8058_L25),
1481 RPM_VREG(RPM_VREG_ID_PM8058_S0),
1482 RPM_VREG(RPM_VREG_ID_PM8058_S1),
1483 RPM_VREG(RPM_VREG_ID_PM8058_S2),
1484 RPM_VREG(RPM_VREG_ID_PM8058_S3),
1485 RPM_VREG(RPM_VREG_ID_PM8058_S4),
1486 RPM_VREG(RPM_VREG_ID_PM8058_LVS0),
1487 RPM_VREG(RPM_VREG_ID_PM8058_LVS1),
1488 RPM_VREG(RPM_VREG_ID_PM8058_NCP),
1489 RPM_VREG(RPM_VREG_ID_PM8901_L0),
1490 RPM_VREG(RPM_VREG_ID_PM8901_L1),
1491 RPM_VREG(RPM_VREG_ID_PM8901_L2),
1492 RPM_VREG(RPM_VREG_ID_PM8901_L3),
1493 RPM_VREG(RPM_VREG_ID_PM8901_L4),
1494 RPM_VREG(RPM_VREG_ID_PM8901_L5),
1495 RPM_VREG(RPM_VREG_ID_PM8901_L6),
1496 RPM_VREG(RPM_VREG_ID_PM8901_S2),
1497 RPM_VREG(RPM_VREG_ID_PM8901_S3),
1498 RPM_VREG(RPM_VREG_ID_PM8901_S4),
1499 RPM_VREG(RPM_VREG_ID_PM8901_LVS0),
1500 RPM_VREG(RPM_VREG_ID_PM8901_LVS1),
1501 RPM_VREG(RPM_VREG_ID_PM8901_LVS2),
1502 RPM_VREG(RPM_VREG_ID_PM8901_LVS3),
1503 RPM_VREG(RPM_VREG_ID_PM8901_MVS0),
1504};
1505
1506static struct platform_device *early_regulators[] __initdata = {
1507 &msm_device_saw_s0,
1508 &msm_device_saw_s1,
1509#ifdef CONFIG_PMIC8058
1510 &rpm_vreg_device[RPM_VREG_ID_PM8058_S0],
1511 &rpm_vreg_device[RPM_VREG_ID_PM8058_S1],
1512#endif
1513};
1514
1515static struct platform_device *early_devices[] __initdata = {
1516#ifdef CONFIG_MSM_BUS_SCALING
1517 &msm_bus_apps_fabric,
1518 &msm_bus_sys_fabric,
1519 &msm_bus_mm_fabric,
1520 &msm_bus_sys_fpb,
1521 &msm_bus_cpss_fpb,
1522#endif
1523};
1524
1525static struct resource msm_aux_pcm_resources[] = {
1526
1527 {
1528 .name = "aux_pcm_dout",
1529 .start = 111,
1530 .end = 111,
1531 .flags = IORESOURCE_IO,
1532 },
1533 {
1534 .name = "aux_pcm_din",
1535 .start = 112,
1536 .end = 112,
1537 .flags = IORESOURCE_IO,
1538 },
1539 {
1540 .name = "aux_pcm_syncout",
1541 .start = 113,
1542 .end = 113,
1543 .flags = IORESOURCE_IO,
1544 },
1545 {
1546 .name = "aux_pcm_clkin_a",
1547 .start = 114,
1548 .end = 114,
1549 .flags = IORESOURCE_IO,
1550 },
1551};
1552
1553static struct platform_device msm_aux_pcm_device = {
1554 .name = "msm_aux_pcm",
1555 .id = 0,
1556 .num_resources = ARRAY_SIZE(msm_aux_pcm_resources),
1557 .resource = msm_aux_pcm_resources,
1558};
1559
1560
1561static struct platform_device *qrdc_devices[] __initdata = {
1562 &msm_device_smd,
1563 &smsc911x_device,
1564 &msm_device_uart_dm3,
1565#ifdef CONFIG_I2C_QUP
1566 &msm_gsbi3_qup_i2c_device,
1567 &msm_gsbi4_qup_i2c_device,
1568 &msm_gsbi7_qup_i2c_device,
1569 &msm_gsbi8_qup_i2c_device,
1570 &msm_gsbi9_qup_i2c_device,
1571#endif
1572#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
1573 &msm_gsbi1_qup_spi_device,
1574#endif
1575#ifdef CONFIG_SERIAL_MSM_HS
1576 &msm_device_uart_dm1,
1577#endif
1578#ifdef CONFIG_I2C_SSBI
1579 &msm_device_ssbi1,
1580 &msm_device_ssbi2,
1581 &msm_device_ssbi3,
1582#endif
1583#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_HCD)
1584 &msm_device_otg,
1585#endif
1586#ifdef CONFIG_USB_GADGET_MSM_72K
1587 &msm_device_gadget_peripheral,
1588#endif
1589#ifdef CONFIG_USB_ANDROID
1590 &usb_mass_storage_device,
1591 &rndis_device,
1592 &android_usb_device,
1593#endif
1594#ifdef CONFIG_BATTERY_MSM
1595 &msm_batt_device,
1596#endif
1597#ifdef CONFIG_KERNEL_PMEM_EBI_REGION
1598 &android_pmem_kernel_ebi1_device,
1599#endif
1600#ifdef CONFIG_KERNEL_PMEM_SMI_REGION
1601 &android_pmem_kernel_smi_device,
1602#endif
1603#ifdef CONFIG_ANDROID_PMEM
1604 &android_pmem_device,
1605 &android_pmem_adsp_device,
1606 &android_pmem_smipool_device,
1607#endif
1608#ifdef CONFIG_MSM_ROTATOR
1609 &msm_rotator_device,
1610#endif
1611 &msm_fb_device,
1612 &lcdc_qrdc_panel_device,
1613 &msm_device_kgsl,
1614 &lcdc_samsung_panel_device,
1615#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
1616 &hdmi_msm_device,
1617#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
1618 &mipi_dsi_video_toshiba_wvga_panel_device,
1619#ifdef CONFIG_MSM_GEMINI
1620 &msm_gemini_device,
1621#endif
1622#ifdef CONFIG_MSM_VPE
1623 &msm_vpe_device,
1624#endif
1625#if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
1626 &msm_rpm_log_device,
1627#endif
1628 &msm_device_vidc,
1629 &msm_aux_pcm_device,
1630#ifdef CONFIG_PMIC8058
1631 &rpm_vreg_device[RPM_VREG_ID_PM8058_L0],
1632 &rpm_vreg_device[RPM_VREG_ID_PM8058_L1],
1633 &rpm_vreg_device[RPM_VREG_ID_PM8058_L2],
1634 &rpm_vreg_device[RPM_VREG_ID_PM8058_L3],
1635 &rpm_vreg_device[RPM_VREG_ID_PM8058_L4],
1636 &rpm_vreg_device[RPM_VREG_ID_PM8058_L5],
1637 &rpm_vreg_device[RPM_VREG_ID_PM8058_L6],
1638 &rpm_vreg_device[RPM_VREG_ID_PM8058_L7],
1639 &rpm_vreg_device[RPM_VREG_ID_PM8058_L8],
1640 &rpm_vreg_device[RPM_VREG_ID_PM8058_L9],
1641 &rpm_vreg_device[RPM_VREG_ID_PM8058_L10],
1642 &rpm_vreg_device[RPM_VREG_ID_PM8058_L11],
1643 &rpm_vreg_device[RPM_VREG_ID_PM8058_L12],
1644 &rpm_vreg_device[RPM_VREG_ID_PM8058_L13],
1645 &rpm_vreg_device[RPM_VREG_ID_PM8058_L14],
1646 &rpm_vreg_device[RPM_VREG_ID_PM8058_L15],
1647 &rpm_vreg_device[RPM_VREG_ID_PM8058_L16],
1648 &rpm_vreg_device[RPM_VREG_ID_PM8058_L17],
1649 &rpm_vreg_device[RPM_VREG_ID_PM8058_L18],
1650 &rpm_vreg_device[RPM_VREG_ID_PM8058_L19],
1651 &rpm_vreg_device[RPM_VREG_ID_PM8058_L20],
1652 &rpm_vreg_device[RPM_VREG_ID_PM8058_L21],
1653 &rpm_vreg_device[RPM_VREG_ID_PM8058_L22],
1654 &rpm_vreg_device[RPM_VREG_ID_PM8058_L23],
1655 &rpm_vreg_device[RPM_VREG_ID_PM8058_L24],
1656 &rpm_vreg_device[RPM_VREG_ID_PM8058_L25],
1657 &rpm_vreg_device[RPM_VREG_ID_PM8058_S2],
1658 &rpm_vreg_device[RPM_VREG_ID_PM8058_S3],
1659 &rpm_vreg_device[RPM_VREG_ID_PM8058_S4],
1660 &rpm_vreg_device[RPM_VREG_ID_PM8058_LVS0],
1661 &rpm_vreg_device[RPM_VREG_ID_PM8058_LVS1],
1662 &rpm_vreg_device[RPM_VREG_ID_PM8058_NCP],
1663#endif
1664#ifdef CONFIG_PMIC8901
1665 &rpm_vreg_device[RPM_VREG_ID_PM8901_L0],
1666 &rpm_vreg_device[RPM_VREG_ID_PM8901_L1],
1667 &rpm_vreg_device[RPM_VREG_ID_PM8901_L2],
1668 &rpm_vreg_device[RPM_VREG_ID_PM8901_L3],
1669 &rpm_vreg_device[RPM_VREG_ID_PM8901_L4],
1670 &rpm_vreg_device[RPM_VREG_ID_PM8901_L5],
1671 &rpm_vreg_device[RPM_VREG_ID_PM8901_L6],
1672 &rpm_vreg_device[RPM_VREG_ID_PM8901_S2],
1673 &rpm_vreg_device[RPM_VREG_ID_PM8901_S3],
1674 &rpm_vreg_device[RPM_VREG_ID_PM8901_S4],
1675 &rpm_vreg_device[RPM_VREG_ID_PM8901_LVS0],
1676 &rpm_vreg_device[RPM_VREG_ID_PM8901_LVS1],
1677 &rpm_vreg_device[RPM_VREG_ID_PM8901_LVS2],
1678 &rpm_vreg_device[RPM_VREG_ID_PM8901_LVS3],
1679 &rpm_vreg_device[RPM_VREG_ID_PM8901_MVS0],
1680#endif
1681};
1682
1683#ifdef CONFIG_PMIC8058
1684#define PMIC_GPIO_SDC3_DET 22
1685#define PMIC_GPIO_EXT_POWER 1
1686
1687static int pm8058_gpios_init(void)
1688{
1689 int i;
1690 int rc;
1691 struct pm8058_gpio_cfg {
1692 int gpio;
1693 struct pm8058_gpio cfg;
1694 };
1695
1696 struct pm8058_gpio_cfg gpio_cfgs[] = {
1697 { /* External power enable */
1698 PMIC_GPIO_EXT_POWER - 1,
1699 {
1700 .direction = PM_GPIO_DIR_OUT,
1701 .output_value = 1,
1702 .pull = PM_GPIO_PULL_UP_30,
1703 .vin_sel = 2,
1704 .function = PM_GPIO_FUNC_NORMAL,
1705 .inv_int_pol = 0,
1706 },
1707 },
1708 { /* FFA ethernet */
1709 6,
1710 {
1711 .direction = PM_GPIO_DIR_IN,
1712 .pull = PM_GPIO_PULL_DN,
1713 .vin_sel = 2,
1714 .function = PM_GPIO_FUNC_NORMAL,
1715 .inv_int_pol = 0,
1716 },
1717 },
1718#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
1719 …Large files files are truncated, but you can click here to view the full file