PageRenderTime 34ms CodeModel.GetById 28ms RepoModel.GetById 1ms app.codeStats 0ms

/arch/arm/mach-kirkwood/irq.c

https://bitbucket.org/sammyz/iscream_thunderc-2.6.35-rebase
C | 58 lines | 39 code | 7 blank | 12 comment | 1 complexity | 898e80b99c4c7ab4651d8b0d655dd3dc MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0 
    

  1. /*
    2. 

  2.  * arch/arm/mach-kirkwood/irq.c
    3. 

  3.  *
    4. 

  4.  * Kirkwood IRQ handling.
    5. 

  5.  *
    6. 

  6.  * This file is licensed under the terms of the GNU General Public
    7. 

  7.  * License version 2.  This program is licensed "as is" without any
    8. 

  8.  * warranty of any kind, whether express or implied.
    9. 

  9.  */
    10. 

  10. 

  11. #include <linux/kernel.h>
    12. 

  12. #include <linux/init.h>
    13. 

  13. #include <linux/irq.h>
    14. 

  14. #include <linux/io.h>
    15. 

  15. #include <mach/bridge-regs.h>
    16. 

  16. #include <plat/irq.h>
    17. 

  17. #include <asm/gpio.h>
    18. 

  18. #include "common.h"
    19. 

  19. 

  20. static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
    21. 

  21. {
    22. 

  22. 	BUG_ON(irq < IRQ_KIRKWOOD_GPIO_LOW_0_7);
    23. 

  23. 	BUG_ON(irq > IRQ_KIRKWOOD_GPIO_HIGH_16_23);
    24. 

  24. 

  25. 	orion_gpio_irq_handler((irq - IRQ_KIRKWOOD_GPIO_LOW_0_7) << 3);
    26. 

  26. }
    27. 

  27. 

  28. void __init kirkwood_init_irq(void)
    29. 

  29. {
    30. 

  30. 	int i;
    31. 

  31. 

  32. 	orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
    33. 

  33. 	orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
    34. 

  34. 

  35. 	/*
    36. 

  36. 	 * Mask and clear GPIO IRQ interrupts.
    37. 

  37. 	 */
    38. 

  38. 	writel(0, GPIO_LEVEL_MASK(0));
    39. 

  39. 	writel(0, GPIO_EDGE_MASK(0));
    40. 

  40. 	writel(0, GPIO_EDGE_CAUSE(0));
    41. 

  41. 	writel(0, GPIO_LEVEL_MASK(32));
    42. 

  42. 	writel(0, GPIO_EDGE_MASK(32));
    43. 

  43. 	writel(0, GPIO_EDGE_CAUSE(32));
    44. 

  44. 

  45. 	for (i = IRQ_KIRKWOOD_GPIO_START; i < NR_IRQS; i++) {
    46. 

  46. 		set_irq_chip(i, &orion_gpio_irq_chip);
    47. 

  47. 		set_irq_handler(i, handle_level_irq);
    48. 

  48. 		irq_desc[i].status |= IRQ_LEVEL;
    49. 

  49. 		set_irq_flags(i, IRQF_VALID);
    50. 

  50. 	}
    51. 

  51. 	set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler);
    52. 

  52. 	set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler);
    53. 

  53. 	set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler);
    54. 

  54. 	set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler);
    55. 

  55. 	set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler);
    56. 

  56. 	set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler);
    57. 

  57. 	set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler);
    58. 

  58. }
    59. 

  59.