/arch/arm/mach-ixp2000/include/mach/irqs.h
C++ Header | 207 lines | 136 code | 24 blank | 47 comment | 0 complexity | ea0500a198cbd4884d7ad5f575048285 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/*
2 * arch/arm/mach-ixp2000/include/mach/irqs.h
3 *
4 * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
5 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
6 *
7 * Copyright (C) 2002 Intel Corp.
8 * Copyright (C) 2003-2004 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef _IRQS_H
16#define _IRQS_H
17
18/*
19 * Do NOT add #ifdef MACHINE_FOO in here.
20 * Simpy add your machine IRQs here and increase NR_IRQS if needed to
21 * hold your machine's IRQ table.
22 */
23
24/*
25 * Some interrupt numbers go unused b/c the IRQ mask/ummask/status
26 * register has those bit reserved. We just mark those interrupts
27 * as invalid and this allows us to do mask/unmask with a single
28 * shift operation instead of having to map the IRQ number to
29 * a HW IRQ number.
30 */
31#define IRQ_IXP2000_SOFT_INT 0 /* soft interrupt */
32#define IRQ_IXP2000_ERRSUM 1 /* OR of all bits in ErrorStatus reg*/
33#define IRQ_IXP2000_UART 2
34#define IRQ_IXP2000_GPIO 3
35#define IRQ_IXP2000_TIMER1 4
36#define IRQ_IXP2000_TIMER2 5
37#define IRQ_IXP2000_TIMER3 6
38#define IRQ_IXP2000_TIMER4 7
39#define IRQ_IXP2000_PMU 8
40#define IRQ_IXP2000_SPF 9 /* Slow port framer IRQ */
41#define IRQ_IXP2000_DMA1 10
42#define IRQ_IXP2000_DMA2 11
43#define IRQ_IXP2000_DMA3 12
44#define IRQ_IXP2000_PCI_DOORBELL 13
45#define IRQ_IXP2000_ME_ATTN 14
46#define IRQ_IXP2000_PCI 15 /* PCI INTA or INTB */
47#define IRQ_IXP2000_THDA0 16 /* thread 0-31A */
48#define IRQ_IXP2000_THDA1 17 /* thread 32-63A, IXP2800 only */
49#define IRQ_IXP2000_THDA2 18 /* thread 64-95A */
50#define IRQ_IXP2000_THDA3 19 /* thread 96-127A, IXP2800 only */
51#define IRQ_IXP2000_THDB0 24 /* thread 0-31B */
52#define IRQ_IXP2000_THDB1 25 /* thread 32-63B, IXP2800 only */
53#define IRQ_IXP2000_THDB2 26 /* thread 64-95B */
54#define IRQ_IXP2000_THDB3 27 /* thread 96-127B, IXP2800 only */
55
56/* define generic GPIOs */
57#define IRQ_IXP2000_GPIO0 32
58#define IRQ_IXP2000_GPIO1 33
59#define IRQ_IXP2000_GPIO2 34
60#define IRQ_IXP2000_GPIO3 35
61#define IRQ_IXP2000_GPIO4 36
62#define IRQ_IXP2000_GPIO5 37
63#define IRQ_IXP2000_GPIO6 38
64#define IRQ_IXP2000_GPIO7 39
65
66/* split off the 2 PCI sources */
67#define IRQ_IXP2000_PCIA 40
68#define IRQ_IXP2000_PCIB 41
69
70/* Int sources from IRQ_ERROR_STATUS */
71#define IRQ_IXP2000_DRAM0_MIN_ERR 42
72#define IRQ_IXP2000_DRAM0_MAJ_ERR 43
73#define IRQ_IXP2000_DRAM1_MIN_ERR 44
74#define IRQ_IXP2000_DRAM1_MAJ_ERR 45
75#define IRQ_IXP2000_DRAM2_MIN_ERR 46
76#define IRQ_IXP2000_DRAM2_MAJ_ERR 47
77/* 48-57 reserved */
78#define IRQ_IXP2000_SRAM0_ERR 58
79#define IRQ_IXP2000_SRAM1_ERR 59
80#define IRQ_IXP2000_SRAM2_ERR 60
81#define IRQ_IXP2000_SRAM3_ERR 61
82/* 62-65 reserved */
83#define IRQ_IXP2000_MEDIA_ERR 66
84#define IRQ_IXP2000_PCI_ERR 67
85#define IRQ_IXP2000_SP_INT 68
86
87#define NR_IXP2000_IRQS 69
88
89#define IXP2000_BOARD_IRQ(x) (NR_IXP2000_IRQS + (x))
90
91#define IXP2000_BOARD_IRQ_MASK(irq) (1 << (irq - NR_IXP2000_IRQS))
92
93#define IXP2000_ERR_IRQ_MASK(irq) ( 1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR))
94#define IXP2000_VALID_ERR_IRQ_MASK (\
95 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MIN_ERR) | \
96 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MAJ_ERR) | \
97 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MIN_ERR) | \
98 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MAJ_ERR) | \
99 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MIN_ERR) | \
100 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MAJ_ERR) | \
101 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM0_ERR) | \
102 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM1_ERR) | \
103 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM2_ERR) | \
104 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM3_ERR) | \
105 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_MEDIA_ERR) | \
106 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_PCI_ERR) | \
107 IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SP_INT) )
108
109/*
110 * This allows for all the on-chip sources plus up to 32 CPLD based
111 * IRQs. Should be more than enough.
112 */
113#define IXP2000_BOARD_IRQS 32
114#define NR_IRQS (NR_IXP2000_IRQS + IXP2000_BOARD_IRQS)
115
116
117/*
118 * IXDP2400 specific IRQs
119 */
120#define IRQ_IXDP2400_INGRESS_NPU IXP2000_BOARD_IRQ(0)
121#define IRQ_IXDP2400_ENET IXP2000_BOARD_IRQ(1)
122#define IRQ_IXDP2400_MEDIA_PCI IXP2000_BOARD_IRQ(2)
123#define IRQ_IXDP2400_MEDIA_SP IXP2000_BOARD_IRQ(3)
124#define IRQ_IXDP2400_SF_PCI IXP2000_BOARD_IRQ(4)
125#define IRQ_IXDP2400_SF_SP IXP2000_BOARD_IRQ(5)
126#define IRQ_IXDP2400_PMC IXP2000_BOARD_IRQ(6)
127#define IRQ_IXDP2400_TVM IXP2000_BOARD_IRQ(7)
128
129#define NR_IXDP2400_IRQS ((IRQ_IXDP2400_TVM)+1)
130#define IXDP2400_NR_IRQS NR_IXDP2400_IRQS - NR_IXP2000_IRQS
131
132/* IXDP2800 specific IRQs */
133#define IRQ_IXDP2800_EGRESS_ENET IXP2000_BOARD_IRQ(0)
134#define IRQ_IXDP2800_INGRESS_NPU IXP2000_BOARD_IRQ(1)
135#define IRQ_IXDP2800_PMC IXP2000_BOARD_IRQ(2)
136#define IRQ_IXDP2800_FABRIC_PCI IXP2000_BOARD_IRQ(3)
137#define IRQ_IXDP2800_FABRIC IXP2000_BOARD_IRQ(4)
138#define IRQ_IXDP2800_MEDIA IXP2000_BOARD_IRQ(5)
139
140#define NR_IXDP2800_IRQS ((IRQ_IXDP2800_MEDIA)+1)
141#define IXDP2800_NR_IRQS NR_IXDP2800_IRQS - NR_IXP2000_IRQS
142
143/*
144 * IRQs on both IXDP2x01 boards
145 */
146#define IRQ_IXDP2X01_SPCI_DB_0 IXP2000_BOARD_IRQ(2)
147#define IRQ_IXDP2X01_SPCI_DB_1 IXP2000_BOARD_IRQ(3)
148#define IRQ_IXDP2X01_SPCI_PMC_INTA IXP2000_BOARD_IRQ(4)
149#define IRQ_IXDP2X01_SPCI_PMC_INTB IXP2000_BOARD_IRQ(5)
150#define IRQ_IXDP2X01_SPCI_PMC_INTC IXP2000_BOARD_IRQ(6)
151#define IRQ_IXDP2X01_SPCI_PMC_INTD IXP2000_BOARD_IRQ(7)
152#define IRQ_IXDP2X01_SPCI_FIC_INT IXP2000_BOARD_IRQ(8)
153#define IRQ_IXDP2X01_IPMI_FROM IXP2000_BOARD_IRQ(16)
154#define IRQ_IXDP2X01_125US IXP2000_BOARD_IRQ(17)
155#define IRQ_IXDP2X01_DB_0_ADD IXP2000_BOARD_IRQ(18)
156#define IRQ_IXDP2X01_DB_1_ADD IXP2000_BOARD_IRQ(19)
157#define IRQ_IXDP2X01_UART1 IXP2000_BOARD_IRQ(21)
158#define IRQ_IXDP2X01_UART2 IXP2000_BOARD_IRQ(22)
159#define IRQ_IXDP2X01_FIC_ADD_INT IXP2000_BOARD_IRQ(24)
160#define IRQ_IXDP2X01_CS8900 IXP2000_BOARD_IRQ(25)
161#define IRQ_IXDP2X01_BBSRAM IXP2000_BOARD_IRQ(26)
162
163#define IXDP2X01_VALID_IRQ_MASK ( \
164 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_0) | \
165 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_1) | \
166 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTA) | \
167 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTB) | \
168 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTC) | \
169 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTD) | \
170 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_FIC_INT) | \
171 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_IPMI_FROM) | \
172 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_125US) | \
173 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_0_ADD) | \
174 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_1_ADD) | \
175 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART1) | \
176 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART2) | \
177 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_FIC_ADD_INT) | \
178 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_CS8900) | \
179 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_BBSRAM) )
180
181/*
182 * IXDP2401 specific IRQs
183 */
184#define IRQ_IXDP2401_INTA_82546 IXP2000_BOARD_IRQ(0)
185#define IRQ_IXDP2401_INTB_82546 IXP2000_BOARD_IRQ(1)
186
187#define IXDP2401_VALID_IRQ_MASK ( \
188 IXDP2X01_VALID_IRQ_MASK | \
189 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTA_82546) |\
190 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTB_82546))
191
192/*
193 * IXDP2801-specific IRQs
194 */
195#define IRQ_IXDP2801_RIV IXP2000_BOARD_IRQ(0)
196#define IRQ_IXDP2801_CNFG_MEDIA IXP2000_BOARD_IRQ(27)
197#define IRQ_IXDP2801_CLOCK_REF IXP2000_BOARD_IRQ(28)
198
199#define IXDP2801_VALID_IRQ_MASK ( \
200 IXDP2X01_VALID_IRQ_MASK | \
201 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_RIV) |\
202 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CNFG_MEDIA) |\
203 IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CLOCK_REF))
204
205#define NR_IXDP2X01_IRQS ((IRQ_IXDP2801_CLOCK_REF) + 1)
206
207#endif /*_IRQS_H*/