/arch/arm/mach-fsm/sirc.c

https://bitbucket.org/sammyz/iscream_thunderc-2.6.35-rebase · C · 200 lines · 141 code · 36 blank · 23 comment · 13 complexity · 922c77c2a9d84f17005146a48edd9511 MD5 · raw file

  1. /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License version 2 and
  5. * only version 2 as published by the Free Software Foundation.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. * You should have received a copy of the GNU General Public License
  13. * along with this program; if not, write to the Free Software
  14. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  15. * 02110-1301, USA.
  16. *
  17. */
  18. #include <linux/io.h>
  19. #include <linux/irq.h>
  20. #include <linux/interrupt.h>
  21. #include <asm/irq.h>
  22. static void sirc_irq_mask(unsigned int irq);
  23. static void sirc_irq_unmask(unsigned int irq);
  24. static void sirc_irq_ack(unsigned int irq);
  25. static int sirc_irq_set_wake(unsigned int irq, unsigned int on);
  26. static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type);
  27. static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc);
  28. static unsigned int int_enable;
  29. static unsigned int wake_enable;
  30. static struct sirc_regs_t sirc_regs = {
  31. .int_enable = SPSS_SIRC_INT_ENABLE,
  32. .int_enable_clear = SPSS_SIRC_INT_ENABLE_CLEAR,
  33. .int_enable_set = SPSS_SIRC_INT_ENABLE_SET,
  34. .int_type = SPSS_SIRC_INT_TYPE,
  35. .int_polarity = SPSS_SIRC_INT_POLARITY,
  36. .int_clear = SPSS_SIRC_INT_CLEAR,
  37. };
  38. static struct sirc_cascade_regs sirc_reg_table[] = {
  39. {
  40. .int_status = SPSS_SIRC_IRQ_STATUS,
  41. .cascade_irq = INT_SIRC_0,
  42. }
  43. };
  44. static unsigned int save_type;
  45. static unsigned int save_polarity;
  46. /* Mask off the given interrupt. Keep the int_enable mask in sync with
  47. the enable reg, so it can be restored after power collapse. */
  48. static void sirc_irq_mask(unsigned int irq)
  49. {
  50. unsigned int mask;
  51. mask = 1 << (irq - FIRST_SIRC_IRQ);
  52. writel(mask, sirc_regs.int_enable_clear);
  53. int_enable &= ~mask;
  54. return;
  55. }
  56. /* Unmask the given interrupt. Keep the int_enable mask in sync with
  57. the enable reg, so it can be restored after power collapse. */
  58. static void sirc_irq_unmask(unsigned int irq)
  59. {
  60. unsigned int mask;
  61. mask = 1 << (irq - FIRST_SIRC_IRQ);
  62. writel(mask, sirc_regs.int_enable_set);
  63. int_enable |= mask;
  64. return;
  65. }
  66. static void sirc_irq_ack(unsigned int irq)
  67. {
  68. unsigned int mask;
  69. mask = 1 << (irq - FIRST_SIRC_IRQ);
  70. writel(mask, sirc_regs.int_clear);
  71. return;
  72. }
  73. static int sirc_irq_set_wake(unsigned int irq, unsigned int on)
  74. {
  75. unsigned int mask;
  76. /* Used to set the interrupt enable mask during power collapse. */
  77. mask = 1 << (irq - FIRST_SIRC_IRQ);
  78. if (on)
  79. wake_enable |= mask;
  80. else
  81. wake_enable &= ~mask;
  82. return 0;
  83. }
  84. static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type)
  85. {
  86. unsigned int mask;
  87. unsigned int val;
  88. mask = 1 << (irq - FIRST_SIRC_IRQ);
  89. val = readl(sirc_regs.int_polarity);
  90. if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING))
  91. val |= mask;
  92. else
  93. val &= ~mask;
  94. writel(val, sirc_regs.int_polarity);
  95. val = readl(sirc_regs.int_type);
  96. if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
  97. val |= mask;
  98. irq_desc[irq].handle_irq = handle_edge_irq;
  99. } else {
  100. val &= ~mask;
  101. irq_desc[irq].handle_irq = handle_level_irq;
  102. }
  103. writel(val, sirc_regs.int_type);
  104. return 0;
  105. }
  106. /* Finds the pending interrupt on the passed cascade irq and redrives it */
  107. static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc)
  108. {
  109. unsigned int reg = 0;
  110. unsigned int sirq;
  111. unsigned int status;
  112. while ((reg < ARRAY_SIZE(sirc_reg_table)) &&
  113. (sirc_reg_table[reg].cascade_irq != irq))
  114. reg++;
  115. status = readl(sirc_reg_table[reg].int_status);
  116. status &= SIRC_MASK;
  117. if (status == 0)
  118. return;
  119. for (sirq = 0;
  120. (sirq < NR_SIRC_IRQS) && ((status & (1U << sirq)) == 0);
  121. sirq++)
  122. ;
  123. generic_handle_irq(sirq+FIRST_SIRC_IRQ);
  124. desc->chip->ack(irq);
  125. }
  126. void msm_sirc_enter_sleep(void)
  127. {
  128. save_type = readl(sirc_regs.int_type);
  129. save_polarity = readl(sirc_regs.int_polarity);
  130. writel(wake_enable, sirc_regs.int_enable);
  131. return;
  132. }
  133. void msm_sirc_exit_sleep(void)
  134. {
  135. writel(save_type, sirc_regs.int_type);
  136. writel(save_polarity, sirc_regs.int_polarity);
  137. writel(int_enable, sirc_regs.int_enable);
  138. return;
  139. }
  140. static struct irq_chip sirc_irq_chip = {
  141. .name = "sirc",
  142. .ack = sirc_irq_ack,
  143. .mask = sirc_irq_mask,
  144. .unmask = sirc_irq_unmask,
  145. .set_wake = sirc_irq_set_wake,
  146. .set_type = sirc_irq_set_type,
  147. };
  148. void __init msm_init_sirc(void)
  149. {
  150. int i;
  151. int_enable = 0;
  152. wake_enable = 0;
  153. for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) {
  154. set_irq_chip(i, &sirc_irq_chip);
  155. set_irq_handler(i, handle_edge_irq);
  156. set_irq_flags(i, IRQF_VALID);
  157. }
  158. for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) {
  159. set_irq_chained_handler(sirc_reg_table[i].cascade_irq,
  160. sirc_irq_handler);
  161. set_irq_wake(sirc_reg_table[i].cascade_irq, 1);
  162. }
  163. return;
  164. }