/arch/arm/mach-fsm/sirc.c
C | 200 lines | 141 code | 36 blank | 23 comment | 13 complexity | 922c77c2a9d84f17005146a48edd9511 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18
19#include <linux/io.h>
20#include <linux/irq.h>
21#include <linux/interrupt.h>
22#include <asm/irq.h>
23
24static void sirc_irq_mask(unsigned int irq);
25static void sirc_irq_unmask(unsigned int irq);
26static void sirc_irq_ack(unsigned int irq);
27static int sirc_irq_set_wake(unsigned int irq, unsigned int on);
28static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type);
29static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc);
30
31static unsigned int int_enable;
32static unsigned int wake_enable;
33
34static struct sirc_regs_t sirc_regs = {
35 .int_enable = SPSS_SIRC_INT_ENABLE,
36 .int_enable_clear = SPSS_SIRC_INT_ENABLE_CLEAR,
37 .int_enable_set = SPSS_SIRC_INT_ENABLE_SET,
38 .int_type = SPSS_SIRC_INT_TYPE,
39 .int_polarity = SPSS_SIRC_INT_POLARITY,
40 .int_clear = SPSS_SIRC_INT_CLEAR,
41};
42
43static struct sirc_cascade_regs sirc_reg_table[] = {
44 {
45 .int_status = SPSS_SIRC_IRQ_STATUS,
46 .cascade_irq = INT_SIRC_0,
47 }
48};
49
50static unsigned int save_type;
51static unsigned int save_polarity;
52
53/* Mask off the given interrupt. Keep the int_enable mask in sync with
54 the enable reg, so it can be restored after power collapse. */
55static void sirc_irq_mask(unsigned int irq)
56{
57 unsigned int mask;
58
59
60 mask = 1 << (irq - FIRST_SIRC_IRQ);
61 writel(mask, sirc_regs.int_enable_clear);
62 int_enable &= ~mask;
63 return;
64}
65
66/* Unmask the given interrupt. Keep the int_enable mask in sync with
67 the enable reg, so it can be restored after power collapse. */
68static void sirc_irq_unmask(unsigned int irq)
69{
70 unsigned int mask;
71
72 mask = 1 << (irq - FIRST_SIRC_IRQ);
73 writel(mask, sirc_regs.int_enable_set);
74 int_enable |= mask;
75 return;
76}
77
78static void sirc_irq_ack(unsigned int irq)
79{
80 unsigned int mask;
81
82 mask = 1 << (irq - FIRST_SIRC_IRQ);
83 writel(mask, sirc_regs.int_clear);
84 return;
85}
86
87static int sirc_irq_set_wake(unsigned int irq, unsigned int on)
88{
89 unsigned int mask;
90
91 /* Used to set the interrupt enable mask during power collapse. */
92 mask = 1 << (irq - FIRST_SIRC_IRQ);
93 if (on)
94 wake_enable |= mask;
95 else
96 wake_enable &= ~mask;
97
98 return 0;
99}
100
101static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type)
102{
103 unsigned int mask;
104 unsigned int val;
105
106 mask = 1 << (irq - FIRST_SIRC_IRQ);
107 val = readl(sirc_regs.int_polarity);
108
109 if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING))
110 val |= mask;
111 else
112 val &= ~mask;
113
114 writel(val, sirc_regs.int_polarity);
115
116 val = readl(sirc_regs.int_type);
117 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
118 val |= mask;
119 irq_desc[irq].handle_irq = handle_edge_irq;
120 } else {
121 val &= ~mask;
122 irq_desc[irq].handle_irq = handle_level_irq;
123 }
124
125 writel(val, sirc_regs.int_type);
126
127 return 0;
128}
129
130/* Finds the pending interrupt on the passed cascade irq and redrives it */
131static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc)
132{
133 unsigned int reg = 0;
134 unsigned int sirq;
135 unsigned int status;
136
137 while ((reg < ARRAY_SIZE(sirc_reg_table)) &&
138 (sirc_reg_table[reg].cascade_irq != irq))
139 reg++;
140
141 status = readl(sirc_reg_table[reg].int_status);
142 status &= SIRC_MASK;
143 if (status == 0)
144 return;
145
146 for (sirq = 0;
147 (sirq < NR_SIRC_IRQS) && ((status & (1U << sirq)) == 0);
148 sirq++)
149 ;
150 generic_handle_irq(sirq+FIRST_SIRC_IRQ);
151
152 desc->chip->ack(irq);
153}
154
155void msm_sirc_enter_sleep(void)
156{
157 save_type = readl(sirc_regs.int_type);
158 save_polarity = readl(sirc_regs.int_polarity);
159 writel(wake_enable, sirc_regs.int_enable);
160 return;
161}
162
163void msm_sirc_exit_sleep(void)
164{
165 writel(save_type, sirc_regs.int_type);
166 writel(save_polarity, sirc_regs.int_polarity);
167 writel(int_enable, sirc_regs.int_enable);
168 return;
169}
170
171static struct irq_chip sirc_irq_chip = {
172 .name = "sirc",
173 .ack = sirc_irq_ack,
174 .mask = sirc_irq_mask,
175 .unmask = sirc_irq_unmask,
176 .set_wake = sirc_irq_set_wake,
177 .set_type = sirc_irq_set_type,
178};
179
180void __init msm_init_sirc(void)
181{
182 int i;
183
184 int_enable = 0;
185 wake_enable = 0;
186
187 for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) {
188 set_irq_chip(i, &sirc_irq_chip);
189 set_irq_handler(i, handle_edge_irq);
190 set_irq_flags(i, IRQF_VALID);
191 }
192
193 for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) {
194 set_irq_chained_handler(sirc_reg_table[i].cascade_irq,
195 sirc_irq_handler);
196 set_irq_wake(sirc_reg_table[i].cascade_irq, 1);
197 }
198 return;
199}
200