/arch/arm/mach-fsm/gpio.c

https://bitbucket.org/sammyz/iscream_thunderc-2.6.35-rebase · C · 666 lines · 577 code · 66 blank · 23 comment · 47 complexity · c347426e138d8129d8cae45038925b88 MD5 · raw file 

    

  1. /* linux/arch/arm/mach-msm/gpio.c
    2. 

  2.  *
    3. 

  3.  * Copyright (C) 2007 Google, Inc.
    4. 

  4.  * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
    5. 

  5.  *
    6. 

  6.  * This software is licensed under the terms of the GNU General Public
    7. 

  7.  * License version 2, as published by the Free Software Foundation, and
    8. 

  8.  * may be copied, distributed, and modified under those terms.
    9. 

  9.  *
    10. 

  10.  * This program is distributed in the hope that it will be useful,
    11. 

  11.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    12. 

  12.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    13. 

  13.  * GNU General Public License for more details.
    14. 

  14.  *
    15. 

  15.  */
    16. 

  16. 

  17. #include <asm/io.h>
    18. 

  18. #include <asm/gpio.h>
    19. 

  19. #include <linux/irq.h>
    20. 

  20. #include <linux/module.h>
    21. 

  21. #include <linux/debugfs.h>
    22. 

  22. #include "gpio_chip.h"
    23. 

  23. #include "gpio_hw.h"
    24. 

  24. #include "proc_comm.h"
    25. 

  25. 

  26. #include "smd_private.h"
    27. 

  27. 

  28. #ifndef CONFIG_GPIOLIB
    29. 

  29. 

  30. enum {
    31. 

  31. 	GPIO_DEBUG_SLEEP = 1U << 0,
    32. 

  32. };
    33. 

  33. static int msm_gpio_debug_mask = 0;
    34. 

  34. module_param_named(debug_mask, msm_gpio_debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);
    35. 

  35. 

  36. /* private gpio_configure flags */
    37. 

  37. #define MSM_GPIOF_ENABLE_INTERRUPT      0x10000000
    38. 

  38. #define MSM_GPIOF_DISABLE_INTERRUPT     0x20000000
    39. 

  39. #define MSM_GPIOF_ENABLE_WAKE           0x40000000
    40. 

  40. #define MSM_GPIOF_DISABLE_WAKE          0x80000000
    41. 

  41. 

  42. static int msm_gpio_configure(struct goog_gpio_chip *chip,
    43. 

  43. 			unsigned int gpio,
    44. 

  44. 			unsigned long flags);
    45. 

  45. static int msm_gpio_get_irq_num(struct goog_gpio_chip *chip,
    46. 

  46. 				unsigned int gpio,
    47. 

  47. 				unsigned int *irqp,
    48. 

  48. 				unsigned long *irqnumflagsp);
    49. 

  49. static int msm_gpio_read(struct goog_gpio_chip *chip, unsigned n);
    50. 

  50. static int msm_gpio_write(struct goog_gpio_chip *chip,
    51. 

  51. 			unsigned n,
    52. 

  52. 			unsigned on);
    53. 

  53. static int msm_gpio_read_detect_status(struct goog_gpio_chip *chip,
    54. 

  54. 				unsigned int gpio);
    55. 

  55. static int msm_gpio_clear_detect_status(struct goog_gpio_chip *chip,
    56. 

  56. 					unsigned int gpio);
    57. 

  57. 

  58. struct msm_gpio_chip msm_gpio_chips[] = {
    59. 

  59. 	{
    60. 

  60. 		.regs = {
    61. 

  61. 			.out =         GPIO_OUT_0,
    62. 

  62. 			.in =          GPIO_IN_0,
    63. 

  63. 			.int_status =  GPIO_INT_STATUS_0,
    64. 

  64. 			.int_clear =   GPIO_INT_CLEAR_0,
    65. 

  65. 			.int_en =      GPIO_INT_EN_0,
    66. 

  66. 			.int_edge =    GPIO_INT_EDGE_0,
    67. 

  67. 			.int_pos =     GPIO_INT_POS_0,
    68. 

  68. 			.oe =          GPIO_OE_0,
    69. 

  69. 		},
    70. 

  70. 		.chip = {
    71. 

  71. 			.start = 0,
    72. 

  72. 			.end = 15,
    73. 

  73. 			.configure = msm_gpio_configure,
    74. 

  74. 			.get_irq_num = msm_gpio_get_irq_num,
    75. 

  75. 			.read = msm_gpio_read,
    76. 

  76. 			.write = msm_gpio_write,
    77. 

  77. 			.read_detect_status = msm_gpio_read_detect_status,
    78. 

  78. 			.clear_detect_status = msm_gpio_clear_detect_status
    79. 

  79. 		}
    80. 

  80. 	},
    81. 

  81. 	{
    82. 

  82. 		.regs = {
    83. 

  83. 			.out =         GPIO_OUT_1,
    84. 

  84. 			.in =          GPIO_IN_1,
    85. 

  85. 			.int_status =  GPIO_INT_STATUS_1,
    86. 

  86. 			.int_clear =   GPIO_INT_CLEAR_1,
    87. 

  87. 			.int_en =      GPIO_INT_EN_1,
    88. 

  88. 			.int_edge =    GPIO_INT_EDGE_1,
    89. 

  89. 			.int_pos =     GPIO_INT_POS_1,
    90. 

  90. 			.oe =          GPIO_OE_1,
    91. 

  91. 		},
    92. 

  92. 		.chip = {
    93. 

  93. 			.start = 16,
    94. 

  94. #if defined(CONFIG_ARCH_MSM7X30)
    95. 

  95. 			.end = 43,
    96. 

  96. #else
    97. 

  97. 			.end = 42,
    98. 

  98. #endif
    99. 

  99. 			.configure = msm_gpio_configure,
    100. 

  100. 			.get_irq_num = msm_gpio_get_irq_num,
    101. 

  101. 			.read = msm_gpio_read,
    102. 

  102. 			.write = msm_gpio_write,
    103. 

  103. 			.read_detect_status = msm_gpio_read_detect_status,
    104. 

  104. 			.clear_detect_status = msm_gpio_clear_detect_status
    105. 

  105. 		}
    106. 

  106. 	},
    107. 

  107. 	{
    108. 

  108. 		.regs = {
    109. 

  109. 			.out =         GPIO_OUT_2,
    110. 

  110. 			.in =          GPIO_IN_2,
    111. 

  111. 			.int_status =  GPIO_INT_STATUS_2,
    112. 

  112. 			.int_clear =   GPIO_INT_CLEAR_2,
    113. 

  113. 			.int_en =      GPIO_INT_EN_2,
    114. 

  114. 			.int_edge =    GPIO_INT_EDGE_2,
    115. 

  115. 			.int_pos =     GPIO_INT_POS_2,
    116. 

  116. 			.oe =          GPIO_OE_2,
    117. 

  117. 		},
    118. 

  118. 		.chip = {
    119. 

  119. #if defined(CONFIG_ARCH_MSM7X30)
    120. 

  120. 			.start = 44,
    121. 

  121. #else
    122. 

  122. 			.start = 43,
    123. 

  123. #endif
    124. 

  124. 			.end = 67,
    125. 

  125. 			.configure = msm_gpio_configure,
    126. 

  126. 			.get_irq_num = msm_gpio_get_irq_num,
    127. 

  127. 			.read = msm_gpio_read,
    128. 

  128. 			.write = msm_gpio_write,
    129. 

  129. 			.read_detect_status = msm_gpio_read_detect_status,
    130. 

  130. 			.clear_detect_status = msm_gpio_clear_detect_status
    131. 

  131. 		}
    132. 

  132. 	},
    133. 

  133. 	{
    134. 

  134. 		.regs = {
    135. 

  135. 			.out =         GPIO_OUT_3,
    136. 

  136. 			.in =          GPIO_IN_3,
    137. 

  137. 			.int_status =  GPIO_INT_STATUS_3,
    138. 

  138. 			.int_clear =   GPIO_INT_CLEAR_3,
    139. 

  139. 			.int_en =      GPIO_INT_EN_3,
    140. 

  140. 			.int_edge =    GPIO_INT_EDGE_3,
    141. 

  141. 			.int_pos =     GPIO_INT_POS_3,
    142. 

  142. 			.oe =          GPIO_OE_3,
    143. 

  143. 		},
    144. 

  144. 		.chip = {
    145. 

  145. 			.start = 68,
    146. 

  146. 			.end = 94,
    147. 

  147. 			.configure = msm_gpio_configure,
    148. 

  148. 			.get_irq_num = msm_gpio_get_irq_num,
    149. 

  149. 			.read = msm_gpio_read,
    150. 

  150. 			.write = msm_gpio_write,
    151. 

  151. 			.read_detect_status = msm_gpio_read_detect_status,
    152. 

  152. 			.clear_detect_status = msm_gpio_clear_detect_status
    153. 

  153. 		}
    154. 

  154. 	},
    155. 

  155. 	{
    156. 

  156. 		.regs = {
    157. 

  157. 			.out =         GPIO_OUT_4,
    158. 

  158. 			.in =          GPIO_IN_4,
    159. 

  159. 			.int_status =  GPIO_INT_STATUS_4,
    160. 

  160. 			.int_clear =   GPIO_INT_CLEAR_4,
    161. 

  161. 			.int_en =      GPIO_INT_EN_4,
    162. 

  162. 			.int_edge =    GPIO_INT_EDGE_4,
    163. 

  163. 			.int_pos =     GPIO_INT_POS_4,
    164. 

  164. 			.oe =          GPIO_OE_4,
    165. 

  165. 		},
    166. 

  166. 		.chip = {
    167. 

  167. 			.start = 95,
    168. 

  168. #if defined(CONFIG_ARCH_QSD8X50)
    169. 

  169. 			.end = 103,
    170. 

  170. #else
    171. 

  171. 			.end = 106,
    172. 

  172. #endif
    173. 

  173. 			.configure = msm_gpio_configure,
    174. 

  174. 			.get_irq_num = msm_gpio_get_irq_num,
    175. 

  175. 			.read = msm_gpio_read,
    176. 

  176. 			.write = msm_gpio_write,
    177. 

  177. 			.read_detect_status = msm_gpio_read_detect_status,
    178. 

  178. 			.clear_detect_status = msm_gpio_clear_detect_status
    179. 

  179. 		}
    180. 

  180. 	},
    181. 

  181. 	{
    182. 

  182. 		.regs = {
    183. 

  183. 			.out =         GPIO_OUT_5,
    184. 

  184. 			.in =          GPIO_IN_5,
    185. 

  185. 			.int_status =  GPIO_INT_STATUS_5,
    186. 

  186. 			.int_clear =   GPIO_INT_CLEAR_5,
    187. 

  187. 			.int_en =      GPIO_INT_EN_5,
    188. 

  188. 			.int_edge =    GPIO_INT_EDGE_5,
    189. 

  189. 			.int_pos =     GPIO_INT_POS_5,
    190. 

  190. 			.oe =          GPIO_OE_5,
    191. 

  191. 		},
    192. 

  192. 		.chip = {
    193. 

  193. #if defined(CONFIG_ARCH_QSD8X50)
    194. 

  194. 			.start = 104,
    195. 

  195. 			.end = 121,
    196. 

  196. #elif defined(CONFIG_ARCH_MSM7X30)
    197. 

  197. 			.start = 107,
    198. 

  198. 			.end = 133,
    199. 

  199. #else
    200. 

  200. 			.start = 107,
    201. 

  201. 			.end = 132,
    202. 

  202. #endif
    203. 

  203. 			.configure = msm_gpio_configure,
    204. 

  204. 			.get_irq_num = msm_gpio_get_irq_num,
    205. 

  205. 			.read = msm_gpio_read,
    206. 

  206. 			.write = msm_gpio_write,
    207. 

  207. 			.read_detect_status = msm_gpio_read_detect_status,
    208. 

  208. 			.clear_detect_status = msm_gpio_clear_detect_status
    209. 

  209. 		}
    210. 

  210. 	},
    211. 

  211. #if defined(CONFIG_ARCH_MSM_SCORPION)
    212. 

  212. 	{
    213. 

  213. 		.regs = {
    214. 

  214. 			.out =         GPIO_OUT_6,
    215. 

  215. 			.in =          GPIO_IN_6,
    216. 

  216. 			.int_status =  GPIO_INT_STATUS_6,
    217. 

  217. 			.int_clear =   GPIO_INT_CLEAR_6,
    218. 

  218. 			.int_en =      GPIO_INT_EN_6,
    219. 

  219. 			.int_edge =    GPIO_INT_EDGE_6,
    220. 

  220. 			.int_pos =     GPIO_INT_POS_6,
    221. 

  221. 			.oe =          GPIO_OE_6,
    222. 

  222. 		},
    223. 

  223. 		.chip = {
    224. 

  224. #if defined(CONFIG_ARCH_MSM7X30)
    225. 

  225. 			.start = 134,
    226. 

  226. 			.end = 150,
    227. 

  227. #else
    228. 

  228. 			.start = 122,
    229. 

  229. 			.end = 152,
    230. 

  230. #endif
    231. 

  231. 			.configure = msm_gpio_configure,
    232. 

  232. 			.get_irq_num = msm_gpio_get_irq_num,
    233. 

  233. 			.read = msm_gpio_read,
    234. 

  234. 			.write = msm_gpio_write,
    235. 

  235. 			.read_detect_status = msm_gpio_read_detect_status,
    236. 

  236. 			.clear_detect_status = msm_gpio_clear_detect_status
    237. 

  237. 		}
    238. 

  238. 	},
    239. 

  239. 	{
    240. 

  240. 		.regs = {
    241. 

  241. 			.out =         GPIO_OUT_7,
    242. 

  242. 			.in =          GPIO_IN_7,
    243. 

  243. 			.int_status =  GPIO_INT_STATUS_7,
    244. 

  244. 			.int_clear =   GPIO_INT_CLEAR_7,
    245. 

  245. 			.int_en =      GPIO_INT_EN_7,
    246. 

  246. 			.int_edge =    GPIO_INT_EDGE_7,
    247. 

  247. 			.int_pos =     GPIO_INT_POS_7,
    248. 

  248. 			.oe =          GPIO_OE_7,
    249. 

  249. 		},
    250. 

  250. 		.chip = {
    251. 

  251. #if defined(CONFIG_ARCH_MSM7X30)
    252. 

  252. 			.start = 151,
    253. 

  253. 			.end = 181,
    254. 

  254. #else
    255. 

  255. 			.start = 153,
    256. 

  256. 			.end = 164,
    257. 

  257. #endif
    258. 

  258. 			.configure = msm_gpio_configure,
    259. 

  259. 			.get_irq_num = msm_gpio_get_irq_num,
    260. 

  260. 			.read = msm_gpio_read,
    261. 

  261. 			.write = msm_gpio_write,
    262. 

  262. 			.read_detect_status = msm_gpio_read_detect_status,
    263. 

  263. 			.clear_detect_status = msm_gpio_clear_detect_status
    264. 

  264. 		}
    265. 

  265. 	},
    266. 

  266. #endif
    267. 

  267. };
    268. 

  268. 

  269. static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip)
    270. 

  270. {
    271. 

  271. 	int loop_limit = 100;
    272. 

  272. 	unsigned pol, val, val2, intstat;
    273. 

  273. 	do {
    274. 

  274. 		val = readl(msm_chip->regs.in);
    275. 

  275. 		pol = readl(msm_chip->regs.int_pos);
    276. 

  276. 		pol = (pol & ~msm_chip->both_edge_detect) | (~val & msm_chip->both_edge_detect);
    277. 

  277. 		writel(pol, msm_chip->regs.int_pos);
    278. 

  278. 		intstat = readl(msm_chip->regs.int_status);
    279. 

  279. 		val2 = readl(msm_chip->regs.in);
    280. 

  280. 		if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0)
    281. 

  281. 			return;
    282. 

  282. 	} while (loop_limit-- > 0);
    283. 

  283. 	printk(KERN_ERR "msm_gpio_update_both_edge_detect, failed to reach stable state %x != %x\n", val, val2);
    284. 

  284. }
    285. 

  285. 

  286. static int msm_gpio_write(struct goog_gpio_chip *chip, unsigned n, unsigned on)
    287. 

  287. {
    288. 

  288. 	struct msm_gpio_chip *msm_chip = container_of(chip, struct msm_gpio_chip, chip);
    289. 

  289. 	unsigned b = 1U << (n - chip->start);
    290. 

  290. 	unsigned v;
    291. 

  291. 

  292. 	v = readl(msm_chip->regs.out);
    293. 

  293. 	if (on) {
    294. 

  294. 		writel(v | b, msm_chip->regs.out);
    295. 

  295. 	} else {
    296. 

  296. 		writel(v & (~b), msm_chip->regs.out);
    297. 

  297. 	}
    298. 

  298. 	return 0;
    299. 

  299. }
    300. 

  300. 

  301. static int msm_gpio_read(struct goog_gpio_chip *chip, unsigned n)
    302. 

  302. {
    303. 

  303. 	struct msm_gpio_chip *msm_chip = container_of(chip, struct msm_gpio_chip, chip);
    304. 

  304. 	unsigned b = 1U << (n - chip->start);
    305. 

  305. 

  306. 	return (readl(msm_chip->regs.in) & b) ? 1 : 0;
    307. 

  307. }
    308. 

  308. 

  309. static int msm_gpio_read_detect_status(struct goog_gpio_chip *chip,
    310. 

  310. 				unsigned int gpio)
    311. 

  311. {
    312. 

  312. 	struct msm_gpio_chip *msm_chip = container_of(chip, struct msm_gpio_chip, chip);
    313. 

  313. 	unsigned b = 1U << (gpio - chip->start);
    314. 

  314. 	unsigned v;
    315. 

  315. 

  316. 	v = readl(msm_chip->regs.int_status);
    317. 

  317. #if MSM_GPIO_BROKEN_INT_CLEAR
    318. 

  318. 	v |= msm_chip->int_status_copy;
    319. 

  319. #endif
    320. 

  320. 	return (v & b) ? 1 : 0;
    321. 

  321. }
    322. 

  322. 

  323. static int msm_gpio_clear_detect_status(struct goog_gpio_chip *chip,
    324. 

  324. 					unsigned int gpio)
    325. 

  325. {
    326. 

  326. 	struct msm_gpio_chip *msm_chip = container_of(chip, struct msm_gpio_chip, chip);
    327. 

  327. 	unsigned b = 1U << (gpio - chip->start);
    328. 

  328. 

  329. #if MSM_GPIO_BROKEN_INT_CLEAR
    330. 

  330. 	/* Save interrupts that already triggered before we loose them. */
    331. 

  331. 	/* Any interrupt that triggers between the read of int_status */
    332. 

  332. 	/* and the write to int_clear will still be lost though. */
    333. 

  333. 	msm_chip->int_status_copy |= readl(msm_chip->regs.int_status);
    334. 

  334. 	msm_chip->int_status_copy &= ~b;
    335. 

  335. #endif
    336. 

  336. 	writel(b, msm_chip->regs.int_clear);
    337. 

  337. 	msm_gpio_update_both_edge_detect(msm_chip);
    338. 

  338. 	return 0;
    339. 

  339. }
    340. 

  340. 

  341. int msm_gpio_configure(struct goog_gpio_chip *chip,
    342. 

  342. 		unsigned int gpio,
    343. 

  343. 		unsigned long flags)
    344. 

  344. {
    345. 

  345. 	struct msm_gpio_chip *msm_chip = container_of(chip, struct msm_gpio_chip, chip);
    346. 

  346. 	unsigned b = 1U << (gpio - chip->start);
    347. 

  347. 	unsigned v;
    348. 

  348. 

  349. 	if (flags & (GPIOF_OUTPUT_LOW | GPIOF_OUTPUT_HIGH))
    350. 

  350. 		msm_gpio_write(chip, gpio, flags & GPIOF_OUTPUT_HIGH);
    351. 

  351. 

  352. 	if (flags & (GPIOF_INPUT | GPIOF_DRIVE_OUTPUT)) {
    353. 

  353. 		v = readl(msm_chip->regs.oe);
    354. 

  354. 		if (flags & GPIOF_DRIVE_OUTPUT) {
    355. 

  355. 			writel(v | b, msm_chip->regs.oe);
    356. 

  356. 		} else {
    357. 

  357. 			writel(v & (~b), msm_chip->regs.oe);
    358. 

  358. 		}
    359. 

  359. 	}
    360. 

  360. 

  361. 	if (flags & (IRQF_TRIGGER_MASK | GPIOF_IRQF_TRIGGER_NONE)) {
    362. 

  362. 		v = readl(msm_chip->regs.int_edge);
    363. 

  363. 		if (flags & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING)) {
    364. 

  364. 			writel(v | b, msm_chip->regs.int_edge);
    365. 

  365. 			irq_desc[MSM_GPIO_TO_INT(gpio)].handle_irq = handle_edge_irq;
    366. 

  366. 		} else {
    367. 

  367. 			writel(v & (~b), msm_chip->regs.int_edge);
    368. 

  368. 			irq_desc[MSM_GPIO_TO_INT(gpio)].handle_irq = handle_level_irq;
    369. 

  369. 		}
    370. 

  370. 		if ((flags & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING)) == (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING)) {
    371. 

  371. 			msm_chip->both_edge_detect |= b;
    372. 

  372. 			msm_gpio_update_both_edge_detect(msm_chip);
    373. 

  373. 		} else {
    374. 

  374. 			msm_chip->both_edge_detect &= ~b;
    375. 

  375. 			v = readl(msm_chip->regs.int_pos);
    376. 

  376. 			if (flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH)) {
    377. 

  377. 				writel(v | b, msm_chip->regs.int_pos);
    378. 

  378. 			} else {
    379. 

  379. 				writel(v & (~b), msm_chip->regs.int_pos);
    380. 

  380. 			}
    381. 

  381. 		}
    382. 

  382. 	}
    383. 

  383. 

  384. 	/* used by msm_gpio_irq_mask and msm_gpio_irq_unmask */
    385. 

  385. 	if (flags & (MSM_GPIOF_ENABLE_INTERRUPT | MSM_GPIOF_DISABLE_INTERRUPT)) {
    386. 

  386. 		v = readl(msm_chip->regs.int_edge);
    387. 

  387. 		/* level triggered interrupts are also latched */
    388. 

  388. 		if (!(v & b))
    389. 

  389. 			msm_gpio_clear_detect_status(chip, gpio);
    390. 

  390. 		if (flags & MSM_GPIOF_ENABLE_INTERRUPT) {
    391. 

  391. 			msm_chip->int_enable[0] |= b;
    392. 

  392. 		} else {
    393. 

  393. 			msm_chip->int_enable[0] &= ~b;
    394. 

  394. 		}
    395. 

  395. 		writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
    396. 

  396. 	}
    397. 

  397. 

  398. 	if (flags & (MSM_GPIOF_ENABLE_WAKE | MSM_GPIOF_DISABLE_WAKE)) {
    399. 

  399. 		if (flags & MSM_GPIOF_ENABLE_WAKE)
    400. 

  400. 			msm_chip->int_enable[1] |= b;
    401. 

  401. 		else
    402. 

  402. 			msm_chip->int_enable[1] &= ~b;
    403. 

  403. 	}
    404. 

  404. 

  405. 	return 0;
    406. 

  406. }
    407. 

  407. 

  408. static int msm_gpio_get_irq_num(struct goog_gpio_chip *chip,
    409. 

  409. 				unsigned int gpio,
    410. 

  410. 				unsigned int *irqp,
    411. 

  411. 				unsigned long *irqnumflagsp)
    412. 

  412. {
    413. 

  413. 	*irqp = MSM_GPIO_TO_INT(gpio);
    414. 

  414. 	if (irqnumflagsp)
    415. 

  415. 		*irqnumflagsp = 0;
    416. 

  416. 	return 0;
    417. 

  417. }
    418. 

  418. 

  419. 

  420. static void msm_gpio_irq_ack(unsigned int irq)
    421. 

  421. {
    422. 

  422. 	gpio_clear_detect_status(irq - NR_MSM_IRQS);
    423. 

  423. }
    424. 

  424. 

  425. static void msm_gpio_irq_mask(unsigned int irq)
    426. 

  426. {
    427. 

  427. 	gpio_configure(irq - NR_MSM_IRQS, MSM_GPIOF_DISABLE_INTERRUPT);
    428. 

  428. }
    429. 

  429. 

  430. static void msm_gpio_irq_unmask(unsigned int irq)
    431. 

  431. {
    432. 

  432. 	gpio_configure(irq - NR_MSM_IRQS, MSM_GPIOF_ENABLE_INTERRUPT);
    433. 

  433. }
    434. 

  434. 

  435. static void msm_gpio_irq_disable(unsigned int irq)
    436. 

  436. {
    437. 

  437. 	struct irq_desc *desc = irq_to_desc(irq);
    438. 

  438. 

  439. 	msm_gpio_irq_mask(irq);
    440. 

  440. 	desc->status |= IRQ_MASKED;
    441. 

  441. }
    442. 

  442. 

  443. static void msm_gpio_irq_enable(unsigned int irq)
    444. 

  444. {
    445. 

  445. 	struct irq_desc *desc = irq_to_desc(irq);
    446. 

  446. 

  447. 	msm_gpio_irq_unmask(irq);
    448. 

  448. 	desc->status &= ~IRQ_MASKED;
    449. 

  449. }
    450. 

  450. 

  451. static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
    452. 

  452. {
    453. 

  453. 	return gpio_configure(irq - NR_MSM_IRQS, on ? MSM_GPIOF_ENABLE_WAKE : MSM_GPIOF_DISABLE_WAKE);
    454. 

  454. }
    455. 

  455. 

  456. 

  457. static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
    458. 

  458. {
    459. 

  459. 	return gpio_configure(irq - NR_MSM_IRQS, flow_type);
    460. 

  460. }
    461. 

  461. 

  462. static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
    463. 

  463. {
    464. 

  464. 	int i, j, m;
    465. 

  465. 	unsigned v;
    466. 

  466. 

  467. 	for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
    468. 

  468. 		struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i];
    469. 

  469. 		v = readl(msm_chip->regs.int_status);
    470. 

  470. 		v &= msm_chip->int_enable[0];
    471. 

  471. 		while (v) {
    472. 

  472. 			m = v & -v;
    473. 

  473. 			j = fls(m) - 1;
    474. 

  474. 			/* printk("msm_gpio_irq_handler %08x %08x bit %d gpio %d irq %d\n", v, m, j, msm_chip->chip.start + j, NR_MSM_IRQS + msm_chip->chip.start + j); */
    475. 

  475. 			v &= ~m;
    476. 

  476. 			generic_handle_irq(NR_MSM_IRQS + msm_chip->chip.start + j);
    477. 

  477. 		}
    478. 

  478. 	}
    479. 

  479. 	desc->chip->ack(irq);
    480. 

  480. }
    481. 

  481. 

  482. static struct irq_chip msm_gpio_irq_chip = {
    483. 

  483. 	.name      = "msmgpio",
    484. 

  484. 	.ack       = msm_gpio_irq_ack,
    485. 

  485. 	.mask      = msm_gpio_irq_mask,
    486. 

  486. 	.unmask    = msm_gpio_irq_unmask,
    487. 

  487. 	.disable   = msm_gpio_irq_disable,
    488. 

  488. 	.enable    = msm_gpio_irq_enable,
    489. 

  489. 	.set_wake  = msm_gpio_irq_set_wake,
    490. 

  490. 	.set_type  = msm_gpio_irq_set_type,
    491. 

  491. };
    492. 

  492. 

  493. #define NUM_GPIO_SMEM_BANKS 6
    494. 

  494. #define GPIO_SMEM_NUM_GROUPS 2
    495. 

  495. #define GPIO_SMEM_MAX_PC_INTERRUPTS 8
    496. 

  496. struct tramp_gpio_smem
    497. 

  497. {
    498. 

  498. 	uint16_t num_fired[GPIO_SMEM_NUM_GROUPS];
    499. 

  499. 	uint16_t fired[GPIO_SMEM_NUM_GROUPS][GPIO_SMEM_MAX_PC_INTERRUPTS];
    500. 

  500. 	uint32_t enabled[NUM_GPIO_SMEM_BANKS];
    501. 

  501. 	uint32_t detection[NUM_GPIO_SMEM_BANKS];
    502. 

  502. 	uint32_t polarity[NUM_GPIO_SMEM_BANKS];
    503. 

  503. };
    504. 

  504. 

  505. static void msm_gpio_sleep_int(unsigned long arg)
    506. 

  506. {
    507. 

  507. 	int i, j;
    508. 

  508. 	struct tramp_gpio_smem *smem_gpio;
    509. 

  509. 

  510. 	BUILD_BUG_ON(NR_GPIO_IRQS > NUM_GPIO_SMEM_BANKS * 32);
    511. 

  511. 

  512. 	smem_gpio = smem_alloc(SMEM_GPIO_INT, sizeof(*smem_gpio)); 
    513. 

  513. 	if (smem_gpio == NULL)
    514. 

  514. 		return;
    515. 

  515. 

  516. 	local_irq_disable();
    517. 

  517. 	for(i = 0; i < GPIO_SMEM_NUM_GROUPS; i++) {
    518. 

  518. 		int count = smem_gpio->num_fired[i];
    519. 

  519. 		for(j = 0; j < count; j++) {
    520. 

  520. 			/* TODO: Check mask */
    521. 

  521. 			generic_handle_irq(MSM_GPIO_TO_INT(smem_gpio->fired[i][j]));
    522. 

  522. 		}
    523. 

  523. 	}
    524. 

  524. 	local_irq_enable();
    525. 

  525. }
    526. 

  526. 

  527. static DECLARE_TASKLET(msm_gpio_sleep_int_tasklet, msm_gpio_sleep_int, 0);
    528. 

  528. 

  529. void msm_gpio_enter_sleep(int from_idle)
    530. 

  530. {
    531. 

  531. 	int i;
    532. 

  532. 	struct tramp_gpio_smem *smem_gpio;
    533. 

  533. 

  534. 	smem_gpio = smem_alloc(SMEM_GPIO_INT, sizeof(*smem_gpio)); 
    535. 

  535. 

  536. 	if (smem_gpio) {
    537. 

  537. 		for (i = 0; i < ARRAY_SIZE(smem_gpio->enabled); i++) {
    538. 

  538. 			smem_gpio->enabled[i] = 0;
    539. 

  539. 			smem_gpio->detection[i] = 0;
    540. 

  540. 			smem_gpio->polarity[i] = 0;
    541. 

  541. 		}
    542. 

  542. 	}
    543. 

  543. 

  544. 	for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
    545. 

  545. 		writel(msm_gpio_chips[i].int_enable[!from_idle], msm_gpio_chips[i].regs.int_en);
    546. 

  546. 		if (smem_gpio) {
    547. 

  547. 			uint32_t tmp;
    548. 

  548. 			int start, index, shiftl, shiftr;
    549. 

  549. 			start = msm_gpio_chips[i].chip.start;
    550. 

  550. 			index = start / 32;
    551. 

  551. 			shiftl = start % 32;
    552. 

  552. 			shiftr = 32 - shiftl;
    553. 

  553. 			tmp = msm_gpio_chips[i].int_enable[!from_idle];
    554. 

  554. 			smem_gpio->enabled[index] |= tmp << shiftl;
    555. 

  555. 			smem_gpio->enabled[index+1] |= tmp >> shiftr;
    556. 

  556. 			smem_gpio->detection[index] |= readl(msm_gpio_chips[i].regs.int_edge) << shiftl;
    557. 

  557. 			smem_gpio->detection[index+1] |= readl(msm_gpio_chips[i].regs.int_edge) >> shiftr;
    558. 

  558. 			smem_gpio->polarity[index] |= readl(msm_gpio_chips[i].regs.int_pos) << shiftl;
    559. 

  559. 			smem_gpio->polarity[index+1] |= readl(msm_gpio_chips[i].regs.int_pos) >> shiftr;
    560. 

  560. 		}
    561. 

  561. 	}
    562. 

  562. 

  563. 	if (smem_gpio) {
    564. 

  564. 		if (msm_gpio_debug_mask & GPIO_DEBUG_SLEEP)
    565. 

  565. 			for (i = 0; i < ARRAY_SIZE(smem_gpio->enabled); i++) {
    566. 

  566. 				printk("msm_gpio_enter_sleep gpio %d-%d: enable"
    567. 

  567. 				       " %08x, edge %08x, polarity %08x\n",
    568. 

  568. 				       i * 32, i * 32 + 31,
    569. 

  569. 				       smem_gpio->enabled[i],
    570. 

  570. 				       smem_gpio->detection[i],
    571. 

  571. 				       smem_gpio->polarity[i]);
    572. 

  572. 			}
    573. 

  573. 		for(i = 0; i < GPIO_SMEM_NUM_GROUPS; i++)
    574. 

  574. 			smem_gpio->num_fired[i] = 0;
    575. 

  575. 	}
    576. 

  576. }
    577. 

  577. 

  578. void msm_gpio_exit_sleep(void)
    579. 

  579. {
    580. 

  580. 	int i;
    581. 

  581. 	struct tramp_gpio_smem *smem_gpio;
    582. 

  582. 

  583. 	smem_gpio = smem_alloc(SMEM_GPIO_INT, sizeof(*smem_gpio)); 
    584. 

  584. 

  585. 	for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
    586. 

  586. 		writel(msm_gpio_chips[i].int_enable[0], msm_gpio_chips[i].regs.int_en);
    587. 

  587. 	}
    588. 

  588. 

  589. 	if (smem_gpio && (smem_gpio->num_fired[0] || smem_gpio->num_fired[1])) {
    590. 

  590. 		if (msm_gpio_debug_mask & GPIO_DEBUG_SLEEP)
    591. 

  591. 			printk(KERN_INFO "gpio: fired %x %x\n",
    592. 

  592. 			      smem_gpio->num_fired[0], smem_gpio->num_fired[1]);
    593. 

  593. 		tasklet_schedule(&msm_gpio_sleep_int_tasklet);
    594. 

  594. 	}
    595. 

  595. }
    596. 

  596. 

  597. static int __init msm_init_gpio(void)
    598. 

  598. {
    599. 

  599. 	int i;
    600. 

  600. 

  601. 	for (i = NR_MSM_IRQS; i < NR_MSM_IRQS + NR_GPIO_IRQS; i++) {
    602. 

  602. 		set_irq_chip(i, &msm_gpio_irq_chip);
    603. 

  603. 		set_irq_handler(i, handle_edge_irq);
    604. 

  604. 		set_irq_flags(i, IRQF_VALID);
    605. 

  605. 	}
    606. 

  606. 

  607. 	for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
    608. 

  608. 		writel(0, msm_gpio_chips[i].regs.int_en);
    609. 

  609. 		register_gpio_chip(&msm_gpio_chips[i].chip);
    610. 

  610. 	}
    611. 

  611. 

  612. 	set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
    613. 

  613. 	set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
    614. 

  614. 	set_irq_wake(INT_GPIO_GROUP1, 1);
    615. 

  615. 	set_irq_wake(INT_GPIO_GROUP2, 2);
    616. 

  616. 	return 0;
    617. 

  617. }
    618. 

  618. 

  619. postcore_initcall(msm_init_gpio);
    620. 

  620. 

  621. #if defined(CONFIG_DEBUG_FS)
    622. 

  622. 

  623. static int msm_gpio_debug_result = 1;
    624. 

  624. 

  625. static int gpio_enable_set(void *data, u64 val)
    626. 

  626. {
    627. 

  627. 	msm_gpio_debug_result = gpio_tlmm_config(val, 0);
    628. 

  628. 	return 0;
    629. 

  629. }
    630. 

  630. static int gpio_disable_set(void *data, u64 val)
    631. 

  631. {
    632. 

  632. 	msm_gpio_debug_result = gpio_tlmm_config(val, 1);
    633. 

  633. 	return 0;
    634. 

  634. }
    635. 

  635. 

  636. static int gpio_debug_get(void *data, u64 *val)
    637. 

  637. {
    638. 

  638. 	unsigned int result = msm_gpio_debug_result;
    639. 

  639. 	msm_gpio_debug_result = 1;
    640. 

  640. 	if (result)
    641. 

  641. 		*val = 1;
    642. 

  642. 	else
    643. 

  643. 		*val = 0;
    644. 

  644. 	return 0;
    645. 

  645. }
    646. 

  646. 

  647. DEFINE_SIMPLE_ATTRIBUTE(gpio_enable_fops, gpio_debug_get,
    648. 

  648. 						gpio_enable_set, "%llu\n");
    649. 

  649. DEFINE_SIMPLE_ATTRIBUTE(gpio_disable_fops, gpio_debug_get,
    650. 

  650. 						gpio_disable_set, "%llu\n");
    651. 

  651. 

  652. static int __init gpio_debug_init(void)
    653. 

  653. {
    654. 

  654. 	struct dentry *dent;
    655. 

  655. 	dent = debugfs_create_dir("gpio", 0);
    656. 

  656. 	if (IS_ERR(dent))
    657. 

  657. 		return 0;
    658. 

  658. 

  659. 	debugfs_create_file("enable", 0644, dent, 0, &gpio_enable_fops);
    660. 

  660. 	debugfs_create_file("disable", 0644, dent, 0, &gpio_disable_fops);
    661. 

  661. 	return 0;
    662. 

  662. }
    663. 

  663. 

  664. device_initcall(gpio_debug_init);
    665. 

  665. #endif
    666. 

  666. #endif
    667.