/arch/arm/mach-fsm/qdsp6v2/apr_audio.h
C++ Header | 910 lines | 706 code | 110 blank | 94 comment | 0 complexity | 1bd4a3094233a5f17111e43aa43beb9d MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1
2/*
3 *
4 * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
18 * 02110-1301, USA.
19 *
20 */
21
22#ifndef _APR_AUDIO_H_
23#define _APR_AUDIO_H_
24
25/* ASM opcodes without APR payloads*/
26#include "apr.h"
27
28
29/*
30 * Audio Front End (AFE)
31 */
32
33/* Port ID */
34enum {
35 PRIMARY_I2S_RX = 0,
36 PRIMARY_I2S_TX = 1,
37 PCM_RX = 2,
38 PCM_TX = 3,
39 SECONDARY_I2S_RX = 4,
40 SECONDARY_I2S_TX = 5,
41 MI2S_RX = 6,
42 RSVD_1 = 7,
43 HDMI_RX = 8,
44 RSVD_2 = 9,
45 RSVD_3 = 10,
46 DIGI_MIC_TX = 11,
47 AFE_MAX_PORTS ,
48};
49
50#define AFE_PORT_CMD_START 0x000100ca
51struct afe_port_start_command {
52 struct apr_hdr hdr;
53 u16 port_id;
54 u16 gain; /* Q13 */
55 u32 sample_rate; /* 8 , 16, 48khz */
56} __attribute__ ((packed));
57
58#define AFE_PORT_CMD_STOP 0x000100cb
59struct afe_port_stop_command {
60 struct apr_hdr hdr;
61 u16 port_id;
62 u16 reserved;
63} __attribute__ ((packed));
64
65#define AFE_PORT_CMD_APPLY_GAIN 0x000100cc
66struct afe_port_gain_command {
67 struct apr_hdr hdr;
68 u16 port_id;
69 u16 gain; /* Q13 */
70} __attribute__ ((packed));
71
72#define AFE_PORT_CMD_SIDETONE_CTL 0x000100cd
73struct afe_port_sidetone_command {
74 struct apr_hdr hdr;
75 u16 tx_port_id; /* Primary i2s rx = 0 */
76 /* PCM rx = 2 */
77 /* Secondary i2s rx = 4 */
78 /* Mi2S rx = 6 */
79 /* HDMI rx = 8 */
80 u16 rx_port_id; /* Primary i2s tx = 1 */
81 /* PCM tx = 3 */
82 /* Secondary i2s tx = 5 */
83 /* Mi2s tx = 7 */
84 /* Digital mic tx = 11 */
85 u16 gain; /* Q13 */
86 u16 enable; /* 1 = enable, 0 = disable */
87} __attribute__ ((packed));
88
89#define AFE_PORT_CMD_LOOPBACK 0x000100ce
90struct afe_loopback_command {
91 struct apr_hdr hdr;
92 u16 tx_port_id; /* Primary i2s rx = 0 */
93 /* PCM rx = 2 */
94 /* Secondary i2s rx = 4 */
95 /* Mi2S rx = 6 */
96 /* HDMI rx = 8 */
97 u16 rx_port_id; /* Primary i2s tx = 1 */
98 /* PCM tx = 3 */
99 /* Secondary i2s tx = 5 */
100 /* Mi2s tx = 7 */
101 /* Digital mic tx = 11 */
102 u16 mode; /* Default -1, DSP will conver
103 the tx to rx format */
104 u16 enable; /* 1 = enable, 0 = disable */
105} __attribute__ ((packed));
106
107#define AFE_PSEUDOPORT_CMD_START 0x000100cf
108struct afe_pseudoport_start_command {
109 struct apr_hdr hdr;
110 u16 port_id; /* Pseudo Port 1 = 0x8000 */
111 /* Pseudo Port 2 = 0x8001 */
112 /* Pseudo Port 3 = 0x8002 */
113 u16 timing; /* FTRT = 0 , AVTimer = 1, */
114} __attribute__ ((packed));
115
116#define AFE_PSEUDOPORT_CMD_STOP 0x000100d0
117struct afe_pseudoport_stop_command {
118 struct apr_hdr hdr;
119 u16 port_id; /* Pseudo Port 1 = 0x8000 */
120 /* Pseudo Port 2 = 0x8001 */
121 /* Pseudo Port 3 = 0x8002 */
122 u16 reserved;
123} __attribute__ ((packed));
124
125#define AFE_CMD_GET_ACTIVE_PORTS 0x000100d1
126
127
128#define AFE_CMD_GET_ACTIVE_HANDLES_FOR_PORT 0x000100d2
129struct afe_get_active_handles_command {
130 struct apr_hdr hdr;
131 u16 port_id;
132 u16 reserved;
133} __attribute__ ((packed));
134
135struct afe_port_pcm_cfg {
136 u16 port_id;
137 u16 mode; /* PCM (short sync) = 0, AUXPCM (long sync) = 1 */
138 u16 sync; /* external = 0 , internal = 1 */
139 u16 frame; /* 8 bpf = 0 */
140 /* 16 bpf = 1 */
141 /* 32 bpf = 2 */
142 /* 64 bpf = 3 */
143 /* 128 bpf = 4 */
144 /* 256 bpf = 5 */
145 u16 quant;
146 u16 slot; /* Slot for PCM stream , 0 - 31 */
147 u16 data; /* 0, PCM block is the only master */
148 /* 1, PCM block is shares to driver data out signal */
149 /* other master */
150 u16 reserved;
151} __attribute__ ((packed));
152
153struct afe_port_mi2s_cfg {
154 u16 port_id;
155 u16 bitwidth; /* 16,24,32 */
156 u16 line; /* i2s_sd0 = 1 */
157 /* i2s_sd1 = 2 */
158 /* i2s_sd2 = 3 */
159 /* i2s_sd3 = 4 */
160 /* i2s_quad01 = 5 */
161 /* i2s_quad23 = 6 */
162 /* i2s_6chs = 7 */
163 /* i2s_8chs = 8 */
164 u16 channel; /* i2s mono = 0 */
165 /* i2s mono right = 1 */
166 /* i2s mono left = 2 */
167 /* i2s stereo = 3 */
168 u16 ws; /* 0, word select signal from external source */
169 /* 1, word select signal from internal source */
170 u16 reserved;
171} __attribute__ ((packed));
172
173
174
175#define AFE_PORT_AUDIO_IF_CONFIG 0x000100d3
176struct afe_audioif_config_command {
177 struct apr_hdr hdr;
178 union {
179 struct afe_port_pcm_cfg pcm;
180 struct afe_port_mi2s_cfg mi2s;
181 } __attribute__((packed)) port;
182} __attribute__ ((packed));
183
184
185
186#define AFE_TEST_CODEC_LOOPBACK_CTL 0x000100d5
187struct afe_codec_loopback_command {
188 u16 port_inf; /* Primary i2s = 0 */
189 /* PCM = 2 */
190 /* Secondary i2s = 4 */
191 /* Mi2s = 6 */
192 u16 enable; /* 0, disable. 1, enable */
193} __attribute__ ((packed));
194
195
196#define AFE_EVENT_GET_ACTIVE_PORTS 0x00010100
197struct afe_get_active_ports_rsp {
198 u16 num_ports;
199 u16 port_id;
200} __attribute__ ((packed));
201
202
203#define AFE_EVENT_GET_ACTIVE_HANDLES 0x00010102
204struct afe_get_active_handles_rsp {
205 u16 port_id;
206 u16 num_handles;
207 u16 mode; /* 0, voice rx */
208 /* 1, voice tx */
209 /* 2, audio rx */
210 /* 3, audio tx */
211 u16 handle;
212} __attribute__ ((packed));
213
214#define ADM_MAX_COPPS 5
215
216#define ADM_SERVICE_CMD_GET_COPP_HANDLES 0x00010300
217struct adm_get_copp_handles_command {
218 struct apr_hdr hdr;
219} __attribute__ ((packed));
220
221#define ADM_CMD_MATRIX_MAP_ROUTINGS 0x00010301
222struct adm_routings_session {
223 u16 id;
224 u16 num_copps;
225 u16 copp_id[ADM_MAX_COPPS];
226} __attribute__ ((packed));
227
228struct adm_routings_command {
229 struct apr_hdr hdr;
230 u32 path; /* 0 = Rx, 1 Tx */
231 u32 num_sessions;
232 struct adm_routings_session sessions[8];
233} __attribute__ ((packed));
234
235
236#define ADM_CMD_MATRIX_RAMP_GAINS 0x00010302
237struct adm_ramp_gain {
238 struct apr_hdr hdr;
239 u16 session_id;
240 u16 copp_id;
241 u16 initial_gain;
242 u16 gain_increment;
243 u16 ramp_duration;
244 u16 reserved;
245} __attribute__ ((packed));
246
247struct adm_ramp_gains_command {
248 struct apr_hdr hdr;
249 u32 id;
250 u32 num_gains;
251 struct adm_ramp_gain gains[ADM_MAX_COPPS];
252} __attribute__ ((packed));
253
254
255#define ADM_CMD_COPP_OPEN 0x00010304
256struct adm_copp_open_command {
257 struct apr_hdr hdr;
258 u16 flags;
259 u16 endpoint_id;
260 u32 topology_id;
261} __attribute__ ((packed));
262
263#define ADM_CMD_COPP_CLOSE 0x00010305
264
265
266#define DEFAULT_TOPOLOGY 0x00010be4
267
268struct asm_pp_param_data_hdr {
269 u32 module_id;
270 u32 param_id;
271 u16 param_size;
272 u16 updated_flag;
273} __attribute__ ((packed));
274
275
276#define VOLUME_CONTROL_MODULE_ID 0x00010bfe
277#define MASTER_GAIN_PARAM_ID 0x00010bff
278#define L_R_CHANNEL_GAIN_PARAM_ID 0x00010c00
279#define MUTE_CONFIG_PARAM_ID 0x00010c01
280
281#define IIR_FILTER_ENABLE_PARAM_ID 0x00010c03
282#define IIR_FILTER_PREGAIN_PARAM_ID 0x00010c04
283#define IIR_FILTER_CONFIG_PARAM_ID 0x00010c05
284
285#define MBADRC_MODULE_ID 0x00010c06
286#define MBADRC_ENABLE_PARAM_ID 0x00010c07
287#define MBADRC_CONFIG_PARAM_ID 0x00010c08
288
289struct asm_pp_params {
290 struct asm_pp_param_data_hdr hdr;
291} __attribute__ ((packed));
292
293#define ADM_CMD_SET_PARAMS 0x00010306
294struct adm_set_params_command {
295 struct apr_hdr hdr;
296 struct asm_pp_params param;
297} __attribute__ ((packed));
298
299
300#define ADM_CMD_TAP_COPP_PCM 0x00010307
301struct adm_tap_copp_pcm_command {
302 struct apr_hdr hdr;
303} __attribute__ ((packed));
304
305
306/* QDSP6 to Client messages
307*/
308#define ADM_SERVICE_CMDRSP_GET_COPP_HANDLES 0x00010308
309struct adm_get_copp_handles_respond {
310 struct apr_hdr hdr;
311 u32 handles;
312 u32 copp_id;
313} __attribute__ ((packed));
314
315#define ADM_CMDRSP_COPP_OPEN 0x0001030A
316struct adm_copp_open_respond {
317 u32 status;
318 u16 copp_id;
319 u16 reserved;
320} __attribute__ ((packed));
321
322#define ASM_STREAM_PRIORITY_NORMAL 0
323#define ASM_STREAM_PRIORITY_LOW 1
324#define ASM_STREAM_PRIORITY_HIGH 2
325#define ASM_STREAM_PRIORITY_RESERVED 3
326
327#define ASM_END_POINT_DEVICE_MATRIX 0
328#define ASM_END_POINT_STREAM 1
329
330#define ASM_STREAM_CMD_CLOSE 0x00010BCD
331#define ASM_STREAM_CMD_FLUSH 0x00010BCE
332#define ASM_STREAM_CMD_SET_PP_PARAMS 0x00010BCF
333#define ASM_STREAM_CMD_GET_PP_PARAMS 0x00010BD0
334#define ASM_STREAM_CMDRSP_GET_PP_PARAMS 0x00010BD1
335#define ASM_SESSION_CMD_PAUSE 0x00010BD3
336#define ASM_SESSION_CMD_GET_SESSION_TIME 0x00010BD4
337#define ASM_DATA_CMD_EOS 0x00010BDB
338#define ASM_DATA_EVENT_EOS 0x00010BDD
339
340#define ASM_SERVICE_CMD_GET_STREAM_HANDLES 0x00010C0B
341#define ASM_STREAM_CMD_FLUSH_READBUFS 0x00010C09
342
343#define ASM_SESSION_EVENT_RX_UNDERFLOW 0x00010C17
344#define ASM_SESSION_EVENT_TX_OVERFLOW 0x00010C18
345#define ASM_SERVICE_CMD_GET_WALLCLOCK_TIME 0x00010C19
346#define ASM_DATA_CMDRSP_EOS 0x00010C1C
347
348/* ASM Data structures */
349
350/* common declarations */
351struct asm_pcm_cfg {
352 u16 ch_cfg;
353 u16 bits_per_sample;
354 u32 sample_rate;
355 u16 is_signed;
356 u16 interleaved;
357};
358
359struct asm_adpcm_cfg {
360 u16 ch_cfg;
361 u16 bits_per_sample;
362 u32 sample_rate;
363 u32 block_size;
364};
365
366struct asm_yadpcm_cfg {
367 u16 ch_cfg;
368 u16 bits_per_sample;
369 u32 sample_rate;
370};
371
372struct asm_midi_cfg {
373 u32 nMode;
374};
375
376struct asm_wma_cfg {
377 u16 format_tag;
378 u16 ch_cfg;
379 u32 sample_rate;
380 u32 ave_bytes_per_sec;
381 u16 block_align;
382 u16 valid_bits_per_sample;
383 u32 ch_mask;
384 u16 encode_opt;
385 u16 adv_encode_opt;
386 u16 adv_encode_opt2;
387 u32 drc_peak_ref;
388 u32 drc_peak_target;
389 u32 drc_ave_ref;
390 u32 drc_ave_target;
391};
392
393struct asm_aac_cfg {
394 u16 format;
395 u16 aot;
396 u16 ep_config;
397 u16 section_data_resilience;
398 u16 scalefactor_data_resilience;
399 u16 spectral_data_resilience;
400 u16 sbr_on;
401 u16 sbr_ps_on;
402 u16 ch_cfg;
403 u16 reserved;
404 u32 sample_rate;
405};
406
407struct asm_flac_cfg {
408 u16 stream_info_present;
409 u16 min_blk_size;
410 u16 max_blk_size;
411 u16 ch_cfg;
412 u16 sample_size;
413 u16 sample_rate;
414 u16 md5_sum;
415 u32 ext_sample_rate;
416 u32 min_frame_size;
417 u32 max_frame_size;
418};
419
420struct asm_vorbis_cfg {
421 u32 ch_cfg;
422 u32 bit_rate;
423 u32 min_bit_rate;
424 u32 max_bit_rate;
425 u16 bit_depth_pcm_sample;
426 u16 bit_stream_format;
427};
428
429struct asm_aac_read_cfg {
430 u32 bitrate;
431 u32 enc_mode;
432 u16 format;
433 u16 ch_cfg;
434 u32 sample_rate;
435};
436
437struct asm_amrnb_read_cfg {
438 u16 mode;
439 u16 dtx_mode;
440 u16 min_rate;
441 u16 max_rate;
442};
443
444struct asm_evrc_read_cfg {
445 u16 min_rate;
446 u16 max_rate;
447};
448
449struct asm_qcelp13_read_cfg {
450 u16 min_rate;
451 u16 max_rate;
452};
453
454struct asm_sbc_read_cfg {
455 u32 subband;
456 u32 block_len;
457 u32 ch_mode;
458 u32 alloc_method;
459 u32 bit_rate;
460 u32 sample_rate;
461};
462
463struct asm_sbc_bitrate {
464 u32 bitrate;
465};
466
467struct asm_aac_immed_decode {
468 u16 mode;
469 u16 padding;
470};
471
472struct asm_frame_meta_info {
473 u32 offset_to_frame;
474 u32 encoded_pcm_samples;
475 u32 msw_ts;
476 u32 lsw_ts;
477};
478
479/* Stream level commands */
480#define ASM_STREAM_CMD_OPEN_READ 0x00010BCB
481struct asm_stream_cmd_open_read {
482 struct apr_hdr hdr;
483 u32 uMode;
484 u32 src_endpoint;
485 u32 frames_per_buf;
486 u32 pre_proc_top;
487 u32 format;
488 u32 cfg_size;
489 union {
490 struct asm_pcm_cfg pcm_cfg;
491 struct asm_aac_read_cfg aac_cfg;
492 struct asm_amrnb_read_cfg amr_cfg;
493 struct asm_evrc_read_cfg evrc_cfg;
494 struct asm_qcelp13_read_cfg qcelp13_cfg;
495 struct asm_sbc_read_cfg sbc_cfg;
496 } __attribute__((packed)) read_cfg;
497} __attribute__((packed));
498
499/* Supported formats */
500#define LINEAR_PCM 0x00010BE5
501#define DTMF 0x00010BE6
502#define ADPCM 0x00010BE7
503#define YADPCM 0x00010BE8
504#define MP3 0x00010BE9
505#define MPEG4_AAC 0x00010BEA
506#define AMRNB_FS 0x00010BEB
507#define V13K_FS 0x00010BED
508#define EVRC_FS 0x00010BEE
509#define EVRCB_FS 0x00010BEF
510#define EVRCWB_FS 0x00010BF0
511#define MIDI 0x00010BF1
512#define SBC 0x00010BF2
513#define WMA_V10PRO 0x00010BF3
514#define WMA_V9 0x00010BF4
515#define AMR_WB_PLUS 0x00010BF5
516#define AC3_DECODER 0x00010BF6
517#define G711_ALAW_FS 0x00010BF7
518#define G711_MLAW_FS 0x00010BF8
519#define G711_PCM_FS 0x00010BF9
520
521#define ASM_STREAM_CMD_OPEN_WRITE 0x00010BCA
522struct asm_stream_cmd_open_write {
523 struct apr_hdr hdr;
524 u32 uMode;
525 u16 sink_endpoint;
526 u16 stream_handle;
527 u32 post_proc_top;
528 u32 format;
529 u32 cfg_size;
530 union {
531 struct asm_pcm_cfg pcm_cfg;
532 struct asm_adpcm_cfg adpcm_cfg;
533 struct asm_yadpcm_cfg yadpcm_cfg;
534 struct asm_midi_cfg midi_cfg;
535 struct asm_wma_cfg wma_cfg;
536 struct asm_aac_cfg aac_cfg;
537 struct asm_flac_cfg flac_cfg;
538 struct asm_vorbis_cfg vorbis_cfg;
539 } __attribute__((packed)) write_cfg;
540} __attribute__((packed));
541
542#define ASM_STREAM_CMD_OPEN_READWRITE 0x00010BCC
543/* pcm in; aac, amrnb, evrc, qcelp13, sbc out */
544struct asm_stream_cmd_open_read_pcmwrite {
545 struct apr_hdr hdr;
546 u32 uMode;
547 u32 post_proc_top;
548 u32 sample_rate;
549 u32 write_format;
550 u32 write_cfg_size;
551 u32 frames_per_buffer;
552 u32 read_format;
553 u32 read_cfg_size;
554 struct asm_pcm_cfg pcm_write_cfg;
555 union {
556 struct asm_pcm_cfg pcm_cfg;
557 struct asm_aac_read_cfg aac_cfg;
558 struct asm_amrnb_read_cfg amr_cfg;
559 struct asm_evrc_read_cfg evrc_cfg;
560 struct asm_qcelp13_read_cfg qcelp13_cfg;
561 struct asm_sbc_read_cfg sbc_cfg;
562 } __attribute__((packed)) read_cfg;
563} __attribute__((packed));
564
565/* adpcm in;pcm, aac, amrnb, evrc, qcelp13, sbc out */
566struct asm_stream_cmd_open_read_adpcmwrite {
567 struct apr_hdr hdr;
568 u32 uMode;
569 u32 post_proc_top;
570 u32 sample_rate;
571 u32 write_format;
572 u32 write_cfg_size;
573 u32 frames_per_buffer;
574 u32 read_format;
575 u32 read_cfg_size;
576 struct asm_adpcm_cfg adpcm_write_cfg;
577 union {
578 struct asm_pcm_cfg pcm_cfg;
579 struct asm_aac_read_cfg aac_cfg;
580 struct asm_amrnb_read_cfg amr_cfg;
581 struct asm_evrc_read_cfg evrc_cfg;
582 struct asm_qcelp13_read_cfg qcelp13_cfg;
583 struct asm_sbc_read_cfg sbc_cfg;
584 } __attribute__((packed)) read_cfg;
585} __attribute__((packed));
586
587/* yadpcm in:pcm, aac, amrnb, evrc, qcelp13, sbc out */
588struct asm_stream_cmd_open_read_yadpcmwrite {
589 struct apr_hdr hdr;
590 u32 uMode;
591 u32 post_proc_top;
592 u32 sample_rate;
593 u32 write_format;
594 u32 write_cfg_size;
595 u32 frames_per_buffer;
596 u32 read_format;
597 u32 read_cfg_size;
598 struct asm_yadpcm_cfg yadpcm_write_cfg;
599 union {
600 struct asm_pcm_cfg pcm_cfg;
601 struct asm_aac_read_cfg aac_cfg;
602 struct asm_amrnb_read_cfg amr_cfg;
603 struct asm_evrc_read_cfg evrc_cfg;
604 struct asm_qcelp13_read_cfg qcelp13_cfg;
605 struct asm_sbc_read_cfg sbc_cfg;
606 } __attribute__((packed)) read_cfg;
607} __attribute__((packed));
608
609/* midi in;pcm, aac, amrnb, evrc, qcelp13, sbc out */
610struct asm_stream_cmd_open_read_midiwrite {
611 struct apr_hdr hdr;
612 u32 uMode;
613 u32 post_proc_top;
614 u32 sample_rate;
615 u32 write_format;
616 u32 write_cfg_size;
617 u32 frames_per_buffer;
618 u32 read_format;
619 u32 read_cfg_size;
620 struct asm_midi_cfg midi_write_cfg;
621 union {
622 struct asm_pcm_cfg pcm_cfg;
623 struct asm_aac_read_cfg aac_cfg;
624 struct asm_amrnb_read_cfg amr_cfg;
625 struct asm_evrc_read_cfg evrc_cfg;
626 struct asm_qcelp13_read_cfg qcelp13_cfg;
627 struct asm_sbc_read_cfg sbc_cfg;
628 } __attribute__((packed)) read_cfg;
629} __attribute__((packed));
630
631/* wma in: pcm, aac, amrnb, evrc, qcelp13, sbc out */
632struct asm_stream_cmd_open_read_wmawrite {
633 struct apr_hdr hdr;
634 u32 uMode;
635 u32 post_proc_top;
636 u32 sample_rate;
637 u32 write_format;
638 u32 write_cfg_size;
639 u32 frames_per_buffer;
640 u32 read_format;
641 u32 read_cfg_size;
642 struct asm_wma_cfg wma_write_cfg;
643 union {
644 struct asm_pcm_cfg pcm_cfg;
645 struct asm_aac_read_cfg aac_cfg;
646 struct asm_amrnb_read_cfg amr_cfg;
647 struct asm_evrc_read_cfg evrc_cfg;
648 struct asm_qcelp13_read_cfg qcelp13_cfg;
649 struct asm_sbc_read_cfg sbc_cfg;
650 } __attribute__((packed)) read_cfg;
651} __attribute__((packed));
652
653/* aac in; pcm, aac, amrnb, evrc, qcelp13, sbc out */
654struct asm_stream_cmd_open_read_aacwrite {
655 struct apr_hdr hdr;
656 u32 uMode;
657 u32 post_proc_top;
658 u32 sample_rate;
659 u32 write_format;
660 u32 write_cfg_size;
661 u32 frames_per_buffer;
662 u32 read_format;
663 u32 read_cfg_size;
664 struct asm_aac_cfg aac_write_cfg;
665 union {
666 struct asm_pcm_cfg pcm_cfg;
667 struct asm_aac_read_cfg aac_cfg;
668 struct asm_amrnb_read_cfg amr_cfg;
669 struct asm_evrc_read_cfg evrc_cfg;
670 struct asm_qcelp13_read_cfg qcelp13_cfg;
671 struct asm_sbc_read_cfg sbc_cfg;
672 } __attribute__((packed)) read_cfg;
673} __attribute__((packed));
674
675/* flac in; pcm, aac, amrnb, evrc, qcelp13, sbc out */
676struct asm_stream_cmd_open_read_flacwrite {
677 struct apr_hdr hdr;
678 u32 uMode;
679 u32 post_proc_top;
680 u32 sample_rate;
681 u32 write_format;
682 u32 write_cfg_size;
683 u32 frames_per_buffer;
684 u32 read_format;
685 u32 read_cfg_size;
686 struct asm_flac_cfg flac_write_cfg;
687 union {
688 struct asm_pcm_cfg pcm_cfg;
689 struct asm_aac_read_cfg aac_cfg;
690 struct asm_amrnb_read_cfg amr_cfg;
691 struct asm_evrc_read_cfg evrc_cfg;
692 struct asm_qcelp13_read_cfg qcelp13_cfg;
693 struct asm_sbc_read_cfg sbc_cfg;
694 } __attribute__((packed)) read_cfg;
695} __attribute__((packed));
696
697/* vorbis in; pcm, aac, amrnb, evrc, qcelp13, sbc out */
698struct asm_stream_cmd_open_read_vorbiswrite {
699 struct apr_hdr hdr;
700 u32 uMode;
701 u32 post_proc_top;
702 u32 sample_rate;
703 u32 write_format;
704 u32 write_cfg_size;
705 u32 frames_per_buffer;
706 u32 read_format;
707 u32 read_cfg_size;
708 struct asm_vorbis_cfg vorbis_write_cfg;
709 union {
710 struct asm_pcm_cfg pcm_cfg;
711 struct asm_aac_read_cfg aac_cfg;
712 struct asm_amrnb_read_cfg amr_cfg;
713 struct asm_evrc_read_cfg evrc_cfg;
714 struct asm_qcelp13_read_cfg qcelp13_cfg;
715 struct asm_sbc_read_cfg sbc_cfg;
716 } __attribute__((packed)) read_cfg;
717} __attribute__((packed));
718
719
720#define ASM_STREAM_CMD_SET_ENCDEC_PARAM 0x00010C10
721struct asm_stream_cmd_set_readwrite_param{
722 struct apr_hdr hdr;
723 u32 param_id;
724 u16 param_size;
725 u16 padding;
726 union {
727 struct asm_sbc_bitrate sbc_bitrate;
728 struct asm_aac_immed_decode aac_dec;
729 } __attribute__((packed)) read_write_cfg;
730} __attribute__((packed));
731
732#define ASM_STREAM_CMD_GET_ENCDEC_PARAM 0x00010C11
733struct asm_stream_cmd_get_readwrite_param{
734 struct apr_hdr hdr;
735 u32 param_id;
736 u16 param_size;
737 u16 padding;
738 union {
739 struct asm_sbc_bitrate sbc_bitrate;
740 struct asm_aac_immed_decode aac_dec;
741 } __attribute__((packed)) read_write_cfg;
742} __attribute__((packed));
743
744#define ASM_STREAM _CMD_ADJUST_SAMPLES 0x00010C0A
745struct asm_stream_cmd_adjust_samples{
746 struct apr_hdr hdr;
747 u16 nsamples;
748 u16 reserved;
749} __attribute__((packed));
750
751#define ASM_STREAM_CMD_TAP_POPP_PCM 0x00010BF9
752struct asm_stream_cmd_tap_popp_pcm{
753 struct apr_hdr hdr;
754 u16 enable;
755 u16 reserved;
756 u32 module_id;
757} __attribute__((packed));
758
759/* Session Level commands */
760
761#define ASM_SESSION_CMD_RUN 0x00010BD2
762struct asm_stream_cmd_run{
763 struct apr_hdr hdr;
764 u32 flags;
765 u32 msw_ts;
766 u32 lsw_ts;
767} __attribute__((packed));
768
769/* Session level events */
770#define ASM_SESSION_CMD_REGISTER_FOR_RX_UNDERFLOW_EVENTS 0x00010BD5
771struct asm_stream_cmd_reg_rx_underflow_event{
772 struct apr_hdr hdr;
773 u16 enable;
774 u16 reserved;
775} __attribute__((packed));
776
777#define ASM_SESSION_CMD_REGISTER_FOR_TX_OVERFLOW_EVENTS 0x00010BD6
778struct asm_stream_cmd_reg_tx_overflow_event{
779 struct apr_hdr hdr;
780 u16 enable;
781 u16 reserved;
782} __attribute__((packed));
783
784/* Data Path commands */
785#define ASM_DATA_CMD_WRITE 0x00010BD9
786struct asm_stream_cmd_write{
787 struct apr_hdr hdr;
788 u32 buf_add;
789 u32 avail_bytes;
790 u32 msw_ts;
791 u32 lsw_ts;
792 u32 uflags;
793 u32 uid;
794} __attribute__((packed));
795
796#define ASM_DATA_CMD_READ 0x00010BDA
797struct asm_stream_cmd_read{
798 struct apr_hdr hdr;
799 u32 buf_add;
800 u32 buf_size;
801 u32 uid;
802} __attribute__((packed));
803
804#define ASM_DATA_CMD_MEDIA_FORMAT_UPDATE 0x00010BDC
805#define ASM_DATA_EVENT_MEDIA_FORMAT_UPDATE 0x00010BDE
806struct asm_stream_media_format_update{
807 struct apr_hdr hdr;
808 u32 format;
809 u32 cfg_size;
810 union {
811 struct asm_pcm_cfg pcm_cfg;
812 struct asm_adpcm_cfg adpcm_cfg;
813 struct asm_yadpcm_cfg yadpcm_cfg;
814 struct asm_midi_cfg midi_cfg;
815 struct asm_wma_cfg wma_cfg;
816 struct asm_aac_cfg aac_cfg;
817 struct asm_flac_cfg flac_cfg;
818 struct asm_vorbis_cfg vorbis_cfg;
819 } __attribute__((packed)) write_cfg;
820} __attribute__((packed));
821
822
823/* Command Responses */
824#define ASM_STREAM_CMDRSP_GET_ENCDEC_PARAM 0x00010C12
825struct asm_stream_cmdrsp_get_readwrite_param{
826 struct apr_hdr hdr;
827 u32 status;
828 u32 param_id;
829 u16 param_size;
830 u16 padding;
831 union {
832 struct asm_sbc_bitrate sbc_bitrate;
833 struct asm_aac_immed_decode aac_dec;
834 } __attribute__((packed)) read_write_cfg;
835} __attribute__((packed));
836
837
838#define ASM_SESSION_CMDRSP_GET_SESSION_TIME 0x00010BD8
839struct asm_stream_cmdrsp_get_session_time{
840 struct apr_hdr hdr;
841 u32 status;
842 u32 msw_ts;
843 u32 lsw_ts;
844} __attribute__((packed));
845
846#define ASM_DATA_EVENT_WRITE_DONE 0x00010BDF
847struct asm_data_event_write_done{
848 u32 buf_add;
849 u32 status;
850} __attribute__((packed));
851
852#define ASM_DATA_EVENT_READ_DONE 0x00010BE0
853struct asm_data_event_read_done{
854 u32 status;
855 u32 buffer_add;
856 u32 enc_frame_size;
857 u32 offset;
858 u32 msw_ts;
859 u32 lsw_ts;
860 u32 flags;
861 u32 num_frames;
862 u32 id;
863} __attribute__((packed));
864
865
866/* service level events */
867
868#define ASM_SERVICE_CMDRSP_GET_STREAM_HANDLES 0x00010C1B
869struct asm_svc_cmdrsp_get_strm_handles{
870 struct apr_hdr hdr;
871 u32 num_handles;
872 u32 stream_handles;
873} __attribute__((packed));
874
875
876#define ASM_SERVICE_CMDRSP_GET_WALLCLOCK_TIME 0x00010C1A
877struct asm_svc_cmdrsp_get_wallclock_time{
878 struct apr_hdr hdr;
879 u32 status;
880 u32 msw_ts;
881 u32 lsw_ts;
882} __attribute__((packed));
883
884/*
885 * Error code
886*/
887#define ADSP_EOK 0x00000000 /* Success / completed / no errors. */
888#define ADSP_EFAILED 0x00000001 /* General failure. */
889#define ADSP_EBADPARAM 0x00000002 /* Bad operation parameter(s). */
890#define ADSP_EUNSUPPORTED 0x00000003 /* Unsupported routine/operation. */
891#define ADSP_EVERSION 0x00000004 /* Unsupported version. */
892#define ADSP_EUNEXPECTED 0x00000005 /* Unexpected problem encountered. */
893#define ADSP_EPANIC 0x00000006 /* Unhandled problem occurred. */
894#define ADSP_ENORESOURCE 0x00000007 /* Unable to allocate resource(s). */
895#define ADSP_EHANDLE 0x00000008 /* Invalid handle. */
896#define ADSP_EALREADY 0x00000009 /* Operation is already processed. */
897#define ADSP_ENOTREADY 0x0000000A /* Operation not ready to be processed*/
898#define ADSP_EPENDING 0x0000000B /* Operation is pending completion*/
899#define ADSP_EBUSY 0x0000000C /* Operation could not be accepted or
900 processed. */
901#define ADSP_EABORTED 0x0000000D /* Operation aborted due to an error. */
902#define ADSP_EPREEMPTED 0x0000000E /* Operation preempted by higher priority*/
903#define ADSP_ECONTINUE 0x0000000F /* Operation requests intervention
904 to complete. */
905#define ADSP_EIMMEDIATE 0x00000010 /* Operation requests immediate
906 intervention to complete. */
907#define ADSP_ENOTIMPL 0x00000011 /* Operation is not implemented. */
908#define ADSP_ENEEDMORE 0x00000012 /* Operation needs more data or resources*/
909
910#endif /*_APR_AUDIO_H_*/