/arch/arm/mach-fsm/include/mach/qdsp5v2/lpa_hw.h
C++ Header | 252 lines | 175 code | 27 blank | 50 comment | 0 complexity | ae6c9177f46e28cace2a9610e8d2158e MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29#ifndef __MACH_QDSP5_V2_LPA_HW_H__
30#define __MACH_QDSP5_V2_LPA_HW_H__
31
32#define LPA_MAX_BUF_SIZE 0x30000
33
34/* LPA Output config registers */
35enum {
36 LPA_OBUF_CONTROL = 0x00000000,
37 LPA_OBUF_CODEC = 0x00000004,
38 LPA_OBUF_HLB_MIN_ADDR = 0x00000008,
39 LPA_OBUF_HLB_MAX_ADDR = 0x0000000C,
40 LPA_OBUF_HLB_WPTR = 0x00000010,
41 LPA_OBUF_HLB_VOLUME_CONTROL = 0x00000014,
42 LPA_OBUF_LLB_MIN_ADDR = 0x00000018,
43 LPA_OBUF_LLB_MAX_ADDR = 0x0000001C,
44 LPA_OBUF_SB_MIN_ADDR = 0x00000020,
45 LPA_OBUF_SB_MAX_ADDR = 0x00000024,
46 LPA_OBUF_INTR_ENABLE = 0x00000028,
47 LPA_OBUF_INTR_STATUS = 0x0000002C,
48 LPA_OBUF_WMARK_ASSIGN = 0x00000030,
49 LPA_OBUF_WMARK_0_LLB = 0x00000034,
50 LPA_OBUF_WMARK_1_LLB = 0x00000038,
51 LPA_OBUF_WMARK_2_LLB = 0x0000003C,
52 LPA_OBUF_WMARK_3_LLB = 0x00000040,
53 LPA_OBUF_WMARK_HLB = 0x00000044,
54 LPA_OBUF_WMARK_SB = 0x00000048,
55 LPA_OBUF_RDPTR_LLB = 0x0000004C,
56 LPA_OBUF_RDPTR_HLB = 0x00000050,
57 LPA_OBUF_WRPTR_SB = 0x00000054,
58 LPA_OBUF_UTC_CONFIG = 0x00000058,
59 LPA_OBUF_UTC_INTR_LOW = 0x0000005C,
60 LPA_OBUF_UTC_INTR_HIGH = 0x00000060,
61 LPA_OBUF_UTC_LOW = 0x00000064,
62 LPA_OBUF_UTC_HIGH = 0x00000068,
63 LPA_OBUF_MISR = 0x0000006C,
64 LPA_OBUF_STATUS = 0x00000070,
65 LPA_OBUF_ACK = 0x00000074,
66 LPA_OBUF_MEMORY_CONTROL = 0x00000078,
67 LPA_OBUF_MEMORY_STATUS = 0x0000007C,
68 LPA_OBUF_MEMORY_TIME_CONTROL = 0x00000080,
69 LPA_OBUF_ACC_LV = 0x00000084,
70 LPA_OBUF_ACC_HV = 0x0000008c,
71 LPA_OBUF_RESETS = 0x00000090,
72 LPA_OBUF_TESTBUS = 0x00000094,
73};
74
75/* OBUF_CODEC definition */
76#define LPA_OBUF_CODEC_RESERVED31_22_BMSK 0xffc00000
77#define LPA_OBUF_CODEC_RESERVED31_22_SHFT 0x16
78#define LPA_OBUF_CODEC_LOAD_BMSK 0x200000
79#define LPA_OBUF_CODEC_LOAD_SHFT 0x15
80#define LPA_OBUF_CODEC_CODEC_INTF_EN_BMSK 0x100000
81#define LPA_OBUF_CODEC_CODEC_INTF_EN_SHFT 0x14
82#define LPA_OBUF_CODEC_SAMP_BMSK 0xf0000
83#define LPA_OBUF_CODEC_SAMP_SHFT 0x10
84#define LPA_OBUF_CODEC_BITS_PER_CHAN_BMSK 0xc000
85#define LPA_OBUF_CODEC_BITS_PER_CHAN_SHFT 0xe
86#define LPA_OBUF_CODEC_RESERVED_13_7_BMSK 0x3f80
87#define LPA_OBUF_CODEC_RESERVED_13_7_SHFT 0x7
88#define LPA_OBUF_CODEC_INTF_BMSK 0x70
89#define LPA_OBUF_CODEC_INTF_SHFT 0x4
90#define LPA_OBUF_CODEC_NUM_CHAN_BMSK 0xf
91#define LPA_OBUF_CODEC_NUM_CHAN_SHFT 0
92
93/* OBUF_CONTROL definition */
94#define LPA_OBUF_CONTROL_RESERVED31_9_BMSK 0xfffffe00
95#define LPA_OBUF_CONTROL_RESERVED31_9_SHFT 0x9
96#define LPA_OBUF_CONTROL_TEST_EN_BMSK 0x100
97#define LPA_OBUF_CONTROL_TEST_EN_SHFT 0x8
98#define LPA_OBUF_CONTROL_LLB_CLR_CMD_BMSK 0x80
99#define LPA_OBUF_CONTROL_LLB_CLR_CMD_SHFT 0x7
100#define LPA_OBUF_CONTROL_SB_SAT_EN_BMSK 0x40
101#define LPA_OBUF_CONTROL_SB_SAT_EN_SHFT 0x6
102#define LPA_OBUF_CONTROL_LLB_SAT_EN_BMSK 0x20
103#define LPA_OBUF_CONTROL_LLB_SAT_EN_SHFT 0x5
104#define LPA_OBUF_CONTROL_RESERVED4_BMSK 0x10
105#define LPA_OBUF_CONTROL_RESERVED4_SHFT 0x4
106#define LPA_OBUF_CONTROL_LLB_ACC_EN_BMSK 0x8
107#define LPA_OBUF_CONTROL_LLB_ACC_EN_SHFT 0x3
108#define LPA_OBUF_CONTROL_HLB_EN_BMSK 0x4
109#define LPA_OBUF_CONTROL_HLB_EN_SHFT 0x2
110#define LPA_OBUF_CONTROL_LLB_EN_BMSK 0x2
111#define LPA_OBUF_CONTROL_LLB_EN_SHFT 0x1
112#define LPA_OBUF_CONTROL_SB_EN_BMSK 0x1
113#define LPA_OBUF_CONTROL_SB_EN_SHFT 0
114
115/* OBUF_RESET definition */
116#define LPA_OBUF_RESETS_MISR_RESET 0x1
117#define LPA_OBUF_RESETS_OVERALL_RESET 0x2
118
119/* OBUF_STATUS definition */
120#define LPA_OBUF_STATUS_RESET_DONE 0x80000
121#define LPA_OBUF_STATUS_LLB_CLR_BMSK 0x40000
122#define LPA_OBUF_STATUS_LLB_CLR_SHFT 0x12
123
124/* OBUF_HLB_MIN_ADDR definition */
125#define LPA_OBUF_HLB_MIN_ADDR_LOAD_BMSK 0x40000
126#define LPA_OBUF_HLB_MIN_ADDR_SEG_BMSK 0x3e000
127
128/* OBUF_HLB_MAX_ADDR definition */
129#define LPA_OBUF_HLB_MAX_ADDR_SEG_BMSK 0x3fff8
130
131/* OBUF_LLB_MIN_ADDR definition */
132#define LPA_OBUF_LLB_MIN_ADDR_LOAD_BMSK 0x40000
133#define LPA_OBUF_LLB_MIN_ADDR_SEG_BMSK 0x3e000
134
135/* OBUF_LLB_MAX_ADDR definition */
136#define LPA_OBUF_LLB_MAX_ADDR_SEG_BMSK 0x3ff8
137#define LPA_OBUF_LLB_MAX_ADDR_SEG_SHFT 0x3
138
139/* OBUF_SB_MIN_ADDR definition */
140#define LPA_OBUF_SB_MIN_ADDR_LOAD_BMSK 0x4000
141#define LPA_OBUF_SB_MIN_ADDR_SEG_BMSK 0x3e00
142
143/* OBUF_SB_MAX_ADDR definition */
144#define LPA_OBUF_SB_MAX_ADDR_SEG_BMSK 0x3ff8
145
146/* OBUF_MEMORY_CONTROL definition */
147#define LPA_OBUF_MEM_CTL_PWRUP_BMSK 0xfff
148#define LPA_OBUF_MEM_CTL_PWRUP_SHFT 0x0
149
150/* OBUF_INTR_ENABLE definition */
151#define LPA_OBUF_INTR_EN_BMSK 0x3
152
153/* OBUF_WMARK_ASSIGN definition */
154#define LPA_OBUF_WMARK_ASSIGN_BMSK 0xF
155#define LPA_OBUF_WMARK_ASSIGN_DONE 0xF
156
157/* OBUF_WMARK_n_LLB definition */
158#define LPA_OBUF_WMARK_n_LLB_ADDR(n) (0x00000034 + 0x4 * (n))
159#define LPA_OBUF_LLB_WMARK_CTRL_BMSK 0xc0000
160#define LPA_OBUF_LLB_WMARK_CTRL_SHFT 0x12
161#define LPA_OBUF_LLB_WMARK_MAP_BMSK 0xf00000
162#define LPA_OBUF_LLB_WMARK_MAP_SHFT 0x14
163
164/* OBUF_WMARK_SB definition */
165#define LPA_OBUF_SB_WMARK_CTRL_BMSK 0xc0000
166#define LPA_OBUF_SB_WMARK_CTRL_SHFT 0x12
167#define LPA_OBUF_SB_WMARK_MAP_BMSK 0xf00000
168#define LPA_OBUF_SB_WMARK_MAP_SHFT 0x14
169
170/* OBUF_WMARK_HLB definition */
171#define LPA_OBUF_HLB_WMARK_CTRL_BMSK 0xc0000
172#define LPA_OBUF_HLB_WMARK_CTRL_SHFT 0x12
173#define LPA_OBUF_HLB_WMARK_MAP_BMSK 0xf00000
174#define LPA_OBUF_HLB_WMARK_MAP_SHFT 0x14
175
176/* OBUF_UTC_CONFIG definition */
177#define LPA_OBUF_UTC_CONFIG_MAP_BMSK 0xf0
178#define LPA_OBUF_UTC_CONFIG_MAP_SHFT 0x4
179#define LPA_OBUF_UTC_CONFIG_EN_BMSK 0x1
180#define LPA_OBUF_UTC_CONFIG_EN_SHFT 0
181#define LPA_OBUF_UTC_CONFIG_NO_INTR 0xF
182
183/* OBUF_ACK definition */
184#define LPA_OBUF_ACK_RESET_DONE_BMSK 0x80000
185#define LPA_OBUF_ACK_RESET_DONE_SHFT 0x13
186enum {
187 LPA_SAMPLE_RATE_8KHZ = 0x0000,
188 LPA_SAMPLE_RATE_11P025KHZ = 0x0001,
189 LPA_SAMPLE_RATE_16KHZ = 0x0002,
190 LPA_SAMPLE_RATE_22P05KHZ = 0x0003,
191 LPA_SAMPLE_RATE_32KHZ = 0x0004,
192 LPA_SAMPLE_RATE_44P1KHZ = 0x0005,
193 LPA_SAMPLE_RATE_48KHZ = 0x0006,
194 LPA_SAMPLE_RATE_64KHZ = 0x0007,
195 LPA_SAMPLE_RATE_96KHZ = 0x0008,
196};
197
198enum {
199 LPA_BITS_PER_CHAN_16BITS = 0x0000,
200 LPA_BITS_PER_CHAN_24BITS = 0x0001,
201 LPA_BITS_PER_CHAN_32BITS = 0x0002,
202 LPA_BITS_PER_CHAN_RESERVED = 0x0003,
203};
204
205enum {
206 LPA_INTF_WB_CODEC = 0x0000,
207 LPA_INTF_SDAC = 0x0001,
208 LPA_INTF_MI2S = 0x0002,
209 LPA_INTF_RESERVED = 0x0003,
210};
211
212enum {
213 LPA_BUF_ID_HLB, /* HLB buffer */
214 LPA_BUF_ID_LLB, /* LLB buffer */
215 LPA_BUF_ID_SB, /* SB buffer */
216 LPA_BUF_ID_UTC,
217};
218
219/* WB_CODEC & SDAC can only support 16bit mono/stereo.
220 * MI2S can bit format and number of channel
221 */
222enum {
223 LPA_NUM_CHAN_MONO = 0x0000,
224 LPA_NUM_CHAN_STEREO = 0x0001,
225 LPA_NUM_CHAN_5P1 = 0x0002,
226 LPA_NUM_CHAN_7P1 = 0x0003,
227 LPA_NUM_CHAN_4_CHANNEL = 0x0004,
228};
229
230enum {
231 LPA_WMARK_CTL_DISABLED = 0x0,
232 LPA_WMARK_CTL_NON_BLOCK = 0x1,
233 LPA_WMARK_CTL_ZERO_INSERT = 0x2,
234 LPA_WMARK_CTL_RESERVED = 0x3
235};
236
237struct lpa_mem_bank_select {
238 u32 b0:1; /*RAM bank 0 16KB=2Kx64(0) */
239 u32 b1:1; /*RAM bank 1 16KB=2Kx64(0) */
240 u32 b2:1; /*RAM bank 2 16KB=2Kx64(0) */
241 u32 b3:1; /*RAM bank 3 16KB=2Kx64(0) */
242 u32 b4:1; /*RAM bank 4 16KB=2Kx64(1) */
243 u32 b5:1; /*RAM bank 5 16KB=2Kx64(1) */
244 u32 b6:1; /*RAM bank 6 16KB=2Kx64(1) */
245 u32 b7:1; /*RAM bank 7 16KB=2Kx64(1) */
246 u32 b8:1; /*RAM bank 8 16KB=4Kx32(0) */
247 u32 b9:1; /*RAM bank 9 16KB=4Kx32(1) */
248 u32 b10:1; /*RAM bank 10 16KB=4Kx32(2) */
249 u32 llb:1; /*RAM bank 11 16KB=4Kx32(3) */
250};
251
252#endif