/arch/arm/mach-davinci/include/mach/irqs.h
C++ Header | 506 lines | 448 code | 21 blank | 37 comment | 0 complexity | 16a276053a26c56cdb0b384fea73042a MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
1/*
2 * DaVinci interrupt controller definitions
3 *
4 * Copyright (C) 2006 Texas Instruments.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 */
27#ifndef __ASM_ARCH_IRQS_H
28#define __ASM_ARCH_IRQS_H
29
30/* Base address */
31#define DAVINCI_ARM_INTC_BASE 0x01C48000
32
33#define DAVINCI_INTC_TYPE_AINTC 0
34#define DAVINCI_INTC_TYPE_CP_INTC 1
35
36/* Interrupt lines */
37#define IRQ_VDINT0 0
38#define IRQ_VDINT1 1
39#define IRQ_VDINT2 2
40#define IRQ_HISTINT 3
41#define IRQ_H3AINT 4
42#define IRQ_PRVUINT 5
43#define IRQ_RSZINT 6
44#define IRQ_VFOCINT 7
45#define IRQ_VENCINT 8
46#define IRQ_ASQINT 9
47#define IRQ_IMXINT 10
48#define IRQ_VLCDINT 11
49#define IRQ_USBINT 12
50#define IRQ_EMACINT 13
51
52#define IRQ_CCINT0 16
53#define IRQ_CCERRINT 17
54#define IRQ_TCERRINT0 18
55#define IRQ_TCERRINT 19
56#define IRQ_PSCIN 20
57
58#define IRQ_IDE 22
59#define IRQ_HPIINT 23
60#define IRQ_MBXINT 24
61#define IRQ_MBRINT 25
62#define IRQ_MMCINT 26
63#define IRQ_SDIOINT 27
64#define IRQ_MSINT 28
65#define IRQ_DDRINT 29
66#define IRQ_AEMIFINT 30
67#define IRQ_VLQINT 31
68#define IRQ_TINT0_TINT12 32
69#define IRQ_TINT0_TINT34 33
70#define IRQ_TINT1_TINT12 34
71#define IRQ_TINT1_TINT34 35
72#define IRQ_PWMINT0 36
73#define IRQ_PWMINT1 37
74#define IRQ_PWMINT2 38
75#define IRQ_I2C 39
76#define IRQ_UARTINT0 40
77#define IRQ_UARTINT1 41
78#define IRQ_UARTINT2 42
79#define IRQ_SPINT0 43
80#define IRQ_SPINT1 44
81
82#define IRQ_DSP2ARM0 46
83#define IRQ_DSP2ARM1 47
84#define IRQ_GPIO0 48
85#define IRQ_GPIO1 49
86#define IRQ_GPIO2 50
87#define IRQ_GPIO3 51
88#define IRQ_GPIO4 52
89#define IRQ_GPIO5 53
90#define IRQ_GPIO6 54
91#define IRQ_GPIO7 55
92#define IRQ_GPIOBNK0 56
93#define IRQ_GPIOBNK1 57
94#define IRQ_GPIOBNK2 58
95#define IRQ_GPIOBNK3 59
96#define IRQ_GPIOBNK4 60
97#define IRQ_COMMTX 61
98#define IRQ_COMMRX 62
99#define IRQ_EMUINT 63
100
101#define DAVINCI_N_AINTC_IRQ 64
102
103#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34
104
105/* DaVinci DM6467-specific Interrupts */
106#define IRQ_DM646X_VP_VERTINT0 0
107#define IRQ_DM646X_VP_VERTINT1 1
108#define IRQ_DM646X_VP_VERTINT2 2
109#define IRQ_DM646X_VP_VERTINT3 3
110#define IRQ_DM646X_VP_ERRINT 4
111#define IRQ_DM646X_RESERVED_1 5
112#define IRQ_DM646X_RESERVED_2 6
113#define IRQ_DM646X_WDINT 7
114#define IRQ_DM646X_CRGENINT0 8
115#define IRQ_DM646X_CRGENINT1 9
116#define IRQ_DM646X_TSIFINT0 10
117#define IRQ_DM646X_TSIFINT1 11
118#define IRQ_DM646X_VDCEINT 12
119#define IRQ_DM646X_USBINT 13
120#define IRQ_DM646X_USBDMAINT 14
121#define IRQ_DM646X_PCIINT 15
122#define IRQ_DM646X_TCERRINT2 20
123#define IRQ_DM646X_TCERRINT3 21
124#define IRQ_DM646X_IDE 22
125#define IRQ_DM646X_HPIINT 23
126#define IRQ_DM646X_EMACRXTHINT 24
127#define IRQ_DM646X_EMACRXINT 25
128#define IRQ_DM646X_EMACTXINT 26
129#define IRQ_DM646X_EMACMISCINT 27
130#define IRQ_DM646X_MCASP0TXINT 28
131#define IRQ_DM646X_MCASP0RXINT 29
132#define IRQ_DM646X_RESERVED_3 31
133#define IRQ_DM646X_MCASP1TXINT 32
134#define IRQ_DM646X_VLQINT 38
135#define IRQ_DM646X_UARTINT2 42
136#define IRQ_DM646X_SPINT0 43
137#define IRQ_DM646X_SPINT1 44
138#define IRQ_DM646X_DSP2ARMINT 45
139#define IRQ_DM646X_RESERVED_4 46
140#define IRQ_DM646X_PSCINT 47
141#define IRQ_DM646X_GPIO0 48
142#define IRQ_DM646X_GPIO1 49
143#define IRQ_DM646X_GPIO2 50
144#define IRQ_DM646X_GPIO3 51
145#define IRQ_DM646X_GPIO4 52
146#define IRQ_DM646X_GPIO5 53
147#define IRQ_DM646X_GPIO6 54
148#define IRQ_DM646X_GPIO7 55
149#define IRQ_DM646X_GPIOBNK0 56
150#define IRQ_DM646X_GPIOBNK1 57
151#define IRQ_DM646X_GPIOBNK2 58
152#define IRQ_DM646X_DDRINT 59
153#define IRQ_DM646X_AEMIFINT 60
154
155/* DaVinci DM355-specific Interrupts */
156#define IRQ_DM355_CCDC_VDINT0 0
157#define IRQ_DM355_CCDC_VDINT1 1
158#define IRQ_DM355_CCDC_VDINT2 2
159#define IRQ_DM355_IPIPE_HST 3
160#define IRQ_DM355_H3AINT 4
161#define IRQ_DM355_IPIPE_SDR 5
162#define IRQ_DM355_IPIPEIFINT 6
163#define IRQ_DM355_OSDINT 7
164#define IRQ_DM355_VENCINT 8
165#define IRQ_DM355_IMCOPINT 11
166#define IRQ_DM355_RTOINT 13
167#define IRQ_DM355_TINT4 13
168#define IRQ_DM355_TINT2_TINT12 13
169#define IRQ_DM355_UARTINT2 14
170#define IRQ_DM355_TINT5 14
171#define IRQ_DM355_TINT2_TINT34 14
172#define IRQ_DM355_TINT6 15
173#define IRQ_DM355_TINT3_TINT12 15
174#define IRQ_DM355_SPINT1_0 17
175#define IRQ_DM355_SPINT1_1 18
176#define IRQ_DM355_SPINT2_0 19
177#define IRQ_DM355_SPINT2_1 21
178#define IRQ_DM355_TINT7 22
179#define IRQ_DM355_TINT3_TINT34 22
180#define IRQ_DM355_SDIOINT0 23
181#define IRQ_DM355_MMCINT0 26
182#define IRQ_DM355_MSINT 26
183#define IRQ_DM355_MMCINT1 27
184#define IRQ_DM355_PWMINT3 28
185#define IRQ_DM355_SDIOINT1 31
186#define IRQ_DM355_SPINT0_0 42
187#define IRQ_DM355_SPINT0_1 43
188#define IRQ_DM355_GPIO0 44
189#define IRQ_DM355_GPIO1 45
190#define IRQ_DM355_GPIO2 46
191#define IRQ_DM355_GPIO3 47
192#define IRQ_DM355_GPIO4 48
193#define IRQ_DM355_GPIO5 49
194#define IRQ_DM355_GPIO6 50
195#define IRQ_DM355_GPIO7 51
196#define IRQ_DM355_GPIO8 52
197#define IRQ_DM355_GPIO9 53
198#define IRQ_DM355_GPIOBNK0 54
199#define IRQ_DM355_GPIOBNK1 55
200#define IRQ_DM355_GPIOBNK2 56
201#define IRQ_DM355_GPIOBNK3 57
202#define IRQ_DM355_GPIOBNK4 58
203#define IRQ_DM355_GPIOBNK5 59
204#define IRQ_DM355_GPIOBNK6 60
205
206/* DaVinci DM365-specific Interrupts */
207#define IRQ_DM365_INSFINT 7
208#define IRQ_DM365_IMXINT1 8
209#define IRQ_DM365_IMXINT0 10
210#define IRQ_DM365_KLD_ARMINT 10
211#define IRQ_DM365_IMCOPINT 11
212#define IRQ_DM365_RTOINT 13
213#define IRQ_DM365_TINT5 14
214#define IRQ_DM365_TINT6 15
215#define IRQ_DM365_SPINT2_1 21
216#define IRQ_DM365_TINT7 22
217#define IRQ_DM365_SDIOINT0 23
218#define IRQ_DM365_MMCINT1 27
219#define IRQ_DM365_PWMINT3 28
220#define IRQ_DM365_RTCINT 29
221#define IRQ_DM365_SDIOINT1 31
222#define IRQ_DM365_SPIINT0_0 42
223#define IRQ_DM365_SPIINT3_0 43
224#define IRQ_DM365_GPIO0 44
225#define IRQ_DM365_GPIO1 45
226#define IRQ_DM365_GPIO2 46
227#define IRQ_DM365_GPIO3 47
228#define IRQ_DM365_GPIO4 48
229#define IRQ_DM365_GPIO5 49
230#define IRQ_DM365_GPIO6 50
231#define IRQ_DM365_GPIO7 51
232#define IRQ_DM365_EMAC_RXTHRESH 52
233#define IRQ_DM365_EMAC_RXPULSE 53
234#define IRQ_DM365_EMAC_TXPULSE 54
235#define IRQ_DM365_EMAC_MISCPULSE 55
236#define IRQ_DM365_GPIO12 56
237#define IRQ_DM365_GPIO13 57
238#define IRQ_DM365_GPIO14 58
239#define IRQ_DM365_GPIO15 59
240#define IRQ_DM365_ADCINT 59
241#define IRQ_DM365_KEYINT 60
242#define IRQ_DM365_TCERRINT2 61
243#define IRQ_DM365_TCERRINT3 62
244#define IRQ_DM365_EMUINT 63
245
246/* DA8XX interrupts */
247#define IRQ_DA8XX_COMMTX 0
248#define IRQ_DA8XX_COMMRX 1
249#define IRQ_DA8XX_NINT 2
250#define IRQ_DA8XX_EVTOUT0 3
251#define IRQ_DA8XX_EVTOUT1 4
252#define IRQ_DA8XX_EVTOUT2 5
253#define IRQ_DA8XX_EVTOUT3 6
254#define IRQ_DA8XX_EVTOUT4 7
255#define IRQ_DA8XX_EVTOUT5 8
256#define IRQ_DA8XX_EVTOUT6 9
257#define IRQ_DA8XX_EVTOUT7 10
258#define IRQ_DA8XX_CCINT0 11
259#define IRQ_DA8XX_CCERRINT 12
260#define IRQ_DA8XX_TCERRINT0 13
261#define IRQ_DA8XX_AEMIFINT 14
262#define IRQ_DA8XX_I2CINT0 15
263#define IRQ_DA8XX_MMCSDINT0 16
264#define IRQ_DA8XX_MMCSDINT1 17
265#define IRQ_DA8XX_ALLINT0 18
266#define IRQ_DA8XX_RTC 19
267#define IRQ_DA8XX_SPINT0 20
268#define IRQ_DA8XX_TINT12_0 21
269#define IRQ_DA8XX_TINT34_0 22
270#define IRQ_DA8XX_TINT12_1 23
271#define IRQ_DA8XX_TINT34_1 24
272#define IRQ_DA8XX_UARTINT0 25
273#define IRQ_DA8XX_KEYMGRINT 26
274#define IRQ_DA8XX_SECINT 26
275#define IRQ_DA8XX_SECKEYERR 26
276#define IRQ_DA8XX_CHIPINT0 28
277#define IRQ_DA8XX_CHIPINT1 29
278#define IRQ_DA8XX_CHIPINT2 30
279#define IRQ_DA8XX_CHIPINT3 31
280#define IRQ_DA8XX_TCERRINT1 32
281#define IRQ_DA8XX_C0_RX_THRESH_PULSE 33
282#define IRQ_DA8XX_C0_RX_PULSE 34
283#define IRQ_DA8XX_C0_TX_PULSE 35
284#define IRQ_DA8XX_C0_MISC_PULSE 36
285#define IRQ_DA8XX_C1_RX_THRESH_PULSE 37
286#define IRQ_DA8XX_C1_RX_PULSE 38
287#define IRQ_DA8XX_C1_TX_PULSE 39
288#define IRQ_DA8XX_C1_MISC_PULSE 40
289#define IRQ_DA8XX_MEMERR 41
290#define IRQ_DA8XX_GPIO0 42
291#define IRQ_DA8XX_GPIO1 43
292#define IRQ_DA8XX_GPIO2 44
293#define IRQ_DA8XX_GPIO3 45
294#define IRQ_DA8XX_GPIO4 46
295#define IRQ_DA8XX_GPIO5 47
296#define IRQ_DA8XX_GPIO6 48
297#define IRQ_DA8XX_GPIO7 49
298#define IRQ_DA8XX_GPIO8 50
299#define IRQ_DA8XX_I2CINT1 51
300#define IRQ_DA8XX_LCDINT 52
301#define IRQ_DA8XX_UARTINT1 53
302#define IRQ_DA8XX_MCASPINT 54
303#define IRQ_DA8XX_ALLINT1 55
304#define IRQ_DA8XX_SPINT1 56
305#define IRQ_DA8XX_UHPI_INT1 57
306#define IRQ_DA8XX_USB_INT 58
307#define IRQ_DA8XX_IRQN 59
308#define IRQ_DA8XX_RWAKEUP 60
309#define IRQ_DA8XX_UARTINT2 61
310#define IRQ_DA8XX_DFTSSINT 62
311#define IRQ_DA8XX_EHRPWM0 63
312#define IRQ_DA8XX_EHRPWM0TZ 64
313#define IRQ_DA8XX_EHRPWM1 65
314#define IRQ_DA8XX_EHRPWM1TZ 66
315#define IRQ_DA8XX_ECAP0 69
316#define IRQ_DA8XX_ECAP1 70
317#define IRQ_DA8XX_ECAP2 71
318#define IRQ_DA8XX_ARMCLKSTOPREQ 90
319
320/* DA830 specific interrupts */
321#define IRQ_DA830_MPUERR 27
322#define IRQ_DA830_IOPUERR 27
323#define IRQ_DA830_BOOTCFGERR 27
324#define IRQ_DA830_EHRPWM2 67
325#define IRQ_DA830_EHRPWM2TZ 68
326#define IRQ_DA830_EQEP0 72
327#define IRQ_DA830_EQEP1 73
328#define IRQ_DA830_T12CMPINT0_0 74
329#define IRQ_DA830_T12CMPINT1_0 75
330#define IRQ_DA830_T12CMPINT2_0 76
331#define IRQ_DA830_T12CMPINT3_0 77
332#define IRQ_DA830_T12CMPINT4_0 78
333#define IRQ_DA830_T12CMPINT5_0 79
334#define IRQ_DA830_T12CMPINT6_0 80
335#define IRQ_DA830_T12CMPINT7_0 81
336#define IRQ_DA830_T12CMPINT0_1 82
337#define IRQ_DA830_T12CMPINT1_1 83
338#define IRQ_DA830_T12CMPINT2_1 84
339#define IRQ_DA830_T12CMPINT3_1 85
340#define IRQ_DA830_T12CMPINT4_1 86
341#define IRQ_DA830_T12CMPINT5_1 87
342#define IRQ_DA830_T12CMPINT6_1 88
343#define IRQ_DA830_T12CMPINT7_1 89
344
345#define DA830_N_CP_INTC_IRQ 96
346
347/* DA850 speicific interrupts */
348#define IRQ_DA850_MPUADDRERR0 27
349#define IRQ_DA850_MPUPROTERR0 27
350#define IRQ_DA850_IOPUADDRERR0 27
351#define IRQ_DA850_IOPUPROTERR0 27
352#define IRQ_DA850_IOPUADDRERR1 27
353#define IRQ_DA850_IOPUPROTERR1 27
354#define IRQ_DA850_IOPUADDRERR2 27
355#define IRQ_DA850_IOPUPROTERR2 27
356#define IRQ_DA850_BOOTCFG_ADDR_ERR 27
357#define IRQ_DA850_BOOTCFG_PROT_ERR 27
358#define IRQ_DA850_MPUADDRERR1 27
359#define IRQ_DA850_MPUPROTERR1 27
360#define IRQ_DA850_IOPUADDRERR3 27
361#define IRQ_DA850_IOPUPROTERR3 27
362#define IRQ_DA850_IOPUADDRERR4 27
363#define IRQ_DA850_IOPUPROTERR4 27
364#define IRQ_DA850_IOPUADDRERR5 27
365#define IRQ_DA850_IOPUPROTERR5 27
366#define IRQ_DA850_MIOPU_BOOTCFG_ERR 27
367#define IRQ_DA850_SATAINT 67
368#define IRQ_DA850_TINT12_2 68
369#define IRQ_DA850_TINT34_2 68
370#define IRQ_DA850_TINTALL_2 68
371#define IRQ_DA850_MMCSDINT0_1 72
372#define IRQ_DA850_MMCSDINT1_1 73
373#define IRQ_DA850_T12CMPINT0_2 74
374#define IRQ_DA850_T12CMPINT1_2 75
375#define IRQ_DA850_T12CMPINT2_2 76
376#define IRQ_DA850_T12CMPINT3_2 77
377#define IRQ_DA850_T12CMPINT4_2 78
378#define IRQ_DA850_T12CMPINT5_2 79
379#define IRQ_DA850_T12CMPINT6_2 80
380#define IRQ_DA850_T12CMPINT7_2 81
381#define IRQ_DA850_T12CMPINT0_3 82
382#define IRQ_DA850_T12CMPINT1_3 83
383#define IRQ_DA850_T12CMPINT2_3 84
384#define IRQ_DA850_T12CMPINT3_3 85
385#define IRQ_DA850_T12CMPINT4_3 86
386#define IRQ_DA850_T12CMPINT5_3 87
387#define IRQ_DA850_T12CMPINT6_3 88
388#define IRQ_DA850_T12CMPINT7_3 89
389#define IRQ_DA850_RPIINT 91
390#define IRQ_DA850_VPIFINT 92
391#define IRQ_DA850_CCINT1 93
392#define IRQ_DA850_CCERRINT1 94
393#define IRQ_DA850_TCERRINT2 95
394#define IRQ_DA850_TINT12_3 96
395#define IRQ_DA850_TINT34_3 96
396#define IRQ_DA850_TINTALL_3 96
397#define IRQ_DA850_MCBSP0RINT 97
398#define IRQ_DA850_MCBSP0XINT 98
399#define IRQ_DA850_MCBSP1RINT 99
400#define IRQ_DA850_MCBSP1XINT 100
401
402#define DA850_N_CP_INTC_IRQ 101
403
404
405/* TNETV107X specific interrupts */
406#define IRQ_TNETV107X_TDM1_TXDMA 0
407#define IRQ_TNETV107X_EXT_INT_0 1
408#define IRQ_TNETV107X_EXT_INT_1 2
409#define IRQ_TNETV107X_GPIO_INT12 3
410#define IRQ_TNETV107X_GPIO_INT13 4
411#define IRQ_TNETV107X_TIMER_0_TINT12 5
412#define IRQ_TNETV107X_TIMER_1_TINT12 6
413#define IRQ_TNETV107X_UART0 7
414#define IRQ_TNETV107X_TDM1_RXDMA 8
415#define IRQ_TNETV107X_MCDMA_INT0 9
416#define IRQ_TNETV107X_MCDMA_INT1 10
417#define IRQ_TNETV107X_TPCC 11
418#define IRQ_TNETV107X_TPCC_INT0 12
419#define IRQ_TNETV107X_TPCC_INT1 13
420#define IRQ_TNETV107X_TPCC_INT2 14
421#define IRQ_TNETV107X_TPCC_INT3 15
422#define IRQ_TNETV107X_TPTC0 16
423#define IRQ_TNETV107X_TPTC1 17
424#define IRQ_TNETV107X_TIMER_0_TINT34 18
425#define IRQ_TNETV107X_ETHSS 19
426#define IRQ_TNETV107X_TIMER_1_TINT34 20
427#define IRQ_TNETV107X_DSP2ARM_INT0 21
428#define IRQ_TNETV107X_DSP2ARM_INT1 22
429#define IRQ_TNETV107X_ARM_NPMUIRQ 23
430#define IRQ_TNETV107X_USB1 24
431#define IRQ_TNETV107X_VLYNQ 25
432#define IRQ_TNETV107X_UART0_DMATX 26
433#define IRQ_TNETV107X_UART0_DMARX 27
434#define IRQ_TNETV107X_TDM1_TXMCSP 28
435#define IRQ_TNETV107X_SSP 29
436#define IRQ_TNETV107X_MCDMA_INT2 30
437#define IRQ_TNETV107X_MCDMA_INT3 31
438#define IRQ_TNETV107X_TDM_CODECIF_EOT 32
439#define IRQ_TNETV107X_IMCOP_SQR_ARM 33
440#define IRQ_TNETV107X_USB0 34
441#define IRQ_TNETV107X_USB_CDMA 35
442#define IRQ_TNETV107X_LCD 36
443#define IRQ_TNETV107X_KEYPAD 37
444#define IRQ_TNETV107X_KEYPAD_FREE 38
445#define IRQ_TNETV107X_RNG 39
446#define IRQ_TNETV107X_PKA 40
447#define IRQ_TNETV107X_TDM0_TXDMA 41
448#define IRQ_TNETV107X_TDM0_RXDMA 42
449#define IRQ_TNETV107X_TDM0_TXMCSP 43
450#define IRQ_TNETV107X_TDM0_RXMCSP 44
451#define IRQ_TNETV107X_TDM1_RXMCSP 45
452#define IRQ_TNETV107X_SDIO1 46
453#define IRQ_TNETV107X_SDIO0 47
454#define IRQ_TNETV107X_TSC 48
455#define IRQ_TNETV107X_TS 49
456#define IRQ_TNETV107X_UART1 50
457#define IRQ_TNETV107X_MBX_LITE 51
458#define IRQ_TNETV107X_GPIO_INT00 52
459#define IRQ_TNETV107X_GPIO_INT01 53
460#define IRQ_TNETV107X_GPIO_INT02 54
461#define IRQ_TNETV107X_GPIO_INT03 55
462#define IRQ_TNETV107X_UART2 56
463#define IRQ_TNETV107X_UART2_DMATX 57
464#define IRQ_TNETV107X_UART2_DMARX 58
465#define IRQ_TNETV107X_IMCOP_IMX 59
466#define IRQ_TNETV107X_IMCOP_VLCD 60
467#define IRQ_TNETV107X_AES 61
468#define IRQ_TNETV107X_DES 62
469#define IRQ_TNETV107X_SHAMD5 63
470#define IRQ_TNETV107X_TPCC_ERR 68
471#define IRQ_TNETV107X_TPCC_PROT 69
472#define IRQ_TNETV107X_TPTC0_ERR 70
473#define IRQ_TNETV107X_TPTC1_ERR 71
474#define IRQ_TNETV107X_UART0_ERR 72
475#define IRQ_TNETV107X_UART1_ERR 73
476#define IRQ_TNETV107X_AEMIF_ERR 74
477#define IRQ_TNETV107X_DDR_ERR 75
478#define IRQ_TNETV107X_WDTARM_INT0 76
479#define IRQ_TNETV107X_MCDMA_ERR 77
480#define IRQ_TNETV107X_GPIO_ERR 78
481#define IRQ_TNETV107X_MPU_ADDR 79
482#define IRQ_TNETV107X_MPU_PROT 80
483#define IRQ_TNETV107X_IOPU_ADDR 81
484#define IRQ_TNETV107X_IOPU_PROT 82
485#define IRQ_TNETV107X_KEYPAD_ADDR_ERR 83
486#define IRQ_TNETV107X_WDT0_ADDR_ERR 84
487#define IRQ_TNETV107X_WDT1_ADDR_ERR 85
488#define IRQ_TNETV107X_CLKCTL_ADDR_ERR 86
489#define IRQ_TNETV107X_PLL_UNLOCK 87
490#define IRQ_TNETV107X_WDTDSP_INT0 88
491#define IRQ_TNETV107X_SEC_CTRL_VIOLATION 89
492#define IRQ_TNETV107X_KEY_MNG_VIOLATION 90
493#define IRQ_TNETV107X_PBIST_CPU 91
494#define IRQ_TNETV107X_WDTARM 92
495#define IRQ_TNETV107X_PSC 93
496#define IRQ_TNETV107X_MMC0 94
497#define IRQ_TNETV107X_MMC1 95
498
499#define TNETV107X_N_CP_INTC_IRQ 96
500
501/* da850 currently has the most gpio pins (144) */
502#define DAVINCI_N_GPIO 144
503/* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
504#define NR_IRQS (DA850_N_CP_INTC_IRQ + DAVINCI_N_GPIO)
505
506#endif /* __ASM_ARCH_IRQS_H */