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/arch/arm/include/asm/cacheflush.h

https://bitbucket.org/sammyz/iscream_thunderc-2.6.35-rebase
C++ Header | 475 lines | 254 code | 55 blank | 166 comment | 21 complexity | cc84d4d49cb79400c1a6bdd5883416c4 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1/*
  2 *  arch/arm/include/asm/cacheflush.h
  3 *
  4 *  Copyright (C) 1999-2002 Russell King
  5 *
  6 * This program is free software; you can redistribute it and/or modify
  7 * it under the terms of the GNU General Public License version 2 as
  8 * published by the Free Software Foundation.
  9 */
 10#ifndef _ASMARM_CACHEFLUSH_H
 11#define _ASMARM_CACHEFLUSH_H
 12
 13#include <linux/mm.h>
 14
 15#include <asm/glue.h>
 16#include <asm/shmparam.h>
 17#include <asm/cachetype.h>
 18#include <asm/outercache.h>
 19
 20#define CACHE_COLOUR(vaddr)	((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
 21
 22/*
 23 *	Cache Model
 24 *	===========
 25 */
 26#undef _CACHE
 27#undef MULTI_CACHE
 28
 29#if defined(CONFIG_CPU_CACHE_V3)
 30# ifdef _CACHE
 31#  define MULTI_CACHE 1
 32# else
 33#  define _CACHE v3
 34# endif
 35#endif
 36
 37#if defined(CONFIG_CPU_CACHE_V4)
 38# ifdef _CACHE
 39#  define MULTI_CACHE 1
 40# else
 41#  define _CACHE v4
 42# endif
 43#endif
 44
 45#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
 46    defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) || \
 47    defined(CONFIG_CPU_ARM1026)
 48# define MULTI_CACHE 1
 49#endif
 50
 51#if defined(CONFIG_CPU_FA526)
 52# ifdef _CACHE
 53#  define MULTI_CACHE 1
 54# else
 55#  define _CACHE fa
 56# endif
 57#endif
 58
 59#if defined(CONFIG_CPU_ARM926T)
 60# ifdef _CACHE
 61#  define MULTI_CACHE 1
 62# else
 63#  define _CACHE arm926
 64# endif
 65#endif
 66
 67#if defined(CONFIG_CPU_ARM940T)
 68# ifdef _CACHE
 69#  define MULTI_CACHE 1
 70# else
 71#  define _CACHE arm940
 72# endif
 73#endif
 74
 75#if defined(CONFIG_CPU_ARM946E)
 76# ifdef _CACHE
 77#  define MULTI_CACHE 1
 78# else
 79#  define _CACHE arm946
 80# endif
 81#endif
 82
 83#if defined(CONFIG_CPU_CACHE_V4WB)
 84# ifdef _CACHE
 85#  define MULTI_CACHE 1
 86# else
 87#  define _CACHE v4wb
 88# endif
 89#endif
 90
 91#if defined(CONFIG_CPU_XSCALE)
 92# ifdef _CACHE
 93#  define MULTI_CACHE 1
 94# else
 95#  define _CACHE xscale
 96# endif
 97#endif
 98
 99#if defined(CONFIG_CPU_XSC3)
100# ifdef _CACHE
101#  define MULTI_CACHE 1
102# else
103#  define _CACHE xsc3
104# endif
105#endif
106
107#if defined(CONFIG_CPU_MOHAWK)
108# ifdef _CACHE
109#  define MULTI_CACHE 1
110# else
111#  define _CACHE mohawk
112# endif
113#endif
114
115#if defined(CONFIG_CPU_FEROCEON)
116# define MULTI_CACHE 1
117#endif
118
119#if defined(CONFIG_CPU_V6)
120//# ifdef _CACHE
121#  define MULTI_CACHE 1
122//# else
123//#  define _CACHE v6
124//# endif
125#endif
126
127#if defined(CONFIG_CPU_V7)
128//# ifdef _CACHE
129#  define MULTI_CACHE 1
130//# else
131//#  define _CACHE v7
132//# endif
133#endif
134
135#if !defined(_CACHE) && !defined(MULTI_CACHE)
136#error Unknown cache maintainence model
137#endif
138
139/*
140 * This flag is used to indicate that the page pointed to by a pte
141 * is dirty and requires cleaning before returning it to the user.
142 */
143#define PG_dcache_dirty PG_arch_1
144
145/*
146 *	MM Cache Management
147 *	===================
148 *
149 *	The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
150 *	implement these methods.
151 *
152 *	Start addresses are inclusive and end addresses are exclusive;
153 *	start addresses should be rounded down, end addresses up.
154 *
155 *	See Documentation/cachetlb.txt for more information.
156 *	Please note that the implementation of these, and the required
157 *	effects are cache-type (VIVT/VIPT/PIPT) specific.
158 *
159 *	flush_kern_all()
160 *
161 *		Unconditionally clean and invalidate the entire cache.
162 *
163 *	flush_user_all()
164 *
165 *		Clean and invalidate all user space cache entries
166 *		before a change of page tables.
167 *
168 *	flush_user_range(start, end, flags)
169 *
170 *		Clean and invalidate a range of cache entries in the
171 *		specified address space before a change of page tables.
172 *		- start - user start address (inclusive, page aligned)
173 *		- end   - user end address   (exclusive, page aligned)
174 *		- flags - vma->vm_flags field
175 *
176 *	coherent_kern_range(start, end)
177 *
178 *		Ensure coherency between the Icache and the Dcache in the
179 *		region described by start, end.  If you have non-snooping
180 *		Harvard caches, you need to implement this function.
181 *		- start  - virtual start address
182 *		- end    - virtual end address
183 *
184 *	coherent_user_range(start, end)
185 *
186 *		Ensure coherency between the Icache and the Dcache in the
187 *		region described by start, end.  If you have non-snooping
188 *		Harvard caches, you need to implement this function.
189 *		- start  - virtual start address
190 *		- end    - virtual end address
191 *
192 *	flush_kern_dcache_area(kaddr, size)
193 *
194 *		Ensure that the data held in page is written back.
195 *		- kaddr  - page address
196 *		- size   - region size
197 *
198 *	DMA Cache Coherency
199 *	===================
200 *
201 *	dma_inv_range(start, end)
202 *
203 *		Invalidate (discard) the specified virtual address range.
204 *		May not write back any entries.  If 'start' or 'end'
205 *		are not cache line aligned, those lines must be written
206 *		back.
207 *		- start  - virtual start address
208 *		- end    - virtual end address
209 *
210 *	dma_clean_range(start, end)
211 *
212 *		Clean (write back) the specified virtual address range.
213 *		- start  - virtual start address
214 *		- end    - virtual end address
215 *
216 *	dma_flush_range(start, end)
217 *
218 *		Clean and invalidate the specified virtual address range.
219 *		- start  - virtual start address
220 *		- end    - virtual end address
221 */
222
223struct cpu_cache_fns {
224	void (*flush_kern_all)(void);
225	void (*flush_user_all)(void);
226	void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
227
228	void (*coherent_kern_range)(unsigned long, unsigned long);
229	void (*coherent_user_range)(unsigned long, unsigned long);
230	void (*flush_kern_dcache_area)(void *, size_t);
231
232	void (*dma_map_area)(const void *, size_t, int);
233	void (*dma_unmap_area)(const void *, size_t, int);
234
235	void (*dma_inv_range)(const void *, const void *);
236	void (*dma_clean_range)(const void *, const void *);
237	void (*dma_flush_range)(const void *, const void *);
238};
239
240/*
241 * Select the calling method
242 */
243#ifdef MULTI_CACHE
244
245extern struct cpu_cache_fns cpu_cache;
246
247#define __cpuc_flush_kern_all		cpu_cache.flush_kern_all
248#define __cpuc_flush_user_all		cpu_cache.flush_user_all
249#define __cpuc_flush_user_range		cpu_cache.flush_user_range
250#define __cpuc_coherent_kern_range	cpu_cache.coherent_kern_range
251#define __cpuc_coherent_user_range	cpu_cache.coherent_user_range
252#define __cpuc_flush_dcache_area	cpu_cache.flush_kern_dcache_area
253
254/*
255 * These are private to the dma-mapping API.  Do not use directly.
256 * Their sole purpose is to ensure that data held in the cache
257 * is visible to DMA, or data written by DMA to system memory is
258 * visible to the CPU.
259 */
260#define dmac_map_area			cpu_cache.dma_map_area
261#define dmac_unmap_area		cpu_cache.dma_unmap_area
262#define dmac_inv_range			cpu_cache.dma_inv_range
263#define dmac_clean_range		cpu_cache.dma_clean_range
264#define dmac_flush_range		cpu_cache.dma_flush_range
265
266#else
267
268#define __cpuc_flush_kern_all		__glue(_CACHE,_flush_kern_cache_all)
269#define __cpuc_flush_user_all		__glue(_CACHE,_flush_user_cache_all)
270#define __cpuc_flush_user_range		__glue(_CACHE,_flush_user_cache_range)
271#define __cpuc_coherent_kern_range	__glue(_CACHE,_coherent_kern_range)
272#define __cpuc_coherent_user_range	__glue(_CACHE,_coherent_user_range)
273#define __cpuc_flush_dcache_area	__glue(_CACHE,_flush_kern_dcache_area)
274
275extern void __cpuc_flush_kern_all(void);
276extern void __cpuc_flush_user_all(void);
277extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
278extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
279extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
280extern void __cpuc_flush_dcache_area(void *, size_t);
281
282/*
283 * These are private to the dma-mapping API.  Do not use directly.
284 * Their sole purpose is to ensure that data held in the cache
285 * is visible to DMA, or data written by DMA to system memory is
286 * visible to the CPU.
287 */
288#define dmac_map_area			__glue(_CACHE,_dma_map_area)
289#define dmac_unmap_area		__glue(_CACHE,_dma_unmap_area)
290#define dmac_inv_range			__glue(_CACHE,_dma_inv_range)
291#define dmac_clean_range		__glue(_CACHE,_dma_clean_range)
292#define dmac_flush_range		__glue(_CACHE,_dma_flush_range)
293
294extern void dmac_map_area(const void *, size_t, int);
295extern void dmac_unmap_area(const void *, size_t, int);
296extern void dmac_inv_range(const void *, const void *);
297extern void dmac_clean_range(const void *, const void *);
298extern void dmac_flush_range(const void *, const void *);
299
300#endif
301
302/*
303 * Copy user data from/to a page which is mapped into a different
304 * processes address space.  Really, we want to allow our "user
305 * space" model to handle this.
306 */
307extern void copy_to_user_page(struct vm_area_struct *, struct page *,
308	unsigned long, void *, const void *, unsigned long);
309#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
310	do {							\
311		memcpy(dst, src, len);				\
312	} while (0)
313
314/*
315 * Convert calls to our calling convention.
316 */
317#define flush_cache_all()		__cpuc_flush_kern_all()
318
319static inline void vivt_flush_cache_mm(struct mm_struct *mm)
320{
321	if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
322		__cpuc_flush_user_all();
323}
324
325static inline void
326vivt_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
327{
328	if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)))
329		__cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
330					vma->vm_flags);
331}
332
333static inline void
334vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
335{
336	if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
337		unsigned long addr = user_addr & PAGE_MASK;
338		__cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
339	}
340}
341
342#ifndef CONFIG_CPU_CACHE_VIPT
343#define flush_cache_mm(mm) \
344		vivt_flush_cache_mm(mm)
345#define flush_cache_range(vma,start,end) \
346		vivt_flush_cache_range(vma,start,end)
347#define flush_cache_page(vma,addr,pfn) \
348		vivt_flush_cache_page(vma,addr,pfn)
349#else
350extern void flush_cache_mm(struct mm_struct *mm);
351extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
352extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
353#endif
354
355#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
356
357/*
358 * flush_cache_user_range is used when we want to ensure that the
359 * Harvard caches are synchronised for the user space address range.
360 * This is used for the ARM private sys_cacheflush system call.
361 */
362#define flush_cache_user_range(start,end) \
363	__cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
364
365/*
366 * Perform necessary cache operations to ensure that data previously
367 * stored within this range of addresses can be executed by the CPU.
368 */
369#define flush_icache_range(s,e)		__cpuc_coherent_kern_range(s,e)
370
371/*
372 * Perform necessary cache operations to ensure that the TLB will
373 * see data written in the specified area.
374 */
375#define clean_dcache_area(start,size)	cpu_dcache_clean_area(start, size)
376
377/*
378 * flush_dcache_page is used when the kernel has written to the page
379 * cache page at virtual address page->virtual.
380 *
381 * If this page isn't mapped (ie, page_mapping == NULL), or it might
382 * have userspace mappings, then we _must_ always clean + invalidate
383 * the dcache entries associated with the kernel mapping.
384 *
385 * Otherwise we can defer the operation, and clean the cache when we are
386 * about to change to user space.  This is the same method as used on SPARC64.
387 * See update_mmu_cache for the user space part.
388 */
389#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
390extern void flush_dcache_page(struct page *);
391
392static inline void __flush_icache_all(void)
393{
394#ifdef CONFIG_ARM_ERRATA_411920
395	extern void v6_icache_inval_all(void);
396	v6_icache_inval_all();
397#elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7
398	asm("mcr	p15, 0, %0, c7, c1, 0	@ invalidate I-cache inner shareable\n"
399	    :
400	    : "r" (0));
401#else
402	asm("mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache\n"
403	    :
404	    : "r" (0));
405#endif
406}
407static inline void flush_kernel_vmap_range(void *addr, int size)
408{
409	if ((cache_is_vivt() || cache_is_vipt_aliasing()))
410	  __cpuc_flush_dcache_area(addr, (size_t)size);
411}
412static inline void invalidate_kernel_vmap_range(void *addr, int size)
413{
414	if ((cache_is_vivt() || cache_is_vipt_aliasing()))
415	  __cpuc_flush_dcache_area(addr, (size_t)size);
416}
417
418#define ARCH_HAS_FLUSH_ANON_PAGE
419static inline void flush_anon_page(struct vm_area_struct *vma,
420			 struct page *page, unsigned long vmaddr)
421{
422	extern void __flush_anon_page(struct vm_area_struct *vma,
423				struct page *, unsigned long);
424	if (PageAnon(page))
425		__flush_anon_page(vma, page, vmaddr);
426}
427
428#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
429static inline void flush_kernel_dcache_page(struct page *page)
430{
431	/* highmem pages are always flushed upon kunmap already */
432	if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page))
433		__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
434}
435
436#define flush_dcache_mmap_lock(mapping) \
437	spin_lock_irq(&(mapping)->tree_lock)
438#define flush_dcache_mmap_unlock(mapping) \
439	spin_unlock_irq(&(mapping)->tree_lock)
440
441#define flush_icache_user_range(vma,page,addr,len) \
442	flush_dcache_page(page)
443
444/*
445 * We don't appear to need to do anything here.  In fact, if we did, we'd
446 * duplicate cache flushing elsewhere performed by flush_dcache_page().
447 */
448#define flush_icache_page(vma,page)	do { } while (0)
449
450/*
451 * flush_cache_vmap() is used when creating mappings (eg, via vmap,
452 * vmalloc, ioremap etc) in kernel space for pages.  On non-VIPT
453 * caches, since the direct-mappings of these pages may contain cached
454 * data, we need to do a full cache flush to ensure that writebacks
455 * don't corrupt data placed into these pages via the new mappings.
456 */
457static inline void flush_cache_vmap(unsigned long start, unsigned long end)
458{
459	if (!cache_is_vipt_nonaliasing())
460		flush_cache_all();
461	else
462		/*
463		 * set_pte_at() called from vmap_pte_range() does not
464		 * have a DSB after cleaning the cache line.
465		 */
466		dsb();
467}
468
469static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
470{
471	if (!cache_is_vipt_nonaliasing())
472		flush_cache_all();
473}
474
475#endif