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/arch/alpha/include/asm/core_irongate.h

https://bitbucket.org/sammyz/iscream_thunderc-2.6.35-rebase
C++ Header | 232 lines | 132 code | 49 blank | 51 comment | 1 complexity | 2d1447f155f517e71f96dd04923f0756 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. #ifndef __ALPHA_IRONGATE__H__
  2. #define __ALPHA_IRONGATE__H__
  3. #include <linux/types.h>
  4. #include <asm/compiler.h>
  5. /*
  6. * IRONGATE is the internal name for the AMD-751 K7 core logic chipset
  7. * which provides memory controller and PCI access for NAUTILUS-based
  8. * EV6 (21264) systems.
  9. *
  10. * This file is based on:
  11. *
  12. * IronGate management library, (c) 1999 Alpha Processor, Inc.
  13. * Copyright (C) 1999 Alpha Processor, Inc.,
  14. * (David Daniel, Stig Telfer, Soohoon Lee)
  15. */
  16. /*
  17. * The 21264 supports, and internally recognizes, a 44-bit physical
  18. * address space that is divided equally between memory address space
  19. * and I/O address space. Memory address space resides in the lower
  20. * half of the physical address space (PA[43]=0) and I/O address space
  21. * resides in the upper half of the physical address space (PA[43]=1).
  22. */
  23. /*
  24. * Irongate CSR map. Some of the CSRs are 8 or 16 bits, but all access
  25. * through the routines given is 32-bit.
  26. *
  27. * The first 0x40 bytes are standard as per the PCI spec.
  28. */
  29. typedef volatile __u32 igcsr32;
  30. typedef struct {
  31. igcsr32 dev_vendor; /* 0x00 - device ID, vendor ID */
  32. igcsr32 stat_cmd; /* 0x04 - status, command */
  33. igcsr32 class; /* 0x08 - class code, rev ID */
  34. igcsr32 latency; /* 0x0C - header type, PCI latency */
  35. igcsr32 bar0; /* 0x10 - BAR0 - AGP */
  36. igcsr32 bar1; /* 0x14 - BAR1 - GART */
  37. igcsr32 bar2; /* 0x18 - Power Management reg block */
  38. igcsr32 rsrvd0[6]; /* 0x1C-0x33 reserved */
  39. igcsr32 capptr; /* 0x34 - Capabilities pointer */
  40. igcsr32 rsrvd1[2]; /* 0x38-0x3F reserved */
  41. igcsr32 bacsr10; /* 0x40 - base address chip selects */
  42. igcsr32 bacsr32; /* 0x44 - base address chip selects */
  43. igcsr32 bacsr54_eccms761; /* 0x48 - 751: base addr. chip selects
  44. 761: ECC, mode/status */
  45. igcsr32 rsrvd2[1]; /* 0x4C-0x4F reserved */
  46. igcsr32 drammap; /* 0x50 - address mapping control */
  47. igcsr32 dramtm; /* 0x54 - timing, driver strength */
  48. igcsr32 dramms; /* 0x58 - DRAM mode/status */
  49. igcsr32 rsrvd3[1]; /* 0x5C-0x5F reserved */
  50. igcsr32 biu0; /* 0x60 - bus interface unit */
  51. igcsr32 biusip; /* 0x64 - Serial initialisation pkt */
  52. igcsr32 rsrvd4[2]; /* 0x68-0x6F reserved */
  53. igcsr32 mro; /* 0x70 - memory request optimiser */
  54. igcsr32 rsrvd5[3]; /* 0x74-0x7F reserved */
  55. igcsr32 whami; /* 0x80 - who am I */
  56. igcsr32 pciarb; /* 0x84 - PCI arbitration control */
  57. igcsr32 pcicfg; /* 0x88 - PCI config status */
  58. igcsr32 rsrvd6[4]; /* 0x8C-0x9B reserved */
  59. igcsr32 pci_mem; /* 0x9C - PCI top of memory,
  60. 761 only */
  61. /* AGP (bus 1) control registers */
  62. igcsr32 agpcap; /* 0xA0 - AGP Capability Identifier */
  63. igcsr32 agpstat; /* 0xA4 - AGP status register */
  64. igcsr32 agpcmd; /* 0xA8 - AGP control register */
  65. igcsr32 agpva; /* 0xAC - AGP Virtual Address Space */
  66. igcsr32 agpmode; /* 0xB0 - AGP/GART mode control */
  67. } Irongate0;
  68. typedef struct {
  69. igcsr32 dev_vendor; /* 0x00 - Device and Vendor IDs */
  70. igcsr32 stat_cmd; /* 0x04 - Status and Command regs */
  71. igcsr32 class; /* 0x08 - subclass, baseclass etc */
  72. igcsr32 htype; /* 0x0C - header type (at 0x0E) */
  73. igcsr32 rsrvd0[2]; /* 0x10-0x17 reserved */
  74. igcsr32 busnos; /* 0x18 - Primary, secondary bus nos */
  75. igcsr32 io_baselim_regs; /* 0x1C - IO base, IO lim, AGP status */
  76. igcsr32 mem_baselim; /* 0x20 - memory base, memory lim */
  77. igcsr32 pfmem_baselim; /* 0x24 - prefetchable base, lim */
  78. igcsr32 rsrvd1[2]; /* 0x28-0x2F reserved */
  79. igcsr32 io_baselim; /* 0x30 - IO base, IO limit */
  80. igcsr32 rsrvd2[2]; /* 0x34-0x3B - reserved */
  81. igcsr32 interrupt; /* 0x3C - interrupt, PCI bridge ctrl */
  82. } Irongate1;
  83. extern igcsr32 *IronECC;
  84. /*
  85. * Memory spaces:
  86. */
  87. /* Irongate is consistent with a subset of the Tsunami memory map */
  88. #ifdef USE_48_BIT_KSEG
  89. #define IRONGATE_BIAS 0x80000000000UL
  90. #else
  91. #define IRONGATE_BIAS 0x10000000000UL
  92. #endif
  93. #define IRONGATE_MEM (IDENT_ADDR | IRONGATE_BIAS | 0x000000000UL)
  94. #define IRONGATE_IACK_SC (IDENT_ADDR | IRONGATE_BIAS | 0x1F8000000UL)
  95. #define IRONGATE_IO (IDENT_ADDR | IRONGATE_BIAS | 0x1FC000000UL)
  96. #define IRONGATE_CONF (IDENT_ADDR | IRONGATE_BIAS | 0x1FE000000UL)
  97. /*
  98. * PCI Configuration space accesses are formed like so:
  99. *
  100. * 0x1FE << 24 | : 2 2 2 2 1 1 1 1 : 1 1 1 1 1 1 0 0 : 0 0 0 0 0 0 0 0 :
  101. * : 3 2 1 0 9 8 7 6 : 5 4 3 2 1 0 9 8 : 7 6 5 4 3 2 1 0 :
  102. * ---bus numer--- -device-- -fun- ---register----
  103. */
  104. #define IGCSR(dev,fun,reg) ( IRONGATE_CONF | \
  105. ((dev)<<11) | \
  106. ((fun)<<8) | \
  107. (reg) )
  108. #define IRONGATE0 ((Irongate0 *) IGCSR(0, 0, 0))
  109. #define IRONGATE1 ((Irongate1 *) IGCSR(1, 0, 0))
  110. /*
  111. * Data structure for handling IRONGATE machine checks:
  112. * This is the standard OSF logout frame
  113. */
  114. #define SCB_Q_SYSERR 0x620 /* OSF definitions */
  115. #define SCB_Q_PROCERR 0x630
  116. #define SCB_Q_SYSMCHK 0x660
  117. #define SCB_Q_PROCMCHK 0x670
  118. struct el_IRONGATE_sysdata_mcheck {
  119. __u32 FrameSize; /* Bytes, including this field */
  120. __u32 FrameFlags; /* <31> = Retry, <30> = Second Error */
  121. __u32 CpuOffset; /* Offset to CPU-specific into */
  122. __u32 SystemOffset; /* Offset to system-specific info */
  123. __u32 MCHK_Code;
  124. __u32 MCHK_Frame_Rev;
  125. __u64 I_STAT;
  126. __u64 DC_STAT;
  127. __u64 C_ADDR;
  128. __u64 DC1_SYNDROME;
  129. __u64 DC0_SYNDROME;
  130. __u64 C_STAT;
  131. __u64 C_STS;
  132. __u64 RESERVED0;
  133. __u64 EXC_ADDR;
  134. __u64 IER_CM;
  135. __u64 ISUM;
  136. __u64 MM_STAT;
  137. __u64 PAL_BASE;
  138. __u64 I_CTL;
  139. __u64 PCTX;
  140. };
  141. #ifdef __KERNEL__
  142. #ifndef __EXTERN_INLINE
  143. #define __EXTERN_INLINE extern inline
  144. #define __IO_EXTERN_INLINE
  145. #endif
  146. /*
  147. * I/O functions:
  148. *
  149. * IRONGATE (AMD-751) PCI/memory support chip for the EV6 (21264) and
  150. * K7 can only use linear accesses to get at PCI memory and I/O spaces.
  151. */
  152. /*
  153. * Memory functions. All accesses are done through linear space.
  154. */
  155. __EXTERN_INLINE void __iomem *irongate_ioportmap(unsigned long addr)
  156. {
  157. return (void __iomem *)(addr + IRONGATE_IO);
  158. }
  159. extern void __iomem *irongate_ioremap(unsigned long addr, unsigned long size);
  160. extern void irongate_iounmap(volatile void __iomem *addr);
  161. __EXTERN_INLINE int irongate_is_ioaddr(unsigned long addr)
  162. {
  163. return addr >= IRONGATE_MEM;
  164. }
  165. __EXTERN_INLINE int irongate_is_mmio(const volatile void __iomem *xaddr)
  166. {
  167. unsigned long addr = (unsigned long)xaddr;
  168. return addr < IRONGATE_IO || addr >= IRONGATE_CONF;
  169. }
  170. #undef __IO_PREFIX
  171. #define __IO_PREFIX irongate
  172. #define irongate_trivial_rw_bw 1
  173. #define irongate_trivial_rw_lq 1
  174. #define irongate_trivial_io_bw 1
  175. #define irongate_trivial_io_lq 1
  176. #define irongate_trivial_iounmap 0
  177. #include <asm/io_trivial.h>
  178. #ifdef __IO_EXTERN_INLINE
  179. #undef __EXTERN_INLINE
  180. #undef __IO_EXTERN_INLINE
  181. #endif
  182. #endif /* __KERNEL__ */
  183. #endif /* __ALPHA_IRONGATE__H__ */