/Documentation/powerpc/dts-bindings/fsl/msi-pic.txt

 1* Freescale MSI interrupt controller
 2
 3Required properties:
 4- compatible : compatible list, contains 2 entries,
 5  first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
 6  etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
 7  the parent type.
 8- reg : should contain the address and the length of the shared message
 9  interrupt register set.
10- msi-available-ranges: use <start count> style section to define which
11  msi interrupt can be used in the 256 msi interrupts. This property is
12  optional, without this, all the 256 MSI interrupts can be used.
13- interrupts : each one of the interrupts here is one entry per 32 MSIs,
14  and routed to the host interrupt controller. the interrupts should
15  be set as edge sensitive.
16- interrupt-parent: the phandle for the interrupt controller
17  that services interrupts for this device. for 83xx cpu, the interrupts
18  are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
19  to MPIC.
20
21Example:
22	msi@41600 {
23		compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
24		reg = <0x41600 0x80>;
25		msi-available-ranges = <0 0x100>;
26		interrupts = <
27			0xe0 0
28			0xe1 0
29			0xe2 0
30			0xe3 0
31			0xe4 0
32			0xe5 0
33			0xe6 0
34			0xe7 0>;
35		interrupt-parent = <&mpic>;
36	};