/include/linux/ssb/ssb_driver_gige.h

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t · C Header · 179 lines · 133 code · 28 blank · 18 comment · 7 complexity · 58697c34ab71c5ec1716d23a71becbb5 MD5 · raw file 

    

  1. #ifndef LINUX_SSB_DRIVER_GIGE_H_
    2. 

  2. #define LINUX_SSB_DRIVER_GIGE_H_
    3. 

  3. 

  4. #include <linux/ssb/ssb.h>
    5. 

  5. #include <linux/pci.h>
    6. 

  6. #include <linux/spinlock.h>
    7. 

  7. 

  8. 

  9. #ifdef CONFIG_SSB_DRIVER_GIGE
    10. 

  10. 

  11. 

  12. #define SSB_GIGE_PCIIO			0x0000 /* PCI I/O Registers (1024 bytes) */
    13. 

  13. #define SSB_GIGE_RESERVED		0x0400 /* Reserved (1024 bytes) */
    14. 

  14. #define SSB_GIGE_PCICFG			0x0800 /* PCI config space (256 bytes) */
    15. 

  15. #define SSB_GIGE_SHIM_FLUSHSTAT		0x0C00 /* PCI to OCP: Flush status control (32bit) */
    16. 

  16. #define SSB_GIGE_SHIM_FLUSHRDA		0x0C04 /* PCI to OCP: Flush read address (32bit) */
    17. 

  17. #define SSB_GIGE_SHIM_FLUSHTO		0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
    18. 

  18. #define SSB_GIGE_SHIM_BARRIER		0x0C0C /* PCI to OCP: Barrier register (32bit) */
    19. 

  19. #define SSB_GIGE_SHIM_MAOCPSI		0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
    20. 

  20. #define SSB_GIGE_SHIM_SIOCPMA		0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
    21. 

  21. 

  22. /* TM Status High flags */
    23. 

  23. #define SSB_GIGE_TMSHIGH_RGMII		0x00010000 /* Have an RGMII PHY-bus */
    24. 

  24. /* TM Status Low flags */
    25. 

  25. #define SSB_GIGE_TMSLOW_TXBYPASS	0x00080000 /* TX bypass (no delay) */
    26. 

  26. #define SSB_GIGE_TMSLOW_RXBYPASS	0x00100000 /* RX bypass (no delay) */
    27. 

  27. #define SSB_GIGE_TMSLOW_DLLEN		0x01000000 /* Enable DLL controls */
    28. 

  28. 

  29. /* Boardflags (low) */
    30. 

  30. #define SSB_GIGE_BFL_ROBOSWITCH		0x0010
    31. 

  31. 

  32. 

  33. #define SSB_GIGE_MEM_RES_NAME		"SSB Broadcom 47xx GigE memory"
    34. 

  34. #define SSB_GIGE_IO_RES_NAME		"SSB Broadcom 47xx GigE I/O"
    35. 

  35. 

  36. struct ssb_gige {
    37. 

  37. 	struct ssb_device *dev;
    38. 

  38. 

  39. 	spinlock_t lock;
    40. 

  40. 

  41. 	/* True, if the device has an RGMII bus.
    42. 

  42. 	 * False, if the device has a GMII bus. */
    43. 

  43. 	bool has_rgmii;
    44. 

  44. 

  45. 	/* The PCI controller device. */
    46. 

  46. 	struct pci_controller pci_controller;
    47. 

  47. 	struct pci_ops pci_ops;
    48. 

  48. 	struct resource mem_resource;
    49. 

  49. 	struct resource io_resource;
    50. 

  50. };
    51. 

  51. 

  52. /* Check whether a PCI device is a SSB Gigabit Ethernet core. */
    53. 

  53. extern bool pdev_is_ssb_gige_core(struct pci_dev *pdev);
    54. 

  54. 

  55. /* Convert a pci_dev pointer to a ssb_gige pointer. */
    56. 

  56. static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
    57. 

  57. {
    58. 

  58. 	if (!pdev_is_ssb_gige_core(pdev))
    59. 

  59. 		return NULL;
    60. 

  60. 	return container_of(pdev->bus->ops, struct ssb_gige, pci_ops);
    61. 

  61. }
    62. 

  62. 

  63. /* Returns whether the PHY is connected by an RGMII bus. */
    64. 

  64. static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
    65. 

  65. {
    66. 

  66. 	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
    67. 

  67. 	return (dev ? dev->has_rgmii : 0);
    68. 

  68. }
    69. 

  69. 

  70. /* Returns whether we have a Roboswitch. */
    71. 

  71. static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
    72. 

  72. {
    73. 

  73. 	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
    74. 

  74. 	if (dev)
    75. 

  75. 		return !!(dev->dev->bus->sprom.boardflags_lo &
    76. 

  76. 			  SSB_GIGE_BFL_ROBOSWITCH);
    77. 

  77. 	return 0;
    78. 

  78. }
    79. 

  79. 

  80. /* Returns whether we can only do one DMA at once. */
    81. 

  81. static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
    82. 

  82. {
    83. 

  83. 	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
    84. 

  84. 	if (dev)
    85. 

  85. 		return ((dev->dev->bus->chip_id == 0x4785) &&
    86. 

  86. 			(dev->dev->bus->chip_rev < 2));
    87. 

  87. 	return 0;
    88. 

  88. }
    89. 

  89. 

  90. /* Returns whether we must flush posted writes. */
    91. 

  91. static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
    92. 

  92. {
    93. 

  93. 	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
    94. 

  94. 	if (dev)
    95. 

  95. 		return (dev->dev->bus->chip_id == 0x4785);
    96. 

  96. 	return 0;
    97. 

  97. }
    98. 

  98. 

  99. #ifdef CONFIG_BCM47XX
    100. 

  100. #include <asm/mach-bcm47xx/nvram.h>
    101. 

  101. /* Get the device MAC address */
    102. 

  102. static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
    103. 

  103. {
    104. 

  104. 	char buf[20];
    105. 

  105. 	if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
    106. 

  106. 		return;
    107. 

  107. 	nvram_parse_macaddr(buf, macaddr);
    108. 

  108. }
    109. 

  109. #else
    110. 

  110. static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
    111. 

  111. {
    112. 

  112. }
    113. 

  113. #endif
    114. 

  114. 

  115. extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
    116. 

  116. 					  struct pci_dev *pdev);
    117. 

  117. extern int ssb_gige_map_irq(struct ssb_device *sdev,
    118. 

  118. 			    const struct pci_dev *pdev);
    119. 

  119. 

  120. /* The GigE driver is not a standalone module, because we don't have support
    121. 

  121.  * for unregistering the driver. So we could not unload the module anyway. */
    122. 

  122. extern int ssb_gige_init(void);
    123. 

  123. static inline void ssb_gige_exit(void)
    124. 

  124. {
    125. 

  125. 	/* Currently we can not unregister the GigE driver,
    126. 

  126. 	 * because we can not unregister the PCI bridge. */
    127. 

  127. 	BUG();
    128. 

  128. }
    129. 

  129. 

  130. 

  131. #else /* CONFIG_SSB_DRIVER_GIGE */
    132. 

  132. /* Gigabit Ethernet driver disabled */
    133. 

  133. 

  134. 

  135. static inline int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
    136. 

  136. 						 struct pci_dev *pdev)
    137. 

  137. {
    138. 

  138. 	return -ENOSYS;
    139. 

  139. }
    140. 

  140. static inline int ssb_gige_map_irq(struct ssb_device *sdev,
    141. 

  141. 				   const struct pci_dev *pdev)
    142. 

  142. {
    143. 

  143. 	return -ENOSYS;
    144. 

  144. }
    145. 

  145. static inline int ssb_gige_init(void)
    146. 

  146. {
    147. 

  147. 	return 0;
    148. 

  148. }
    149. 

  149. static inline void ssb_gige_exit(void)
    150. 

  150. {
    151. 

  151. }
    152. 

  152. 

  153. static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
    154. 

  154. {
    155. 

  155. 	return 0;
    156. 

  156. }
    157. 

  157. static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
    158. 

  158. {
    159. 

  159. 	return NULL;
    160. 

  160. }
    161. 

  161. static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
    162. 

  162. {
    163. 

  163. 	return 0;
    164. 

  164. }
    165. 

  165. static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
    166. 

  166. {
    167. 

  167. 	return 0;
    168. 

  168. }
    169. 

  169. static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
    170. 

  170. {
    171. 

  171. 	return 0;
    172. 

  172. }
    173. 

  173. static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
    174. 

  174. {
    175. 

  175. 	return 0;
    176. 

  176. }
    177. 

  177. 

  178. #endif /* CONFIG_SSB_DRIVER_GIGE */
    179. 

  179. #endif /* LINUX_SSB_DRIVER_GIGE_H_ */
    180.