/include/linux/mfd/tps65910.h
C Header | 879 lines | 639 code | 138 blank | 102 comment | 0 complexity | af208e3727e368089cc271dc0a59b65d MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
1/* 2 * tps65910.h -- TI TPS6591x 3 * 4 * Copyright 2010-2011 Texas Instruments Inc. 5 * 6 * Author: Graeme Gregory <gg@slimlogic.co.uk> 7 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk> 8 * Author: Arnaud Deconinck <a-deconinck@ti.com> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 */ 16 17#ifndef __LINUX_MFD_TPS65910_H 18#define __LINUX_MFD_TPS65910_H 19 20#include <linux/gpio.h> 21#include <linux/regmap.h> 22 23/* TPS chip id list */ 24#define TPS65910 0 25#define TPS65911 1 26 27/* TPS regulator type list */ 28#define REGULATOR_LDO 0 29#define REGULATOR_DCDC 1 30 31/* 32 * List of registers for component TPS65910 33 * 34 */ 35 36#define TPS65910_SECONDS 0x0 37#define TPS65910_MINUTES 0x1 38#define TPS65910_HOURS 0x2 39#define TPS65910_DAYS 0x3 40#define TPS65910_MONTHS 0x4 41#define TPS65910_YEARS 0x5 42#define TPS65910_WEEKS 0x6 43#define TPS65910_ALARM_SECONDS 0x8 44#define TPS65910_ALARM_MINUTES 0x9 45#define TPS65910_ALARM_HOURS 0xA 46#define TPS65910_ALARM_DAYS 0xB 47#define TPS65910_ALARM_MONTHS 0xC 48#define TPS65910_ALARM_YEARS 0xD 49#define TPS65910_RTC_CTRL 0x10 50#define TPS65910_RTC_STATUS 0x11 51#define TPS65910_RTC_INTERRUPTS 0x12 52#define TPS65910_RTC_COMP_LSB 0x13 53#define TPS65910_RTC_COMP_MSB 0x14 54#define TPS65910_RTC_RES_PROG 0x15 55#define TPS65910_RTC_RESET_STATUS 0x16 56#define TPS65910_BCK1 0x17 57#define TPS65910_BCK2 0x18 58#define TPS65910_BCK3 0x19 59#define TPS65910_BCK4 0x1A 60#define TPS65910_BCK5 0x1B 61#define TPS65910_PUADEN 0x1C 62#define TPS65910_REF 0x1D 63#define TPS65910_VRTC 0x1E 64#define TPS65910_VIO 0x20 65#define TPS65910_VDD1 0x21 66#define TPS65910_VDD1_OP 0x22 67#define TPS65910_VDD1_SR 0x23 68#define TPS65910_VDD2 0x24 69#define TPS65910_VDD2_OP 0x25 70#define TPS65910_VDD2_SR 0x26 71#define TPS65910_VDD3 0x27 72#define TPS65910_VDIG1 0x30 73#define TPS65910_VDIG2 0x31 74#define TPS65910_VAUX1 0x32 75#define TPS65910_VAUX2 0x33 76#define TPS65910_VAUX33 0x34 77#define TPS65910_VMMC 0x35 78#define TPS65910_VPLL 0x36 79#define TPS65910_VDAC 0x37 80#define TPS65910_THERM 0x38 81#define TPS65910_BBCH 0x39 82#define TPS65910_DCDCCTRL 0x3E 83#define TPS65910_DEVCTRL 0x3F 84#define TPS65910_DEVCTRL2 0x40 85#define TPS65910_SLEEP_KEEP_LDO_ON 0x41 86#define TPS65910_SLEEP_KEEP_RES_ON 0x42 87#define TPS65910_SLEEP_SET_LDO_OFF 0x43 88#define TPS65910_SLEEP_SET_RES_OFF 0x44 89#define TPS65910_EN1_LDO_ASS 0x45 90#define TPS65910_EN1_SMPS_ASS 0x46 91#define TPS65910_EN2_LDO_ASS 0x47 92#define TPS65910_EN2_SMPS_ASS 0x48 93#define TPS65910_EN3_LDO_ASS 0x49 94#define TPS65910_SPARE 0x4A 95#define TPS65910_INT_STS 0x50 96#define TPS65910_INT_MSK 0x51 97#define TPS65910_INT_STS2 0x52 98#define TPS65910_INT_MSK2 0x53 99#define TPS65910_INT_STS3 0x54 100#define TPS65910_INT_MSK3 0x55 101#define TPS65910_GPIO0 0x60 102#define TPS65910_GPIO1 0x61 103#define TPS65910_GPIO2 0x62 104#define TPS65910_GPIO3 0x63 105#define TPS65910_GPIO4 0x64 106#define TPS65910_GPIO5 0x65 107#define TPS65910_GPIO6 0x66 108#define TPS65910_GPIO7 0x67 109#define TPS65910_GPIO8 0x68 110#define TPS65910_JTAGVERNUM 0x80 111#define TPS65910_MAX_REGISTER 0x80 112 113/* 114 * List of registers specific to TPS65911 115 */ 116#define TPS65911_VDDCTRL 0x27 117#define TPS65911_VDDCTRL_OP 0x28 118#define TPS65911_VDDCTRL_SR 0x29 119#define TPS65911_LDO1 0x30 120#define TPS65911_LDO2 0x31 121#define TPS65911_LDO5 0x32 122#define TPS65911_LDO8 0x33 123#define TPS65911_LDO7 0x34 124#define TPS65911_LDO6 0x35 125#define TPS65911_LDO4 0x36 126#define TPS65911_LDO3 0x37 127#define TPS65911_VMBCH 0x6A 128#define TPS65911_VMBCH2 0x6B 129 130/* 131 * List of register bitfields for component TPS65910 132 * 133 */ 134 135 136/*Register BCK1 (0x80) register.RegisterDescription */ 137#define BCK1_BCKUP_MASK 0xFF 138#define BCK1_BCKUP_SHIFT 0 139 140 141/*Register BCK2 (0x80) register.RegisterDescription */ 142#define BCK2_BCKUP_MASK 0xFF 143#define BCK2_BCKUP_SHIFT 0 144 145 146/*Register BCK3 (0x80) register.RegisterDescription */ 147#define BCK3_BCKUP_MASK 0xFF 148#define BCK3_BCKUP_SHIFT 0 149 150 151/*Register BCK4 (0x80) register.RegisterDescription */ 152#define BCK4_BCKUP_MASK 0xFF 153#define BCK4_BCKUP_SHIFT 0 154 155 156/*Register BCK5 (0x80) register.RegisterDescription */ 157#define BCK5_BCKUP_MASK 0xFF 158#define BCK5_BCKUP_SHIFT 0 159 160 161/*Register PUADEN (0x80) register.RegisterDescription */ 162#define PUADEN_EN3P_MASK 0x80 163#define PUADEN_EN3P_SHIFT 7 164#define PUADEN_I2CCTLP_MASK 0x40 165#define PUADEN_I2CCTLP_SHIFT 6 166#define PUADEN_I2CSRP_MASK 0x20 167#define PUADEN_I2CSRP_SHIFT 5 168#define PUADEN_PWRONP_MASK 0x10 169#define PUADEN_PWRONP_SHIFT 4 170#define PUADEN_SLEEPP_MASK 0x08 171#define PUADEN_SLEEPP_SHIFT 3 172#define PUADEN_PWRHOLDP_MASK 0x04 173#define PUADEN_PWRHOLDP_SHIFT 2 174#define PUADEN_BOOT1P_MASK 0x02 175#define PUADEN_BOOT1P_SHIFT 1 176#define PUADEN_BOOT0P_MASK 0x01 177#define PUADEN_BOOT0P_SHIFT 0 178 179 180/*Register REF (0x80) register.RegisterDescription */ 181#define REF_VMBCH_SEL_MASK 0x0C 182#define REF_VMBCH_SEL_SHIFT 2 183#define REF_ST_MASK 0x03 184#define REF_ST_SHIFT 0 185 186 187/*Register VRTC (0x80) register.RegisterDescription */ 188#define VRTC_VRTC_OFFMASK_MASK 0x08 189#define VRTC_VRTC_OFFMASK_SHIFT 3 190#define VRTC_ST_MASK 0x03 191#define VRTC_ST_SHIFT 0 192 193 194/*Register VIO (0x80) register.RegisterDescription */ 195#define VIO_ILMAX_MASK 0xC0 196#define VIO_ILMAX_SHIFT 6 197#define VIO_SEL_MASK 0x0C 198#define VIO_SEL_SHIFT 2 199#define VIO_ST_MASK 0x03 200#define VIO_ST_SHIFT 0 201 202 203/*Register VDD1 (0x80) register.RegisterDescription */ 204#define VDD1_VGAIN_SEL_MASK 0xC0 205#define VDD1_VGAIN_SEL_SHIFT 6 206#define VDD1_ILMAX_MASK 0x20 207#define VDD1_ILMAX_SHIFT 5 208#define VDD1_TSTEP_MASK 0x1C 209#define VDD1_TSTEP_SHIFT 2 210#define VDD1_ST_MASK 0x03 211#define VDD1_ST_SHIFT 0 212 213 214/*Register VDD1_OP (0x80) register.RegisterDescription */ 215#define VDD1_OP_CMD_MASK 0x80 216#define VDD1_OP_CMD_SHIFT 7 217#define VDD1_OP_SEL_MASK 0x7F 218#define VDD1_OP_SEL_SHIFT 0 219 220 221/*Register VDD1_SR (0x80) register.RegisterDescription */ 222#define VDD1_SR_SEL_MASK 0x7F 223#define VDD1_SR_SEL_SHIFT 0 224 225 226/*Register VDD2 (0x80) register.RegisterDescription */ 227#define VDD2_VGAIN_SEL_MASK 0xC0 228#define VDD2_VGAIN_SEL_SHIFT 6 229#define VDD2_ILMAX_MASK 0x20 230#define VDD2_ILMAX_SHIFT 5 231#define VDD2_TSTEP_MASK 0x1C 232#define VDD2_TSTEP_SHIFT 2 233#define VDD2_ST_MASK 0x03 234#define VDD2_ST_SHIFT 0 235 236 237/*Register VDD2_OP (0x80) register.RegisterDescription */ 238#define VDD2_OP_CMD_MASK 0x80 239#define VDD2_OP_CMD_SHIFT 7 240#define VDD2_OP_SEL_MASK 0x7F 241#define VDD2_OP_SEL_SHIFT 0 242 243/*Register VDD2_SR (0x80) register.RegisterDescription */ 244#define VDD2_SR_SEL_MASK 0x7F 245#define VDD2_SR_SEL_SHIFT 0 246 247 248/*Registers VDD1, VDD2 voltage values definitions */ 249#define VDD1_2_NUM_VOLT_FINE 73 250#define VDD1_2_NUM_VOLT_COARSE 3 251#define VDD1_2_MIN_VOLT 6000 252#define VDD1_2_OFFSET 125 253 254 255/*Register VDD3 (0x80) register.RegisterDescription */ 256#define VDD3_CKINEN_MASK 0x04 257#define VDD3_CKINEN_SHIFT 2 258#define VDD3_ST_MASK 0x03 259#define VDD3_ST_SHIFT 0 260#define VDDCTRL_MIN_VOLT 6000 261#define VDDCTRL_OFFSET 125 262 263/*Registers VDIG (0x80) to VDAC register.RegisterDescription */ 264#define LDO_SEL_MASK 0x0C 265#define LDO_SEL_SHIFT 2 266#define LDO_ST_MASK 0x03 267#define LDO_ST_SHIFT 0 268#define LDO_ST_ON_BIT 0x01 269#define LDO_ST_MODE_BIT 0x02 270 271 272/* Registers LDO1 to LDO8 in tps65910 */ 273#define LDO1_SEL_MASK 0xFC 274#define LDO3_SEL_MASK 0x7C 275#define LDO_MIN_VOLT 1000 276#define LDO_MAX_VOLT 3300 277 278 279/*Register VDIG1 (0x80) register.RegisterDescription */ 280#define VDIG1_SEL_MASK 0x0C 281#define VDIG1_SEL_SHIFT 2 282#define VDIG1_ST_MASK 0x03 283#define VDIG1_ST_SHIFT 0 284 285 286/*Register VDIG2 (0x80) register.RegisterDescription */ 287#define VDIG2_SEL_MASK 0x0C 288#define VDIG2_SEL_SHIFT 2 289#define VDIG2_ST_MASK 0x03 290#define VDIG2_ST_SHIFT 0 291 292 293/*Register VAUX1 (0x80) register.RegisterDescription */ 294#define VAUX1_SEL_MASK 0x0C 295#define VAUX1_SEL_SHIFT 2 296#define VAUX1_ST_MASK 0x03 297#define VAUX1_ST_SHIFT 0 298 299 300/*Register VAUX2 (0x80) register.RegisterDescription */ 301#define VAUX2_SEL_MASK 0x0C 302#define VAUX2_SEL_SHIFT 2 303#define VAUX2_ST_MASK 0x03 304#define VAUX2_ST_SHIFT 0 305 306 307/*Register VAUX33 (0x80) register.RegisterDescription */ 308#define VAUX33_SEL_MASK 0x0C 309#define VAUX33_SEL_SHIFT 2 310#define VAUX33_ST_MASK 0x03 311#define VAUX33_ST_SHIFT 0 312 313 314/*Register VMMC (0x80) register.RegisterDescription */ 315#define VMMC_SEL_MASK 0x0C 316#define VMMC_SEL_SHIFT 2 317#define VMMC_ST_MASK 0x03 318#define VMMC_ST_SHIFT 0 319 320 321/*Register VPLL (0x80) register.RegisterDescription */ 322#define VPLL_SEL_MASK 0x0C 323#define VPLL_SEL_SHIFT 2 324#define VPLL_ST_MASK 0x03 325#define VPLL_ST_SHIFT 0 326 327 328/*Register VDAC (0x80) register.RegisterDescription */ 329#define VDAC_SEL_MASK 0x0C 330#define VDAC_SEL_SHIFT 2 331#define VDAC_ST_MASK 0x03 332#define VDAC_ST_SHIFT 0 333 334 335/*Register THERM (0x80) register.RegisterDescription */ 336#define THERM_THERM_HD_MASK 0x20 337#define THERM_THERM_HD_SHIFT 5 338#define THERM_THERM_TS_MASK 0x10 339#define THERM_THERM_TS_SHIFT 4 340#define THERM_THERM_HDSEL_MASK 0x0C 341#define THERM_THERM_HDSEL_SHIFT 2 342#define THERM_RSVD1_MASK 0x02 343#define THERM_RSVD1_SHIFT 1 344#define THERM_THERM_STATE_MASK 0x01 345#define THERM_THERM_STATE_SHIFT 0 346 347 348/*Register BBCH (0x80) register.RegisterDescription */ 349#define BBCH_BBSEL_MASK 0x06 350#define BBCH_BBSEL_SHIFT 1 351#define BBCH_BBCHEN_MASK 0x01 352#define BBCH_BBCHEN_SHIFT 0 353 354 355/*Register DCDCCTRL (0x80) register.RegisterDescription */ 356#define DCDCCTRL_VDD2_PSKIP_MASK 0x20 357#define DCDCCTRL_VDD2_PSKIP_SHIFT 5 358#define DCDCCTRL_VDD1_PSKIP_MASK 0x10 359#define DCDCCTRL_VDD1_PSKIP_SHIFT 4 360#define DCDCCTRL_VIO_PSKIP_MASK 0x08 361#define DCDCCTRL_VIO_PSKIP_SHIFT 3 362#define DCDCCTRL_DCDCCKEXT_MASK 0x04 363#define DCDCCTRL_DCDCCKEXT_SHIFT 2 364#define DCDCCTRL_DCDCCKSYNC_MASK 0x03 365#define DCDCCTRL_DCDCCKSYNC_SHIFT 0 366 367 368/*Register DEVCTRL (0x80) register.RegisterDescription */ 369#define DEVCTRL_RTC_PWDN_MASK 0x40 370#define DEVCTRL_RTC_PWDN_SHIFT 6 371#define DEVCTRL_CK32K_CTRL_MASK 0x20 372#define DEVCTRL_CK32K_CTRL_SHIFT 5 373#define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10 374#define DEVCTRL_SR_CTL_I2C_SEL_SHIFT 4 375#define DEVCTRL_DEV_OFF_RST_MASK 0x08 376#define DEVCTRL_DEV_OFF_RST_SHIFT 3 377#define DEVCTRL_DEV_ON_MASK 0x04 378#define DEVCTRL_DEV_ON_SHIFT 2 379#define DEVCTRL_DEV_SLP_MASK 0x02 380#define DEVCTRL_DEV_SLP_SHIFT 1 381#define DEVCTRL_DEV_OFF_MASK 0x01 382#define DEVCTRL_DEV_OFF_SHIFT 0 383 384 385/*Register DEVCTRL2 (0x80) register.RegisterDescription */ 386#define DEVCTRL2_TSLOT_LENGTH_MASK 0x30 387#define DEVCTRL2_TSLOT_LENGTH_SHIFT 4 388#define DEVCTRL2_SLEEPSIG_POL_MASK 0x08 389#define DEVCTRL2_SLEEPSIG_POL_SHIFT 3 390#define DEVCTRL2_PWON_LP_OFF_MASK 0x04 391#define DEVCTRL2_PWON_LP_OFF_SHIFT 2 392#define DEVCTRL2_PWON_LP_RST_MASK 0x02 393#define DEVCTRL2_PWON_LP_RST_SHIFT 1 394#define DEVCTRL2_IT_POL_MASK 0x01 395#define DEVCTRL2_IT_POL_SHIFT 0 396 397 398/*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */ 399#define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80 400#define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7 401#define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40 402#define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT 6 403#define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20 404#define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT 5 405#define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10 406#define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT 4 407#define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08 408#define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT 3 409#define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04 410#define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT 2 411#define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02 412#define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT 1 413#define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01 414#define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0 415 416 417/*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */ 418#define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80 419#define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7 420#define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40 421#define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT 6 422#define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20 423#define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT 5 424#define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10 425#define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT 4 426#define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08 427#define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT 3 428#define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04 429#define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT 2 430#define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02 431#define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT 1 432#define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01 433#define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0 434 435 436/*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */ 437#define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80 438#define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7 439#define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40 440#define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT 6 441#define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20 442#define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT 5 443#define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10 444#define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT 4 445#define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08 446#define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT 3 447#define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04 448#define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT 2 449#define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02 450#define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT 1 451#define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01 452#define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0 453 454 455/*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */ 456#define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80 457#define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7 458#define SLEEP_SET_RES_OFF_RSVD_MASK 0x60 459#define SLEEP_SET_RES_OFF_RSVD_SHIFT 5 460#define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10 461#define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT 4 462#define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08 463#define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT 3 464#define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04 465#define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT 2 466#define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02 467#define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT 1 468#define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01 469#define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0 470 471 472/*Register EN1_LDO_ASS (0x80) register.RegisterDescription */ 473#define EN1_LDO_ASS_VDAC_EN1_MASK 0x80 474#define EN1_LDO_ASS_VDAC_EN1_SHIFT 7 475#define EN1_LDO_ASS_VPLL_EN1_MASK 0x40 476#define EN1_LDO_ASS_VPLL_EN1_SHIFT 6 477#define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20 478#define EN1_LDO_ASS_VAUX33_EN1_SHIFT 5 479#define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10 480#define EN1_LDO_ASS_VAUX2_EN1_SHIFT 4 481#define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08 482#define EN1_LDO_ASS_VAUX1_EN1_SHIFT 3 483#define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04 484#define EN1_LDO_ASS_VDIG2_EN1_SHIFT 2 485#define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02 486#define EN1_LDO_ASS_VDIG1_EN1_SHIFT 1 487#define EN1_LDO_ASS_VMMC_EN1_MASK 0x01 488#define EN1_LDO_ASS_VMMC_EN1_SHIFT 0 489 490 491/*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */ 492#define EN1_SMPS_ASS_RSVD_MASK 0xE0 493#define EN1_SMPS_ASS_RSVD_SHIFT 5 494#define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10 495#define EN1_SMPS_ASS_SPARE_EN1_SHIFT 4 496#define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08 497#define EN1_SMPS_ASS_VDD3_EN1_SHIFT 3 498#define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04 499#define EN1_SMPS_ASS_VDD2_EN1_SHIFT 2 500#define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02 501#define EN1_SMPS_ASS_VDD1_EN1_SHIFT 1 502#define EN1_SMPS_ASS_VIO_EN1_MASK 0x01 503#define EN1_SMPS_ASS_VIO_EN1_SHIFT 0 504 505 506/*Register EN2_LDO_ASS (0x80) register.RegisterDescription */ 507#define EN2_LDO_ASS_VDAC_EN2_MASK 0x80 508#define EN2_LDO_ASS_VDAC_EN2_SHIFT 7 509#define EN2_LDO_ASS_VPLL_EN2_MASK 0x40 510#define EN2_LDO_ASS_VPLL_EN2_SHIFT 6 511#define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20 512#define EN2_LDO_ASS_VAUX33_EN2_SHIFT 5 513#define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10 514#define EN2_LDO_ASS_VAUX2_EN2_SHIFT 4 515#define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08 516#define EN2_LDO_ASS_VAUX1_EN2_SHIFT 3 517#define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04 518#define EN2_LDO_ASS_VDIG2_EN2_SHIFT 2 519#define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02 520#define EN2_LDO_ASS_VDIG1_EN2_SHIFT 1 521#define EN2_LDO_ASS_VMMC_EN2_MASK 0x01 522#define EN2_LDO_ASS_VMMC_EN2_SHIFT 0 523 524 525/*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */ 526#define EN2_SMPS_ASS_RSVD_MASK 0xE0 527#define EN2_SMPS_ASS_RSVD_SHIFT 5 528#define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10 529#define EN2_SMPS_ASS_SPARE_EN2_SHIFT 4 530#define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08 531#define EN2_SMPS_ASS_VDD3_EN2_SHIFT 3 532#define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04 533#define EN2_SMPS_ASS_VDD2_EN2_SHIFT 2 534#define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02 535#define EN2_SMPS_ASS_VDD1_EN2_SHIFT 1 536#define EN2_SMPS_ASS_VIO_EN2_MASK 0x01 537#define EN2_SMPS_ASS_VIO_EN2_SHIFT 0 538 539 540/*Register EN3_LDO_ASS (0x80) register.RegisterDescription */ 541#define EN3_LDO_ASS_VDAC_EN3_MASK 0x80 542#define EN3_LDO_ASS_VDAC_EN3_SHIFT 7 543#define EN3_LDO_ASS_VPLL_EN3_MASK 0x40 544#define EN3_LDO_ASS_VPLL_EN3_SHIFT 6 545#define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20 546#define EN3_LDO_ASS_VAUX33_EN3_SHIFT 5 547#define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10 548#define EN3_LDO_ASS_VAUX2_EN3_SHIFT 4 549#define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08 550#define EN3_LDO_ASS_VAUX1_EN3_SHIFT 3 551#define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04 552#define EN3_LDO_ASS_VDIG2_EN3_SHIFT 2 553#define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02 554#define EN3_LDO_ASS_VDIG1_EN3_SHIFT 1 555#define EN3_LDO_ASS_VMMC_EN3_MASK 0x01 556#define EN3_LDO_ASS_VMMC_EN3_SHIFT 0 557 558 559/*Register SPARE (0x80) register.RegisterDescription */ 560#define SPARE_SPARE_MASK 0xFF 561#define SPARE_SPARE_SHIFT 0 562 563 564/*Register INT_STS (0x80) register.RegisterDescription */ 565#define INT_STS_RTC_PERIOD_IT_MASK 0x80 566#define INT_STS_RTC_PERIOD_IT_SHIFT 7 567#define INT_STS_RTC_ALARM_IT_MASK 0x40 568#define INT_STS_RTC_ALARM_IT_SHIFT 6 569#define INT_STS_HOTDIE_IT_MASK 0x20 570#define INT_STS_HOTDIE_IT_SHIFT 5 571#define INT_STS_PWRHOLD_IT_MASK 0x10 572#define INT_STS_PWRHOLD_IT_SHIFT 4 573#define INT_STS_PWRON_LP_IT_MASK 0x08 574#define INT_STS_PWRON_LP_IT_SHIFT 3 575#define INT_STS_PWRON_IT_MASK 0x04 576#define INT_STS_PWRON_IT_SHIFT 2 577#define INT_STS_VMBHI_IT_MASK 0x02 578#define INT_STS_VMBHI_IT_SHIFT 1 579#define INT_STS_VMBDCH_IT_MASK 0x01 580#define INT_STS_VMBDCH_IT_SHIFT 0 581 582 583/*Register INT_MSK (0x80) register.RegisterDescription */ 584#define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80 585#define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7 586#define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40 587#define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6 588#define INT_MSK_HOTDIE_IT_MSK_MASK 0x20 589#define INT_MSK_HOTDIE_IT_MSK_SHIFT 5 590#define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10 591#define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4 592#define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08 593#define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3 594#define INT_MSK_PWRON_IT_MSK_MASK 0x04 595#define INT_MSK_PWRON_IT_MSK_SHIFT 2 596#define INT_MSK_VMBHI_IT_MSK_MASK 0x02 597#define INT_MSK_VMBHI_IT_MSK_SHIFT 1 598#define INT_MSK_VMBDCH_IT_MSK_MASK 0x01 599#define INT_MSK_VMBDCH_IT_MSK_SHIFT 0 600 601 602/*Register INT_STS2 (0x80) register.RegisterDescription */ 603#define INT_STS2_GPIO3_F_IT_MASK 0x80 604#define INT_STS2_GPIO3_F_IT_SHIFT 7 605#define INT_STS2_GPIO3_R_IT_MASK 0x40 606#define INT_STS2_GPIO3_R_IT_SHIFT 6 607#define INT_STS2_GPIO2_F_IT_MASK 0x20 608#define INT_STS2_GPIO2_F_IT_SHIFT 5 609#define INT_STS2_GPIO2_R_IT_MASK 0x10 610#define INT_STS2_GPIO2_R_IT_SHIFT 4 611#define INT_STS2_GPIO1_F_IT_MASK 0x08 612#define INT_STS2_GPIO1_F_IT_SHIFT 3 613#define INT_STS2_GPIO1_R_IT_MASK 0x04 614#define INT_STS2_GPIO1_R_IT_SHIFT 2 615#define INT_STS2_GPIO0_F_IT_MASK 0x02 616#define INT_STS2_GPIO0_F_IT_SHIFT 1 617#define INT_STS2_GPIO0_R_IT_MASK 0x01 618#define INT_STS2_GPIO0_R_IT_SHIFT 0 619 620 621/*Register INT_MSK2 (0x80) register.RegisterDescription */ 622#define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80 623#define INT_MSK2_GPIO3_F_IT_MSK_SHIFT 7 624#define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40 625#define INT_MSK2_GPIO3_R_IT_MSK_SHIFT 6 626#define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20 627#define INT_MSK2_GPIO2_F_IT_MSK_SHIFT 5 628#define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10 629#define INT_MSK2_GPIO2_R_IT_MSK_SHIFT 4 630#define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08 631#define INT_MSK2_GPIO1_F_IT_MSK_SHIFT 3 632#define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04 633#define INT_MSK2_GPIO1_R_IT_MSK_SHIFT 2 634#define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02 635#define INT_MSK2_GPIO0_F_IT_MSK_SHIFT 1 636#define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01 637#define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0 638 639 640/*Register INT_STS3 (0x80) register.RegisterDescription */ 641#define INT_STS3_GPIO5_F_IT_MASK 0x08 642#define INT_STS3_GPIO5_F_IT_SHIFT 3 643#define INT_STS3_GPIO5_R_IT_MASK 0x04 644#define INT_STS3_GPIO5_R_IT_SHIFT 2 645#define INT_STS3_GPIO4_F_IT_MASK 0x02 646#define INT_STS3_GPIO4_F_IT_SHIFT 1 647#define INT_STS3_GPIO4_R_IT_MASK 0x01 648#define INT_STS3_GPIO4_R_IT_SHIFT 0 649 650 651/*Register INT_MSK3 (0x80) register.RegisterDescription */ 652#define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08 653#define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3 654#define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04 655#define INT_MSK3_GPIO5_R_IT_MSK_SHIFT 2 656#define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02 657#define INT_MSK3_GPIO4_F_IT_MSK_SHIFT 1 658#define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01 659#define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0 660 661 662/*Register GPIO (0x80) register.RegisterDescription */ 663#define GPIO_SLEEP_MASK 0x80 664#define GPIO_SLEEP_SHIFT 7 665#define GPIO_DEB_MASK 0x10 666#define GPIO_DEB_SHIFT 4 667#define GPIO_PUEN_MASK 0x08 668#define GPIO_PUEN_SHIFT 3 669#define GPIO_CFG_MASK 0x04 670#define GPIO_CFG_SHIFT 2 671#define GPIO_STS_MASK 0x02 672#define GPIO_STS_SHIFT 1 673#define GPIO_SET_MASK 0x01 674#define GPIO_SET_SHIFT 0 675 676 677/*Register JTAGVERNUM (0x80) register.RegisterDescription */ 678#define JTAGVERNUM_VERNUM_MASK 0x0F 679#define JTAGVERNUM_VERNUM_SHIFT 0 680 681 682/* Register VDDCTRL (0x27) bit definitions */ 683#define VDDCTRL_ST_MASK 0x03 684#define VDDCTRL_ST_SHIFT 0 685 686 687/*Register VDDCTRL_OP (0x28) bit definitios */ 688#define VDDCTRL_OP_CMD_MASK 0x80 689#define VDDCTRL_OP_CMD_SHIFT 7 690#define VDDCTRL_OP_SEL_MASK 0x7F 691#define VDDCTRL_OP_SEL_SHIFT 0 692 693 694/*Register VDDCTRL_SR (0x29) bit definitions */ 695#define VDDCTRL_SR_SEL_MASK 0x7F 696#define VDDCTRL_SR_SEL_SHIFT 0 697 698 699/* IRQ Definitions */ 700#define TPS65910_IRQ_VBAT_VMBDCH 0 701#define TPS65910_IRQ_VBAT_VMHI 1 702#define TPS65910_IRQ_PWRON 2 703#define TPS65910_IRQ_PWRON_LP 3 704#define TPS65910_IRQ_PWRHOLD 4 705#define TPS65910_IRQ_HOTDIE 5 706#define TPS65910_IRQ_RTC_ALARM 6 707#define TPS65910_IRQ_RTC_PERIOD 7 708#define TPS65910_IRQ_GPIO_R 8 709#define TPS65910_IRQ_GPIO_F 9 710#define TPS65910_NUM_IRQ 10 711 712#define TPS65911_IRQ_VBAT_VMBDCH 0 713#define TPS65911_IRQ_VBAT_VMBDCH2L 1 714#define TPS65911_IRQ_VBAT_VMBDCH2H 2 715#define TPS65911_IRQ_VBAT_VMHI 3 716#define TPS65911_IRQ_PWRON 4 717#define TPS65911_IRQ_PWRON_LP 5 718#define TPS65911_IRQ_PWRHOLD_F 6 719#define TPS65911_IRQ_PWRHOLD_R 7 720#define TPS65911_IRQ_HOTDIE 8 721#define TPS65911_IRQ_RTC_ALARM 9 722#define TPS65911_IRQ_RTC_PERIOD 10 723#define TPS65911_IRQ_GPIO0_R 11 724#define TPS65911_IRQ_GPIO0_F 12 725#define TPS65911_IRQ_GPIO1_R 13 726#define TPS65911_IRQ_GPIO1_F 14 727#define TPS65911_IRQ_GPIO2_R 15 728#define TPS65911_IRQ_GPIO2_F 16 729#define TPS65911_IRQ_GPIO3_R 17 730#define TPS65911_IRQ_GPIO3_F 18 731#define TPS65911_IRQ_GPIO4_R 19 732#define TPS65911_IRQ_GPIO4_F 20 733#define TPS65911_IRQ_GPIO5_R 21 734#define TPS65911_IRQ_GPIO5_F 22 735#define TPS65911_IRQ_WTCHDG 23 736#define TPS65911_IRQ_PWRDN 24 737 738#define TPS65911_NUM_IRQ 25 739 740 741/* GPIO Register Definitions */ 742#define TPS65910_GPIO_DEB BIT(2) 743#define TPS65910_GPIO_PUEN BIT(3) 744#define TPS65910_GPIO_CFG BIT(2) 745#define TPS65910_GPIO_STS BIT(1) 746#define TPS65910_GPIO_SET BIT(0) 747 748/* Max number of TPS65910/11 GPIOs */ 749#define TPS65910_NUM_GPIO 6 750#define TPS65911_NUM_GPIO 9 751#define TPS6591X_MAX_NUM_GPIO 9 752 753/* Regulator Index Definitions */ 754#define TPS65910_REG_VRTC 0 755#define TPS65910_REG_VIO 1 756#define TPS65910_REG_VDD1 2 757#define TPS65910_REG_VDD2 3 758#define TPS65910_REG_VDD3 4 759#define TPS65910_REG_VDIG1 5 760#define TPS65910_REG_VDIG2 6 761#define TPS65910_REG_VPLL 7 762#define TPS65910_REG_VDAC 8 763#define TPS65910_REG_VAUX1 9 764#define TPS65910_REG_VAUX2 10 765#define TPS65910_REG_VAUX33 11 766#define TPS65910_REG_VMMC 12 767 768#define TPS65911_REG_VDDCTRL 4 769#define TPS65911_REG_LDO1 5 770#define TPS65911_REG_LDO2 6 771#define TPS65911_REG_LDO3 7 772#define TPS65911_REG_LDO4 8 773#define TPS65911_REG_LDO5 9 774#define TPS65911_REG_LDO6 10 775#define TPS65911_REG_LDO7 11 776#define TPS65911_REG_LDO8 12 777 778/* Max number of TPS65910/11 regulators */ 779#define TPS65910_NUM_REGS 13 780 781/* External sleep controls through EN1/EN2/EN3/SLEEP inputs */ 782#define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 0x1 783#define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 0x2 784#define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 0x4 785#define TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP 0x8 786 787/* 788 * Sleep keepon data: Maintains the state in sleep mode 789 * @therm_keepon: Keep on the thermal monitoring in sleep state. 790 * @clkout32k_keepon: Keep on the 32KHz clock output in sleep state. 791 * @i2chs_keepon: Keep on high speed internal clock in sleep state. 792 */ 793struct tps65910_sleep_keepon_data { 794 unsigned therm_keepon:1; 795 unsigned clkout32k_keepon:1; 796 unsigned i2chs_keepon:1; 797}; 798 799/** 800 * struct tps65910_board 801 * Board platform data may be used to initialize regulators. 802 */ 803 804struct tps65910_board { 805 int gpio_base; 806 int irq; 807 int irq_base; 808 int vmbch_threshold; 809 int vmbch2_threshold; 810 bool en_dev_slp; 811 struct tps65910_sleep_keepon_data *slp_keepon; 812 unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS]; 813 bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO]; 814 struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS]; 815}; 816 817/** 818 * struct tps65910 - tps65910 sub-driver chip access routines 819 */ 820 821struct tps65910 { 822 struct device *dev; 823 struct i2c_client *i2c_client; 824 struct regmap *regmap; 825 struct mutex io_mutex; 826 unsigned int id; 827 828 /* Client devices */ 829 struct tps65910_pmic *pmic; 830 struct tps65910_rtc *rtc; 831 struct tps65910_power *power; 832 833 /* IRQ Handling */ 834 struct mutex irq_lock; 835 int chip_irq; 836 int irq_base; 837 int irq_num; 838 u32 irq_mask; 839}; 840 841struct tps65910_platform_data { 842 int irq; 843 int irq_base; 844}; 845 846int tps65910_irq_init(struct tps65910 *tps65910, int irq, 847 struct tps65910_platform_data *pdata); 848int tps65910_irq_exit(struct tps65910 *tps65910); 849 850static inline int tps65910_chip_id(struct tps65910 *tps65910) 851{ 852 return tps65910->id; 853} 854 855static inline int tps65910_reg_read(struct tps65910 *tps65910, u8 reg, 856 unsigned int *val) 857{ 858 return regmap_read(tps65910->regmap, reg, val); 859} 860 861static inline int tps65910_reg_write(struct tps65910 *tps65910, u8 reg, 862 unsigned int val) 863{ 864 return regmap_write(tps65910->regmap, reg, val); 865} 866 867static inline int tps65910_reg_set_bits(struct tps65910 *tps65910, u8 reg, 868 u8 mask) 869{ 870 return regmap_update_bits(tps65910->regmap, reg, mask, mask); 871} 872 873static inline int tps65910_reg_clear_bits(struct tps65910 *tps65910, u8 reg, 874 u8 mask) 875{ 876 return regmap_update_bits(tps65910->regmap, reg, mask, 0); 877} 878 879#endif /* __LINUX_MFD_TPS65910_H */