/drivers/w1/masters/ds1wm.c
C | 594 lines | 448 code | 109 blank | 37 comment | 39 complexity | e244ac3afdd6133cd4bad669e5caf317 MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
1/* 2 * 1-wire busmaster driver for DS1WM and ASICs with embedded DS1WMs 3 * such as HP iPAQs (including h5xxx, h2200, and devices with ASIC3 4 * like hx4700). 5 * 6 * Copyright (c) 2004-2005, Szabolcs Gyurko <szabolcs.gyurko@tlt.hu> 7 * Copyright (c) 2004-2007, Matt Reimer <mreimer@vpop.net> 8 * 9 * Use consistent with the GNU GPL is permitted, 10 * provided that this copyright notice is 11 * preserved in its entirety in all copies and derived works. 12 */ 13 14#include <linux/module.h> 15#include <linux/interrupt.h> 16#include <linux/irq.h> 17#include <linux/pm.h> 18#include <linux/platform_device.h> 19#include <linux/err.h> 20#include <linux/delay.h> 21#include <linux/mfd/core.h> 22#include <linux/mfd/ds1wm.h> 23#include <linux/slab.h> 24 25#include <asm/io.h> 26 27#include "../w1.h" 28#include "../w1_int.h" 29 30 31#define DS1WM_CMD 0x00 /* R/W 4 bits command */ 32#define DS1WM_DATA 0x01 /* R/W 8 bits, transmit/receive buffer */ 33#define DS1WM_INT 0x02 /* R/W interrupt status */ 34#define DS1WM_INT_EN 0x03 /* R/W interrupt enable */ 35#define DS1WM_CLKDIV 0x04 /* R/W 5 bits of divisor and pre-scale */ 36#define DS1WM_CNTRL 0x05 /* R/W master control register (not used yet) */ 37 38#define DS1WM_CMD_1W_RESET (1 << 0) /* force reset on 1-wire bus */ 39#define DS1WM_CMD_SRA (1 << 1) /* enable Search ROM accelerator mode */ 40#define DS1WM_CMD_DQ_OUTPUT (1 << 2) /* write only - forces bus low */ 41#define DS1WM_CMD_DQ_INPUT (1 << 3) /* read only - reflects state of bus */ 42#define DS1WM_CMD_RST (1 << 5) /* software reset */ 43#define DS1WM_CMD_OD (1 << 7) /* overdrive */ 44 45#define DS1WM_INT_PD (1 << 0) /* presence detect */ 46#define DS1WM_INT_PDR (1 << 1) /* presence detect result */ 47#define DS1WM_INT_TBE (1 << 2) /* tx buffer empty */ 48#define DS1WM_INT_TSRE (1 << 3) /* tx shift register empty */ 49#define DS1WM_INT_RBF (1 << 4) /* rx buffer full */ 50#define DS1WM_INT_RSRF (1 << 5) /* rx shift register full */ 51 52#define DS1WM_INTEN_EPD (1 << 0) /* enable presence detect int */ 53#define DS1WM_INTEN_IAS (1 << 1) /* INTR active state */ 54#define DS1WM_INTEN_ETBE (1 << 2) /* enable tx buffer empty int */ 55#define DS1WM_INTEN_ETMT (1 << 3) /* enable tx shift register empty int */ 56#define DS1WM_INTEN_ERBF (1 << 4) /* enable rx buffer full int */ 57#define DS1WM_INTEN_ERSRF (1 << 5) /* enable rx shift register full int */ 58#define DS1WM_INTEN_DQO (1 << 6) /* enable direct bus driving ops */ 59 60#define DS1WM_INTEN_NOT_IAS (~DS1WM_INTEN_IAS) /* all but INTR active state */ 61 62#define DS1WM_TIMEOUT (HZ * 5) 63 64static struct { 65 unsigned long freq; 66 unsigned long divisor; 67} freq[] = { 68 { 1000000, 0x80 }, 69 { 2000000, 0x84 }, 70 { 3000000, 0x81 }, 71 { 4000000, 0x88 }, 72 { 5000000, 0x82 }, 73 { 6000000, 0x85 }, 74 { 7000000, 0x83 }, 75 { 8000000, 0x8c }, 76 { 10000000, 0x86 }, 77 { 12000000, 0x89 }, 78 { 14000000, 0x87 }, 79 { 16000000, 0x90 }, 80 { 20000000, 0x8a }, 81 { 24000000, 0x8d }, 82 { 28000000, 0x8b }, 83 { 32000000, 0x94 }, 84 { 40000000, 0x8e }, 85 { 48000000, 0x91 }, 86 { 56000000, 0x8f }, 87 { 64000000, 0x98 }, 88 { 80000000, 0x92 }, 89 { 96000000, 0x95 }, 90 { 112000000, 0x93 }, 91 { 128000000, 0x9c }, 92/* you can continue this table, consult the OPERATION - CLOCK DIVISOR 93 section of the ds1wm spec sheet. */ 94}; 95 96struct ds1wm_data { 97 void __iomem *map; 98 int bus_shift; /* # of shifts to calc register offsets */ 99 struct platform_device *pdev; 100 const struct mfd_cell *cell; 101 int irq; 102 int slave_present; 103 void *reset_complete; 104 void *read_complete; 105 void *write_complete; 106 int read_error; 107 /* last byte received */ 108 u8 read_byte; 109 /* byte to write that makes all intr disabled, */ 110 /* considering active_state (IAS) (optimization) */ 111 u8 int_en_reg_none; 112 unsigned int reset_recover_delay; /* see ds1wm.h */ 113}; 114 115static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg, 116 u8 val) 117{ 118 __raw_writeb(val, ds1wm_data->map + (reg << ds1wm_data->bus_shift)); 119} 120 121static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg) 122{ 123 return __raw_readb(ds1wm_data->map + (reg << ds1wm_data->bus_shift)); 124} 125 126 127static irqreturn_t ds1wm_isr(int isr, void *data) 128{ 129 struct ds1wm_data *ds1wm_data = data; 130 u8 intr; 131 u8 inten = ds1wm_read_register(ds1wm_data, DS1WM_INT_EN); 132 /* if no bits are set in int enable register (except the IAS) 133 than go no further, reading the regs below has side effects */ 134 if (!(inten & DS1WM_INTEN_NOT_IAS)) 135 return IRQ_NONE; 136 137 ds1wm_write_register(ds1wm_data, 138 DS1WM_INT_EN, ds1wm_data->int_en_reg_none); 139 140 /* this read action clears the INTR and certain flags in ds1wm */ 141 intr = ds1wm_read_register(ds1wm_data, DS1WM_INT); 142 143 ds1wm_data->slave_present = (intr & DS1WM_INT_PDR) ? 0 : 1; 144 145 if ((intr & DS1WM_INT_TSRE) && ds1wm_data->write_complete) { 146 inten &= ~DS1WM_INTEN_ETMT; 147 complete(ds1wm_data->write_complete); 148 } 149 if (intr & DS1WM_INT_RBF) { 150 /* this read clears the RBF flag */ 151 ds1wm_data->read_byte = ds1wm_read_register(ds1wm_data, 152 DS1WM_DATA); 153 inten &= ~DS1WM_INTEN_ERBF; 154 if (ds1wm_data->read_complete) 155 complete(ds1wm_data->read_complete); 156 } 157 if ((intr & DS1WM_INT_PD) && ds1wm_data->reset_complete) { 158 inten &= ~DS1WM_INTEN_EPD; 159 complete(ds1wm_data->reset_complete); 160 } 161 162 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, inten); 163 return IRQ_HANDLED; 164} 165 166static int ds1wm_reset(struct ds1wm_data *ds1wm_data) 167{ 168 unsigned long timeleft; 169 DECLARE_COMPLETION_ONSTACK(reset_done); 170 171 ds1wm_data->reset_complete = &reset_done; 172 173 /* enable Presence detect only */ 174 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, DS1WM_INTEN_EPD | 175 ds1wm_data->int_en_reg_none); 176 177 ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_1W_RESET); 178 179 timeleft = wait_for_completion_timeout(&reset_done, DS1WM_TIMEOUT); 180 ds1wm_data->reset_complete = NULL; 181 if (!timeleft) { 182 dev_err(&ds1wm_data->pdev->dev, "reset failed, timed out\n"); 183 return 1; 184 } 185 186 if (!ds1wm_data->slave_present) { 187 dev_dbg(&ds1wm_data->pdev->dev, "reset: no devices found\n"); 188 return 1; 189 } 190 191 if (ds1wm_data->reset_recover_delay) 192 msleep(ds1wm_data->reset_recover_delay); 193 194 return 0; 195} 196 197static int ds1wm_write(struct ds1wm_data *ds1wm_data, u8 data) 198{ 199 unsigned long timeleft; 200 DECLARE_COMPLETION_ONSTACK(write_done); 201 ds1wm_data->write_complete = &write_done; 202 203 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, 204 ds1wm_data->int_en_reg_none | DS1WM_INTEN_ETMT); 205 206 ds1wm_write_register(ds1wm_data, DS1WM_DATA, data); 207 208 timeleft = wait_for_completion_timeout(&write_done, DS1WM_TIMEOUT); 209 210 ds1wm_data->write_complete = NULL; 211 if (!timeleft) { 212 dev_err(&ds1wm_data->pdev->dev, "write failed, timed out\n"); 213 return -ETIMEDOUT; 214 } 215 216 return 0; 217} 218 219static u8 ds1wm_read(struct ds1wm_data *ds1wm_data, unsigned char write_data) 220{ 221 unsigned long timeleft; 222 u8 intEnable = DS1WM_INTEN_ERBF | ds1wm_data->int_en_reg_none; 223 DECLARE_COMPLETION_ONSTACK(read_done); 224 225 ds1wm_read_register(ds1wm_data, DS1WM_DATA); 226 227 ds1wm_data->read_complete = &read_done; 228 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, intEnable); 229 230 ds1wm_write_register(ds1wm_data, DS1WM_DATA, write_data); 231 timeleft = wait_for_completion_timeout(&read_done, DS1WM_TIMEOUT); 232 233 ds1wm_data->read_complete = NULL; 234 if (!timeleft) { 235 dev_err(&ds1wm_data->pdev->dev, "read failed, timed out\n"); 236 ds1wm_data->read_error = -ETIMEDOUT; 237 return 0xFF; 238 } 239 ds1wm_data->read_error = 0; 240 return ds1wm_data->read_byte; 241} 242 243static int ds1wm_find_divisor(int gclk) 244{ 245 int i; 246 247 for (i = ARRAY_SIZE(freq)-1; i >= 0; --i) 248 if (gclk >= freq[i].freq) 249 return freq[i].divisor; 250 251 return 0; 252} 253 254static void ds1wm_up(struct ds1wm_data *ds1wm_data) 255{ 256 int divisor; 257 struct ds1wm_driver_data *plat = ds1wm_data->pdev->dev.platform_data; 258 259 if (ds1wm_data->cell->enable) 260 ds1wm_data->cell->enable(ds1wm_data->pdev); 261 262 divisor = ds1wm_find_divisor(plat->clock_rate); 263 dev_dbg(&ds1wm_data->pdev->dev, 264 "found divisor 0x%x for clock %d\n", divisor, plat->clock_rate); 265 if (divisor == 0) { 266 dev_err(&ds1wm_data->pdev->dev, 267 "no suitable divisor for %dHz clock\n", 268 plat->clock_rate); 269 return; 270 } 271 ds1wm_write_register(ds1wm_data, DS1WM_CLKDIV, divisor); 272 273 /* Let the w1 clock stabilize. */ 274 msleep(1); 275 276 ds1wm_reset(ds1wm_data); 277} 278 279static void ds1wm_down(struct ds1wm_data *ds1wm_data) 280{ 281 ds1wm_reset(ds1wm_data); 282 283 /* Disable interrupts. */ 284 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, 285 ds1wm_data->int_en_reg_none); 286 287 if (ds1wm_data->cell->disable) 288 ds1wm_data->cell->disable(ds1wm_data->pdev); 289} 290 291/* --------------------------------------------------------------------- */ 292/* w1 methods */ 293 294static u8 ds1wm_read_byte(void *data) 295{ 296 struct ds1wm_data *ds1wm_data = data; 297 298 return ds1wm_read(ds1wm_data, 0xff); 299} 300 301static void ds1wm_write_byte(void *data, u8 byte) 302{ 303 struct ds1wm_data *ds1wm_data = data; 304 305 ds1wm_write(ds1wm_data, byte); 306} 307 308static u8 ds1wm_reset_bus(void *data) 309{ 310 struct ds1wm_data *ds1wm_data = data; 311 312 ds1wm_reset(ds1wm_data); 313 314 return 0; 315} 316 317static void ds1wm_search(void *data, struct w1_master *master_dev, 318 u8 search_type, w1_slave_found_callback slave_found) 319{ 320 struct ds1wm_data *ds1wm_data = data; 321 int i; 322 int ms_discrep_bit = -1; 323 u64 r = 0; /* holds the progress of the search */ 324 u64 r_prime, d; 325 unsigned slaves_found = 0; 326 unsigned int pass = 0; 327 328 dev_dbg(&ds1wm_data->pdev->dev, "search begin\n"); 329 while (true) { 330 ++pass; 331 if (pass > 100) { 332 dev_dbg(&ds1wm_data->pdev->dev, 333 "too many attempts (100), search aborted\n"); 334 return; 335 } 336 337 if (ds1wm_reset(ds1wm_data)) { 338 dev_dbg(&ds1wm_data->pdev->dev, 339 "pass: %d reset error (or no slaves)\n", pass); 340 break; 341 } 342 343 dev_dbg(&ds1wm_data->pdev->dev, 344 "pass: %d r : %0#18llx writing SEARCH_ROM\n", pass, r); 345 ds1wm_write(ds1wm_data, search_type); 346 dev_dbg(&ds1wm_data->pdev->dev, 347 "pass: %d entering ASM\n", pass); 348 ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_SRA); 349 dev_dbg(&ds1wm_data->pdev->dev, 350 "pass: %d begining nibble loop\n", pass); 351 352 r_prime = 0; 353 d = 0; 354 /* we work one nibble at a time */ 355 /* each nibble is interleaved to form a byte */ 356 for (i = 0; i < 16; i++) { 357 358 unsigned char resp, _r, _r_prime, _d; 359 360 _r = (r >> (4*i)) & 0xf; 361 _r = ((_r & 0x1) << 1) | 362 ((_r & 0x2) << 2) | 363 ((_r & 0x4) << 3) | 364 ((_r & 0x8) << 4); 365 366 /* writes _r, then reads back: */ 367 resp = ds1wm_read(ds1wm_data, _r); 368 369 if (ds1wm_data->read_error) { 370 dev_err(&ds1wm_data->pdev->dev, 371 "pass: %d nibble: %d read error\n", pass, i); 372 break; 373 } 374 375 _r_prime = ((resp & 0x02) >> 1) | 376 ((resp & 0x08) >> 2) | 377 ((resp & 0x20) >> 3) | 378 ((resp & 0x80) >> 4); 379 380 _d = ((resp & 0x01) >> 0) | 381 ((resp & 0x04) >> 1) | 382 ((resp & 0x10) >> 2) | 383 ((resp & 0x40) >> 3); 384 385 r_prime |= (unsigned long long) _r_prime << (i * 4); 386 d |= (unsigned long long) _d << (i * 4); 387 388 } 389 if (ds1wm_data->read_error) { 390 dev_err(&ds1wm_data->pdev->dev, 391 "pass: %d read error, retrying\n", pass); 392 break; 393 } 394 dev_dbg(&ds1wm_data->pdev->dev, 395 "pass: %d r\': %0#18llx d:%0#18llx\n", 396 pass, r_prime, d); 397 dev_dbg(&ds1wm_data->pdev->dev, 398 "pass: %d nibble loop complete, exiting ASM\n", pass); 399 ds1wm_write_register(ds1wm_data, DS1WM_CMD, ~DS1WM_CMD_SRA); 400 dev_dbg(&ds1wm_data->pdev->dev, 401 "pass: %d resetting bus\n", pass); 402 ds1wm_reset(ds1wm_data); 403 if ((r_prime & ((u64)1 << 63)) && (d & ((u64)1 << 63))) { 404 dev_err(&ds1wm_data->pdev->dev, 405 "pass: %d bus error, retrying\n", pass); 406 continue; /* start over */ 407 } 408 409 410 dev_dbg(&ds1wm_data->pdev->dev, 411 "pass: %d found %0#18llx\n", pass, r_prime); 412 slave_found(master_dev, r_prime); 413 ++slaves_found; 414 dev_dbg(&ds1wm_data->pdev->dev, 415 "pass: %d complete, preparing next pass\n", pass); 416 417 /* any discrepency found which we already choose the 418 '1' branch is now is now irrelevant we reveal the 419 next branch with this: */ 420 d &= ~r; 421 /* find last bit set, i.e. the most signif. bit set */ 422 ms_discrep_bit = fls64(d) - 1; 423 dev_dbg(&ds1wm_data->pdev->dev, 424 "pass: %d new d:%0#18llx MS discrep bit:%d\n", 425 pass, d, ms_discrep_bit); 426 427 /* prev_ms_discrep_bit = ms_discrep_bit; 428 prepare for next ROM search: */ 429 if (ms_discrep_bit == -1) 430 break; 431 432 r = (r & ~(~0ull << (ms_discrep_bit))) | 1 << ms_discrep_bit; 433 } /* end while true */ 434 dev_dbg(&ds1wm_data->pdev->dev, 435 "pass: %d total: %d search done ms d bit pos: %d\n", pass, 436 slaves_found, ms_discrep_bit); 437} 438 439/* --------------------------------------------------------------------- */ 440 441static struct w1_bus_master ds1wm_master = { 442 .read_byte = ds1wm_read_byte, 443 .write_byte = ds1wm_write_byte, 444 .reset_bus = ds1wm_reset_bus, 445 .search = ds1wm_search, 446}; 447 448static int ds1wm_probe(struct platform_device *pdev) 449{ 450 struct ds1wm_data *ds1wm_data; 451 struct ds1wm_driver_data *plat; 452 struct resource *res; 453 int ret; 454 455 if (!pdev) 456 return -ENODEV; 457 458 ds1wm_data = kzalloc(sizeof(*ds1wm_data), GFP_KERNEL); 459 if (!ds1wm_data) 460 return -ENOMEM; 461 462 platform_set_drvdata(pdev, ds1wm_data); 463 464 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 465 if (!res) { 466 ret = -ENXIO; 467 goto err0; 468 } 469 ds1wm_data->map = ioremap(res->start, resource_size(res)); 470 if (!ds1wm_data->map) { 471 ret = -ENOMEM; 472 goto err0; 473 } 474 475 /* calculate bus shift from mem resource */ 476 ds1wm_data->bus_shift = resource_size(res) >> 3; 477 478 ds1wm_data->pdev = pdev; 479 ds1wm_data->cell = mfd_get_cell(pdev); 480 if (!ds1wm_data->cell) { 481 ret = -ENODEV; 482 goto err1; 483 } 484 plat = pdev->dev.platform_data; 485 if (!plat) { 486 ret = -ENODEV; 487 goto err1; 488 } 489 490 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 491 if (!res) { 492 ret = -ENXIO; 493 goto err1; 494 } 495 ds1wm_data->irq = res->start; 496 ds1wm_data->int_en_reg_none = (plat->active_high ? DS1WM_INTEN_IAS : 0); 497 ds1wm_data->reset_recover_delay = plat->reset_recover_delay; 498 499 if (res->flags & IORESOURCE_IRQ_HIGHEDGE) 500 irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING); 501 if (res->flags & IORESOURCE_IRQ_LOWEDGE) 502 irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING); 503 504 ret = request_irq(ds1wm_data->irq, ds1wm_isr, 505 IRQF_DISABLED | IRQF_SHARED, "ds1wm", ds1wm_data); 506 if (ret) 507 goto err1; 508 509 ds1wm_up(ds1wm_data); 510 511 ds1wm_master.data = (void *)ds1wm_data; 512 513 ret = w1_add_master_device(&ds1wm_master); 514 if (ret) 515 goto err2; 516 517 return 0; 518 519err2: 520 ds1wm_down(ds1wm_data); 521 free_irq(ds1wm_data->irq, ds1wm_data); 522err1: 523 iounmap(ds1wm_data->map); 524err0: 525 kfree(ds1wm_data); 526 527 return ret; 528} 529 530#ifdef CONFIG_PM 531static int ds1wm_suspend(struct platform_device *pdev, pm_message_t state) 532{ 533 struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev); 534 535 ds1wm_down(ds1wm_data); 536 537 return 0; 538} 539 540static int ds1wm_resume(struct platform_device *pdev) 541{ 542 struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev); 543 544 ds1wm_up(ds1wm_data); 545 546 return 0; 547} 548#else 549#define ds1wm_suspend NULL 550#define ds1wm_resume NULL 551#endif 552 553static int ds1wm_remove(struct platform_device *pdev) 554{ 555 struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev); 556 557 w1_remove_master_device(&ds1wm_master); 558 ds1wm_down(ds1wm_data); 559 free_irq(ds1wm_data->irq, ds1wm_data); 560 iounmap(ds1wm_data->map); 561 kfree(ds1wm_data); 562 563 return 0; 564} 565 566static struct platform_driver ds1wm_driver = { 567 .driver = { 568 .name = "ds1wm", 569 }, 570 .probe = ds1wm_probe, 571 .remove = ds1wm_remove, 572 .suspend = ds1wm_suspend, 573 .resume = ds1wm_resume 574}; 575 576static int __init ds1wm_init(void) 577{ 578 printk("DS1WM w1 busmaster driver - (c) 2004 Szabolcs Gyurko\n"); 579 return platform_driver_register(&ds1wm_driver); 580} 581 582static void __exit ds1wm_exit(void) 583{ 584 platform_driver_unregister(&ds1wm_driver); 585} 586 587module_init(ds1wm_init); 588module_exit(ds1wm_exit); 589 590MODULE_LICENSE("GPL"); 591MODULE_AUTHOR("Szabolcs Gyurko <szabolcs.gyurko@tlt.hu>, " 592 "Matt Reimer <mreimer@vpop.net>," 593 "Jean-Francois Dagenais <dagenaisj@sonatest.com>"); 594MODULE_DESCRIPTION("DS1WM w1 busmaster driver");