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/drivers/video/tdfxfb.c

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t
C | 1689 lines | 1271 code | 219 blank | 199 comment | 156 complexity | 9e74a12e5acf11967165bf31446a17f7 MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
   1/*
   2 *
   3 * tdfxfb.c
   4 *
   5 * Author: Hannu Mallat <hmallat@cc.hut.fi>
   6 *
   7 * Copyright © 1999 Hannu Mallat
   8 * All rights reserved
   9 *
  10 * Created      : Thu Sep 23 18:17:43 1999, hmallat
  11 * Last modified: Tue Nov  2 21:19:47 1999, hmallat
  12 *
  13 * I2C part copied from the i2c-voodoo3.c driver by:
  14 * Frodo Looijaard <frodol@dds.nl>,
  15 * Philip Edelbrock <phil@netroedge.com>,
  16 * Ralph Metzler <rjkm@thp.uni-koeln.de>, and
  17 * Mark D. Studebaker <mdsxyz123@yahoo.com>
  18 *
  19 * Lots of the information here comes from the Daryll Strauss' Banshee
  20 * patches to the XF86 server, and the rest comes from the 3dfx
  21 * Banshee specification. I'm very much indebted to Daryll for his
  22 * work on the X server.
  23 *
  24 * Voodoo3 support was contributed Harold Oga. Lots of additions
  25 * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila
  26 * Kesmarki. Thanks guys!
  27 *
  28 * Voodoo1 and Voodoo2 support aren't relevant to this driver as they
  29 * behave very differently from the Voodoo3/4/5. For anyone wanting to
  30 * use frame buffer on the Voodoo1/2, see the sstfb driver (which is
  31 * located at http://www.sourceforge.net/projects/sstfb).
  32 *
  33 * While I _am_ grateful to 3Dfx for releasing the specs for Banshee,
  34 * I do wish the next version is a bit more complete. Without the XF86
  35 * patches I couldn't have gotten even this far... for instance, the
  36 * extensions to the VGA register set go completely unmentioned in the
  37 * spec! Also, lots of references are made to the 'SST core', but no
  38 * spec is publicly available, AFAIK.
  39 *
  40 * The structure of this driver comes pretty much from the Permedia
  41 * driver by Ilario Nardinocchi, which in turn is based on skeletonfb.
  42 *
  43 * TODO:
  44 * - multihead support (basically need to support an array of fb_infos)
  45 * - support other architectures (PPC, Alpha); does the fact that the VGA
  46 *   core can be accessed only thru I/O (not memory mapped) complicate
  47 *   things?
  48 *
  49 * Version history:
  50 *
  51 * 0.1.4 (released 2002-05-28)	ported over to new fbdev api by James Simmons
  52 *
  53 * 0.1.3 (released 1999-11-02)	added Attila's panning support, code
  54 *				reorg, hwcursor address page size alignment
  55 *				(for mmapping both frame buffer and regs),
  56 *				and my changes to get rid of hardcoded
  57 *				VGA i/o register locations (uses PCI
  58 *				configuration info now)
  59 * 0.1.2 (released 1999-10-19)	added Attila Kesmarki's bug fixes and
  60 *				improvements
  61 * 0.1.1 (released 1999-10-07)	added Voodoo3 support by Harold Oga.
  62 * 0.1.0 (released 1999-10-06)	initial version
  63 *
  64 */
  65
  66#include <linux/module.h>
  67#include <linux/kernel.h>
  68#include <linux/errno.h>
  69#include <linux/string.h>
  70#include <linux/mm.h>
  71#include <linux/slab.h>
  72#include <linux/fb.h>
  73#include <linux/init.h>
  74#include <linux/pci.h>
  75#include <asm/io.h>
  76
  77#include <video/tdfx.h>
  78
  79#define DPRINTK(a, b...) pr_debug("fb: %s: " a, __func__ , ## b)
  80
  81#ifdef CONFIG_MTRR
  82#include <asm/mtrr.h>
  83#else
  84/* duplicate asm/mtrr.h defines to work on archs without mtrr */
  85#define MTRR_TYPE_WRCOMB     1
  86
  87static inline int mtrr_add(unsigned long base, unsigned long size,
  88				unsigned int type, char increment)
  89{
  90    return -ENODEV;
  91}
  92static inline int mtrr_del(int reg, unsigned long base,
  93				unsigned long size)
  94{
  95    return -ENODEV;
  96}
  97#endif
  98
  99#define BANSHEE_MAX_PIXCLOCK 270000
 100#define VOODOO3_MAX_PIXCLOCK 300000
 101#define VOODOO5_MAX_PIXCLOCK 350000
 102
 103static struct fb_fix_screeninfo tdfx_fix __devinitdata = {
 104	.type =		FB_TYPE_PACKED_PIXELS,
 105	.visual =	FB_VISUAL_PSEUDOCOLOR,
 106	.ypanstep =	1,
 107	.ywrapstep =	1,
 108	.accel =	FB_ACCEL_3DFX_BANSHEE
 109};
 110
 111static struct fb_var_screeninfo tdfx_var __devinitdata = {
 112	/* "640x480, 8 bpp @ 60 Hz */
 113	.xres =		640,
 114	.yres =		480,
 115	.xres_virtual =	640,
 116	.yres_virtual =	1024,
 117	.bits_per_pixel = 8,
 118	.red =		{0, 8, 0},
 119	.blue =		{0, 8, 0},
 120	.green =	{0, 8, 0},
 121	.activate =	FB_ACTIVATE_NOW,
 122	.height =	-1,
 123	.width =	-1,
 124	.accel_flags =	FB_ACCELF_TEXT,
 125	.pixclock =	39722,
 126	.left_margin =	40,
 127	.right_margin =	24,
 128	.upper_margin =	32,
 129	.lower_margin =	11,
 130	.hsync_len =	96,
 131	.vsync_len =	2,
 132	.vmode =	FB_VMODE_NONINTERLACED
 133};
 134
 135/*
 136 * PCI driver prototypes
 137 */
 138static int __devinit tdfxfb_probe(struct pci_dev *pdev,
 139				  const struct pci_device_id *id);
 140static void __devexit tdfxfb_remove(struct pci_dev *pdev);
 141
 142static struct pci_device_id tdfxfb_id_table[] = {
 143	{ PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_BANSHEE,
 144	  PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
 145	  0xff0000, 0 },
 146	{ PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO3,
 147	  PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
 148	  0xff0000, 0 },
 149	{ PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO5,
 150	  PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
 151	  0xff0000, 0 },
 152	{ 0, }
 153};
 154
 155static struct pci_driver tdfxfb_driver = {
 156	.name		= "tdfxfb",
 157	.id_table	= tdfxfb_id_table,
 158	.probe		= tdfxfb_probe,
 159	.remove		= __devexit_p(tdfxfb_remove),
 160};
 161
 162MODULE_DEVICE_TABLE(pci, tdfxfb_id_table);
 163
 164/*
 165 * Driver data
 166 */
 167static int nopan;
 168static int nowrap = 1;      /* not implemented (yet) */
 169static int hwcursor = 1;
 170static char *mode_option __devinitdata;
 171/* mtrr option */
 172static int nomtrr __devinitdata;
 173
 174/* -------------------------------------------------------------------------
 175 *			Hardware-specific funcions
 176 * ------------------------------------------------------------------------- */
 177
 178static inline u8 vga_inb(struct tdfx_par *par, u32 reg)
 179{
 180	return inb(par->iobase + reg - 0x300);
 181}
 182
 183static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val)
 184{
 185	outb(val, par->iobase + reg - 0x300);
 186}
 187
 188static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val)
 189{
 190	vga_outb(par, GRA_I, idx);
 191	wmb();
 192	vga_outb(par, GRA_D, val);
 193	wmb();
 194}
 195
 196static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val)
 197{
 198	vga_outb(par, SEQ_I, idx);
 199	wmb();
 200	vga_outb(par, SEQ_D, val);
 201	wmb();
 202}
 203
 204static inline u8 seq_inb(struct tdfx_par *par, u32 idx)
 205{
 206	vga_outb(par, SEQ_I, idx);
 207	mb();
 208	return vga_inb(par, SEQ_D);
 209}
 210
 211static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val)
 212{
 213	vga_outb(par, CRT_I, idx);
 214	wmb();
 215	vga_outb(par, CRT_D, val);
 216	wmb();
 217}
 218
 219static inline u8 crt_inb(struct tdfx_par *par, u32 idx)
 220{
 221	vga_outb(par, CRT_I, idx);
 222	mb();
 223	return vga_inb(par, CRT_D);
 224}
 225
 226static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val)
 227{
 228	unsigned char tmp;
 229
 230	tmp = vga_inb(par, IS1_R);
 231	vga_outb(par, ATT_IW, idx);
 232	vga_outb(par, ATT_IW, val);
 233}
 234
 235static inline void vga_disable_video(struct tdfx_par *par)
 236{
 237	unsigned char s;
 238
 239	s = seq_inb(par, 0x01) | 0x20;
 240	seq_outb(par, 0x00, 0x01);
 241	seq_outb(par, 0x01, s);
 242	seq_outb(par, 0x00, 0x03);
 243}
 244
 245static inline void vga_enable_video(struct tdfx_par *par)
 246{
 247	unsigned char s;
 248
 249	s = seq_inb(par, 0x01) & 0xdf;
 250	seq_outb(par, 0x00, 0x01);
 251	seq_outb(par, 0x01, s);
 252	seq_outb(par, 0x00, 0x03);
 253}
 254
 255static inline void vga_enable_palette(struct tdfx_par *par)
 256{
 257	vga_inb(par, IS1_R);
 258	mb();
 259	vga_outb(par, ATT_IW, 0x20);
 260}
 261
 262static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg)
 263{
 264	return readl(par->regbase_virt + reg);
 265}
 266
 267static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val)
 268{
 269	writel(val, par->regbase_virt + reg);
 270}
 271
 272static inline void banshee_make_room(struct tdfx_par *par, int size)
 273{
 274	/* Note: The Voodoo3's onboard FIFO has 32 slots. This loop
 275	 * won't quit if you ask for more. */
 276	while ((tdfx_inl(par, STATUS) & 0x1f) < size - 1)
 277		cpu_relax();
 278}
 279
 280static int banshee_wait_idle(struct fb_info *info)
 281{
 282	struct tdfx_par *par = info->par;
 283	int i = 0;
 284
 285	banshee_make_room(par, 1);
 286	tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP);
 287
 288	do {
 289		if ((tdfx_inl(par, STATUS) & STATUS_BUSY) == 0)
 290			i++;
 291	} while (i < 3);
 292
 293	return 0;
 294}
 295
 296/*
 297 * Set the color of a palette entry in 8bpp mode
 298 */
 299static inline void do_setpalentry(struct tdfx_par *par, unsigned regno, u32 c)
 300{
 301	banshee_make_room(par, 2);
 302	tdfx_outl(par, DACADDR, regno);
 303	/* read after write makes it working */
 304	tdfx_inl(par, DACADDR);
 305	tdfx_outl(par, DACDATA, c);
 306}
 307
 308static u32 do_calc_pll(int freq, int *freq_out)
 309{
 310	int m, n, k, best_m, best_n, best_k, best_error;
 311	int fref = 14318;
 312
 313	best_error = freq;
 314	best_n = best_m = best_k = 0;
 315
 316	for (k = 3; k >= 0; k--) {
 317		for (m = 63; m >= 0; m--) {
 318			/*
 319			 * Estimate value of n that produces target frequency
 320			 * with current m and k
 321			 */
 322			int n_estimated = ((freq * (m + 2) << k) / fref) - 2;
 323
 324			/* Search neighborhood of estimated n */
 325			for (n = max(0, n_estimated);
 326				n <= min(255, n_estimated + 1);
 327				n++) {
 328				/*
 329				 * Calculate PLL freqency with current m, k and
 330				 * estimated n
 331				 */
 332				int f = (fref * (n + 2) / (m + 2)) >> k;
 333				int error = abs(f - freq);
 334
 335				/*
 336				 * If this is the closest we've come to the
 337				 * target frequency then remember n, m and k
 338				 */
 339				if (error < best_error) {
 340					best_error = error;
 341					best_n = n;
 342					best_m = m;
 343					best_k = k;
 344				}
 345			}
 346		}
 347	}
 348
 349	n = best_n;
 350	m = best_m;
 351	k = best_k;
 352	*freq_out = (fref * (n + 2) / (m + 2)) >> k;
 353
 354	return (n << 8) | (m << 2) | k;
 355}
 356
 357static void do_write_regs(struct fb_info *info, struct banshee_reg *reg)
 358{
 359	struct tdfx_par *par = info->par;
 360	int i;
 361
 362	banshee_wait_idle(info);
 363
 364	tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01);
 365
 366	crt_outb(par, 0x11, crt_inb(par, 0x11) & 0x7f); /* CRT unprotect */
 367
 368	banshee_make_room(par, 3);
 369	tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF);
 370	tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001);
 371#if 0
 372	tdfx_outl(par, PLLCTRL1, reg->mempll);
 373	tdfx_outl(par, PLLCTRL2, reg->gfxpll);
 374#endif
 375	tdfx_outl(par, PLLCTRL0, reg->vidpll);
 376
 377	vga_outb(par, MISC_W, reg->misc[0x00] | 0x01);
 378
 379	for (i = 0; i < 5; i++)
 380		seq_outb(par, i, reg->seq[i]);
 381
 382	for (i = 0; i < 25; i++)
 383		crt_outb(par, i, reg->crt[i]);
 384
 385	for (i = 0; i < 9; i++)
 386		gra_outb(par, i, reg->gra[i]);
 387
 388	for (i = 0; i < 21; i++)
 389		att_outb(par, i, reg->att[i]);
 390
 391	crt_outb(par, 0x1a, reg->ext[0]);
 392	crt_outb(par, 0x1b, reg->ext[1]);
 393
 394	vga_enable_palette(par);
 395	vga_enable_video(par);
 396
 397	banshee_make_room(par, 9);
 398	tdfx_outl(par, VGAINIT0, reg->vgainit0);
 399	tdfx_outl(par, DACMODE, reg->dacmode);
 400	tdfx_outl(par, VIDDESKSTRIDE, reg->stride);
 401	tdfx_outl(par, HWCURPATADDR, reg->curspataddr);
 402
 403	tdfx_outl(par, VIDSCREENSIZE, reg->screensize);
 404	tdfx_outl(par, VIDDESKSTART, reg->startaddr);
 405	tdfx_outl(par, VIDPROCCFG, reg->vidcfg);
 406	tdfx_outl(par, VGAINIT1, reg->vgainit1);
 407	tdfx_outl(par, MISCINIT0, reg->miscinit0);
 408
 409	banshee_make_room(par, 8);
 410	tdfx_outl(par, SRCBASE, reg->startaddr);
 411	tdfx_outl(par, DSTBASE, reg->startaddr);
 412	tdfx_outl(par, COMMANDEXTRA_2D, 0);
 413	tdfx_outl(par, CLIP0MIN, 0);
 414	tdfx_outl(par, CLIP0MAX, 0x0fff0fff);
 415	tdfx_outl(par, CLIP1MIN, 0);
 416	tdfx_outl(par, CLIP1MAX, 0x0fff0fff);
 417	tdfx_outl(par, SRCXY, 0);
 418
 419	banshee_wait_idle(info);
 420}
 421
 422static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id)
 423{
 424	u32 draminit0 = tdfx_inl(par, DRAMINIT0);
 425	u32 draminit1 = tdfx_inl(par, DRAMINIT1);
 426	u32 miscinit1;
 427	int num_chips = (draminit0 & DRAMINIT0_SGRAM_NUM) ? 8 : 4;
 428	int chip_size; /* in MB */
 429	int has_sgram = draminit1 & DRAMINIT1_MEM_SDRAM;
 430
 431	if (dev_id < PCI_DEVICE_ID_3DFX_VOODOO5) {
 432		/* Banshee/Voodoo3 */
 433		chip_size = 2;
 434		if (has_sgram && !(draminit0 & DRAMINIT0_SGRAM_TYPE))
 435			chip_size = 1;
 436	} else {
 437		/* Voodoo4/5 */
 438		has_sgram = 0;
 439		chip_size = draminit0 & DRAMINIT0_SGRAM_TYPE_MASK;
 440		chip_size = 1 << (chip_size >> DRAMINIT0_SGRAM_TYPE_SHIFT);
 441	}
 442
 443	/* disable block writes for SDRAM */
 444	miscinit1 = tdfx_inl(par, MISCINIT1);
 445	miscinit1 |= has_sgram ? 0 : MISCINIT1_2DBLOCK_DIS;
 446	miscinit1 |= MISCINIT1_CLUT_INV;
 447
 448	banshee_make_room(par, 1);
 449	tdfx_outl(par, MISCINIT1, miscinit1);
 450	return num_chips * chip_size * 1024l * 1024;
 451}
 452
 453/* ------------------------------------------------------------------------- */
 454
 455static int tdfxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 456{
 457	struct tdfx_par *par = info->par;
 458	u32 lpitch;
 459
 460	if (var->bits_per_pixel != 8  && var->bits_per_pixel != 16 &&
 461	    var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
 462		DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
 463		return -EINVAL;
 464	}
 465
 466	if (var->xres != var->xres_virtual)
 467		var->xres_virtual = var->xres;
 468
 469	if (var->yres > var->yres_virtual)
 470		var->yres_virtual = var->yres;
 471
 472	if (var->xoffset) {
 473		DPRINTK("xoffset not supported\n");
 474		return -EINVAL;
 475	}
 476	var->yoffset = 0;
 477
 478	/*
 479	 * Banshee doesn't support interlace, but Voodoo4/5 and probably
 480	 * Voodoo3 do.
 481	 * no direct information about device id now?
 482	 *  use max_pixclock for this...
 483	 */
 484	if (((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) &&
 485	    (par->max_pixclock < VOODOO3_MAX_PIXCLOCK)) {
 486		DPRINTK("interlace not supported\n");
 487		return -EINVAL;
 488	}
 489
 490	if (info->monspecs.hfmax && info->monspecs.vfmax &&
 491	    info->monspecs.dclkmax && fb_validate_mode(var, info) < 0) {
 492		DPRINTK("mode outside monitor's specs\n");
 493		return -EINVAL;
 494	}
 495
 496	var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
 497	lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
 498
 499	if (var->xres < 320 || var->xres > 2048) {
 500		DPRINTK("width not supported: %u\n", var->xres);
 501		return -EINVAL;
 502	}
 503
 504	if (var->yres < 200 || var->yres > 2048) {
 505		DPRINTK("height not supported: %u\n", var->yres);
 506		return -EINVAL;
 507	}
 508
 509	if (lpitch * var->yres_virtual > info->fix.smem_len) {
 510		var->yres_virtual = info->fix.smem_len / lpitch;
 511		if (var->yres_virtual < var->yres) {
 512			DPRINTK("no memory for screen (%ux%ux%u)\n",
 513				var->xres, var->yres_virtual,
 514				var->bits_per_pixel);
 515			return -EINVAL;
 516		}
 517	}
 518
 519	if (PICOS2KHZ(var->pixclock) > par->max_pixclock) {
 520		DPRINTK("pixclock too high (%ldKHz)\n",
 521			PICOS2KHZ(var->pixclock));
 522		return -EINVAL;
 523	}
 524
 525	var->transp.offset = 0;
 526	var->transp.length = 0;
 527	switch (var->bits_per_pixel) {
 528	case 8:
 529		var->red.length = 8;
 530		var->red.offset = 0;
 531		var->green = var->red;
 532		var->blue = var->red;
 533		break;
 534	case 16:
 535		var->red.offset   = 11;
 536		var->red.length   = 5;
 537		var->green.offset = 5;
 538		var->green.length = 6;
 539		var->blue.offset  = 0;
 540		var->blue.length  = 5;
 541		break;
 542	case 32:
 543		var->transp.offset = 24;
 544		var->transp.length = 8;
 545	case 24:
 546		var->red.offset = 16;
 547		var->green.offset = 8;
 548		var->blue.offset = 0;
 549		var->red.length = var->green.length = var->blue.length = 8;
 550		break;
 551	}
 552	var->width = -1;
 553	var->height = -1;
 554
 555	var->accel_flags = FB_ACCELF_TEXT;
 556
 557	DPRINTK("Checking graphics mode at %dx%d depth %d\n",
 558		var->xres, var->yres, var->bits_per_pixel);
 559	return 0;
 560}
 561
 562static int tdfxfb_set_par(struct fb_info *info)
 563{
 564	struct tdfx_par *par = info->par;
 565	u32 hdispend = info->var.xres;
 566	u32 hsyncsta = hdispend + info->var.right_margin;
 567	u32 hsyncend = hsyncsta + info->var.hsync_len;
 568	u32 htotal   = hsyncend + info->var.left_margin;
 569	u32 hd, hs, he, ht, hbs, hbe;
 570	u32 vd, vs, ve, vt, vbs, vbe;
 571	struct banshee_reg reg;
 572	int fout, freq;
 573	u32 wd;
 574	u32 cpp = (info->var.bits_per_pixel + 7) >> 3;
 575
 576	memset(&reg, 0, sizeof(reg));
 577
 578	reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE |
 579		     VIDCFG_CURS_X11 |
 580		     ((cpp - 1) << VIDCFG_PIXFMT_SHIFT) |
 581		     (cpp != 1 ? VIDCFG_CLUT_BYPASS : 0);
 582
 583	/* PLL settings */
 584	freq = PICOS2KHZ(info->var.pixclock);
 585
 586	reg.vidcfg &= ~VIDCFG_2X;
 587
 588	if (freq > par->max_pixclock / 2) {
 589		freq = freq > par->max_pixclock ? par->max_pixclock : freq;
 590		reg.dacmode |= DACMODE_2X;
 591		reg.vidcfg  |= VIDCFG_2X;
 592		hdispend >>= 1;
 593		hsyncsta >>= 1;
 594		hsyncend >>= 1;
 595		htotal   >>= 1;
 596	}
 597
 598	wd = (hdispend >> 3) - 1;
 599	hd  = wd;
 600	hs  = (hsyncsta >> 3) - 1;
 601	he  = (hsyncend >> 3) - 1;
 602	ht  = (htotal >> 3) - 1;
 603	hbs = hd;
 604	hbe = ht;
 605
 606	if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
 607		vd = (info->var.yres << 1) - 1;
 608		vs  = vd + (info->var.lower_margin << 1);
 609		ve  = vs + (info->var.vsync_len << 1);
 610		vt = ve + (info->var.upper_margin << 1) - 1;
 611		reg.screensize = info->var.xres | (info->var.yres << 13);
 612		reg.vidcfg |= VIDCFG_HALF_MODE;
 613		reg.crt[0x09] = 0x80;
 614	} else {
 615		vd = info->var.yres - 1;
 616		vs  = vd + info->var.lower_margin;
 617		ve  = vs + info->var.vsync_len;
 618		vt = ve + info->var.upper_margin - 1;
 619		reg.screensize = info->var.xres | (info->var.yres << 12);
 620		reg.vidcfg &= ~VIDCFG_HALF_MODE;
 621	}
 622	vbs = vd;
 623	vbe = vt;
 624
 625	/* this is all pretty standard VGA register stuffing */
 626	reg.misc[0x00] = 0x0f |
 627			(info->var.xres < 400 ? 0xa0 :
 628			 info->var.xres < 480 ? 0x60 :
 629			 info->var.xres < 768 ? 0xe0 : 0x20);
 630
 631	reg.gra[0x05] = 0x40;
 632	reg.gra[0x06] = 0x05;
 633	reg.gra[0x07] = 0x0f;
 634	reg.gra[0x08] = 0xff;
 635
 636	reg.att[0x00] = 0x00;
 637	reg.att[0x01] = 0x01;
 638	reg.att[0x02] = 0x02;
 639	reg.att[0x03] = 0x03;
 640	reg.att[0x04] = 0x04;
 641	reg.att[0x05] = 0x05;
 642	reg.att[0x06] = 0x06;
 643	reg.att[0x07] = 0x07;
 644	reg.att[0x08] = 0x08;
 645	reg.att[0x09] = 0x09;
 646	reg.att[0x0a] = 0x0a;
 647	reg.att[0x0b] = 0x0b;
 648	reg.att[0x0c] = 0x0c;
 649	reg.att[0x0d] = 0x0d;
 650	reg.att[0x0e] = 0x0e;
 651	reg.att[0x0f] = 0x0f;
 652	reg.att[0x10] = 0x41;
 653	reg.att[0x12] = 0x0f;
 654
 655	reg.seq[0x00] = 0x03;
 656	reg.seq[0x01] = 0x01; /* fixme: clkdiv2? */
 657	reg.seq[0x02] = 0x0f;
 658	reg.seq[0x03] = 0x00;
 659	reg.seq[0x04] = 0x0e;
 660
 661	reg.crt[0x00] = ht - 4;
 662	reg.crt[0x01] = hd;
 663	reg.crt[0x02] = hbs;
 664	reg.crt[0x03] = 0x80 | (hbe & 0x1f);
 665	reg.crt[0x04] = hs;
 666	reg.crt[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
 667	reg.crt[0x06] = vt;
 668	reg.crt[0x07] = ((vs & 0x200) >> 2) |
 669			((vd & 0x200) >> 3) |
 670			((vt & 0x200) >> 4) | 0x10 |
 671			((vbs & 0x100) >> 5) |
 672			((vs & 0x100) >> 6) |
 673			((vd & 0x100) >> 7) |
 674			((vt & 0x100) >> 8);
 675	reg.crt[0x09] |= 0x40 | ((vbs & 0x200) >> 4);
 676	reg.crt[0x10] = vs;
 677	reg.crt[0x11] = (ve & 0x0f) | 0x20;
 678	reg.crt[0x12] = vd;
 679	reg.crt[0x13] = wd;
 680	reg.crt[0x15] = vbs;
 681	reg.crt[0x16] = vbe + 1;
 682	reg.crt[0x17] = 0xc3;
 683	reg.crt[0x18] = 0xff;
 684
 685	/* Banshee's nonvga stuff */
 686	reg.ext[0x00] = (((ht & 0x100) >> 8) |
 687			((hd & 0x100) >> 6) |
 688			((hbs & 0x100) >> 4) |
 689			((hbe & 0x40) >> 1) |
 690			((hs & 0x100) >> 2) |
 691			((he & 0x20) << 2));
 692	reg.ext[0x01] = (((vt & 0x400) >> 10) |
 693			((vd & 0x400) >> 8) |
 694			((vbs & 0x400) >> 6) |
 695			((vbe & 0x400) >> 4));
 696
 697	reg.vgainit0 =	VGAINIT0_8BIT_DAC     |
 698			VGAINIT0_EXT_ENABLE   |
 699			VGAINIT0_WAKEUP_3C3   |
 700			VGAINIT0_ALT_READBACK |
 701			VGAINIT0_EXTSHIFTOUT;
 702	reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff;
 703
 704	if (hwcursor)
 705		reg.curspataddr = info->fix.smem_len;
 706
 707	reg.cursloc   = 0;
 708
 709	reg.cursc0    = 0;
 710	reg.cursc1    = 0xffffff;
 711
 712	reg.stride    = info->var.xres * cpp;
 713	reg.startaddr = info->var.yoffset * reg.stride
 714			+ info->var.xoffset * cpp;
 715
 716	reg.vidpll = do_calc_pll(freq, &fout);
 717#if 0
 718	reg.mempll = do_calc_pll(..., &fout);
 719	reg.gfxpll = do_calc_pll(..., &fout);
 720#endif
 721
 722	if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
 723		reg.vidcfg |= VIDCFG_INTERLACE;
 724	reg.miscinit0 = tdfx_inl(par, MISCINIT0);
 725
 726#if defined(__BIG_ENDIAN)
 727	switch (info->var.bits_per_pixel) {
 728	case 8:
 729	case 24:
 730		reg.miscinit0 &= ~(1 << 30);
 731		reg.miscinit0 &= ~(1 << 31);
 732		break;
 733	case 16:
 734		reg.miscinit0 |= (1 << 30);
 735		reg.miscinit0 |= (1 << 31);
 736		break;
 737	case 32:
 738		reg.miscinit0 |= (1 << 30);
 739		reg.miscinit0 &= ~(1 << 31);
 740		break;
 741	}
 742#endif
 743	do_write_regs(info, &reg);
 744
 745	/* Now change fb_fix_screeninfo according to changes in par */
 746	info->fix.line_length = reg.stride;
 747	info->fix.visual = (info->var.bits_per_pixel == 8)
 748				? FB_VISUAL_PSEUDOCOLOR
 749				: FB_VISUAL_TRUECOLOR;
 750	DPRINTK("Graphics mode is now set at %dx%d depth %d\n",
 751		info->var.xres, info->var.yres, info->var.bits_per_pixel);
 752	return 0;
 753}
 754
 755/* A handy macro shamelessly pinched from matroxfb */
 756#define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
 757
 758static int tdfxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
 759			    unsigned blue, unsigned transp,
 760			    struct fb_info *info)
 761{
 762	struct tdfx_par *par = info->par;
 763	u32 rgbcol;
 764
 765	if (regno >= info->cmap.len || regno > 255)
 766		return 1;
 767
 768	/* grayscale works only partially under directcolor */
 769	if (info->var.grayscale) {
 770		/* grayscale = 0.30*R + 0.59*G + 0.11*B */
 771		blue = (red * 77 + green * 151 + blue * 28) >> 8;
 772		green = blue;
 773		red = blue;
 774	}
 775
 776	switch (info->fix.visual) {
 777	case FB_VISUAL_PSEUDOCOLOR:
 778		rgbcol = (((u32)red   & 0xff00) << 8) |
 779			 (((u32)green & 0xff00) << 0) |
 780			 (((u32)blue  & 0xff00) >> 8);
 781		do_setpalentry(par, regno, rgbcol);
 782		break;
 783	/* Truecolor has no hardware color palettes. */
 784	case FB_VISUAL_TRUECOLOR:
 785		if (regno < 16) {
 786			rgbcol = (CNVT_TOHW(red, info->var.red.length) <<
 787				  info->var.red.offset) |
 788				(CNVT_TOHW(green, info->var.green.length) <<
 789				 info->var.green.offset) |
 790				(CNVT_TOHW(blue, info->var.blue.length) <<
 791				 info->var.blue.offset) |
 792				(CNVT_TOHW(transp, info->var.transp.length) <<
 793				 info->var.transp.offset);
 794			par->palette[regno] = rgbcol;
 795		}
 796
 797		break;
 798	default:
 799		DPRINTK("bad depth %u\n", info->var.bits_per_pixel);
 800		break;
 801	}
 802
 803	return 0;
 804}
 805
 806/* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
 807static int tdfxfb_blank(int blank, struct fb_info *info)
 808{
 809	struct tdfx_par *par = info->par;
 810	int vgablank = 1;
 811	u32 dacmode = tdfx_inl(par, DACMODE);
 812
 813	dacmode &= ~(BIT(1) | BIT(3));
 814
 815	switch (blank) {
 816	case FB_BLANK_UNBLANK: /* Screen: On; HSync: On, VSync: On */
 817		vgablank = 0;
 818		break;
 819	case FB_BLANK_NORMAL: /* Screen: Off; HSync: On, VSync: On */
 820		break;
 821	case FB_BLANK_VSYNC_SUSPEND: /* Screen: Off; HSync: On, VSync: Off */
 822		dacmode |= BIT(3);
 823		break;
 824	case FB_BLANK_HSYNC_SUSPEND: /* Screen: Off; HSync: Off, VSync: On */
 825		dacmode |= BIT(1);
 826		break;
 827	case FB_BLANK_POWERDOWN: /* Screen: Off; HSync: Off, VSync: Off */
 828		dacmode |= BIT(1) | BIT(3);
 829		break;
 830	}
 831
 832	banshee_make_room(par, 1);
 833	tdfx_outl(par, DACMODE, dacmode);
 834	if (vgablank)
 835		vga_disable_video(par);
 836	else
 837		vga_enable_video(par);
 838	return 0;
 839}
 840
 841/*
 842 * Set the starting position of the visible screen to var->yoffset
 843 */
 844static int tdfxfb_pan_display(struct fb_var_screeninfo *var,
 845			      struct fb_info *info)
 846{
 847	struct tdfx_par *par = info->par;
 848	u32 addr = var->yoffset * info->fix.line_length;
 849
 850	if (nopan || var->xoffset)
 851		return -EINVAL;
 852
 853	banshee_make_room(par, 1);
 854	tdfx_outl(par, VIDDESKSTART, addr);
 855
 856	return 0;
 857}
 858
 859#ifdef CONFIG_FB_3DFX_ACCEL
 860/*
 861 * FillRect 2D command (solidfill or invert (via ROP_XOR))
 862 */
 863static void tdfxfb_fillrect(struct fb_info *info,
 864			    const struct fb_fillrect *rect)
 865{
 866	struct tdfx_par *par = info->par;
 867	u32 bpp = info->var.bits_per_pixel;
 868	u32 stride = info->fix.line_length;
 869	u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
 870	int tdfx_rop;
 871	u32 dx = rect->dx;
 872	u32 dy = rect->dy;
 873	u32 dstbase = 0;
 874
 875	if (rect->rop == ROP_COPY)
 876		tdfx_rop = TDFX_ROP_COPY;
 877	else
 878		tdfx_rop = TDFX_ROP_XOR;
 879
 880	/* assume always rect->height < 4096 */
 881	if (dy + rect->height > 4095) {
 882		dstbase = stride * dy;
 883		dy = 0;
 884	}
 885	/* assume always rect->width < 4096 */
 886	if (dx + rect->width > 4095) {
 887		dstbase += dx * bpp >> 3;
 888		dx = 0;
 889	}
 890	banshee_make_room(par, 6);
 891	tdfx_outl(par, DSTFORMAT, fmt);
 892	if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
 893		tdfx_outl(par, COLORFORE, rect->color);
 894	} else { /* FB_VISUAL_TRUECOLOR */
 895		tdfx_outl(par, COLORFORE, par->palette[rect->color]);
 896	}
 897	tdfx_outl(par, COMMAND_2D, COMMAND_2D_FILLRECT | (tdfx_rop << 24));
 898	tdfx_outl(par, DSTBASE, dstbase);
 899	tdfx_outl(par, DSTSIZE, rect->width | (rect->height << 16));
 900	tdfx_outl(par, LAUNCH_2D, dx | (dy << 16));
 901}
 902
 903/*
 904 * Screen-to-Screen BitBlt 2D command (for the bmove fb op.)
 905 */
 906static void tdfxfb_copyarea(struct fb_info *info,
 907			    const struct fb_copyarea *area)
 908{
 909	struct tdfx_par *par = info->par;
 910	u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy;
 911	u32 bpp = info->var.bits_per_pixel;
 912	u32 stride = info->fix.line_length;
 913	u32 blitcmd = COMMAND_2D_S2S_BITBLT | (TDFX_ROP_COPY << 24);
 914	u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
 915	u32 dstbase = 0;
 916	u32 srcbase = 0;
 917
 918	/* assume always area->height < 4096 */
 919	if (sy + area->height > 4095) {
 920		srcbase = stride * sy;
 921		sy = 0;
 922	}
 923	/* assume always area->width < 4096 */
 924	if (sx + area->width > 4095) {
 925		srcbase += sx * bpp >> 3;
 926		sx = 0;
 927	}
 928	/* assume always area->height < 4096 */
 929	if (dy + area->height > 4095) {
 930		dstbase = stride * dy;
 931		dy = 0;
 932	}
 933	/* assume always area->width < 4096 */
 934	if (dx + area->width > 4095) {
 935		dstbase += dx * bpp >> 3;
 936		dx = 0;
 937	}
 938
 939	if (area->sx <= area->dx) {
 940		/* -X */
 941		blitcmd |= BIT(14);
 942		sx += area->width - 1;
 943		dx += area->width - 1;
 944	}
 945	if (area->sy <= area->dy) {
 946		/* -Y */
 947		blitcmd |= BIT(15);
 948		sy += area->height - 1;
 949		dy += area->height - 1;
 950	}
 951
 952	banshee_make_room(par, 8);
 953
 954	tdfx_outl(par, SRCFORMAT, fmt);
 955	tdfx_outl(par, DSTFORMAT, fmt);
 956	tdfx_outl(par, COMMAND_2D, blitcmd);
 957	tdfx_outl(par, DSTSIZE, area->width | (area->height << 16));
 958	tdfx_outl(par, DSTXY, dx | (dy << 16));
 959	tdfx_outl(par, SRCBASE, srcbase);
 960	tdfx_outl(par, DSTBASE, dstbase);
 961	tdfx_outl(par, LAUNCH_2D, sx | (sy << 16));
 962}
 963
 964static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image)
 965{
 966	struct tdfx_par *par = info->par;
 967	int size = image->height * ((image->width * image->depth + 7) >> 3);
 968	int fifo_free;
 969	int i, stride = info->fix.line_length;
 970	u32 bpp = info->var.bits_per_pixel;
 971	u32 dstfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13);
 972	u8 *chardata = (u8 *) image->data;
 973	u32 srcfmt;
 974	u32 dx = image->dx;
 975	u32 dy = image->dy;
 976	u32 dstbase = 0;
 977
 978	if (image->depth != 1) {
 979#ifdef BROKEN_CODE
 980		banshee_make_room(par, 6 + ((size + 3) >> 2));
 981		srcfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13) |
 982			0x400000;
 983#else
 984		cfb_imageblit(info, image);
 985#endif
 986		return;
 987	}
 988	banshee_make_room(par, 9);
 989	switch (info->fix.visual) {
 990	case FB_VISUAL_PSEUDOCOLOR:
 991		tdfx_outl(par, COLORFORE, image->fg_color);
 992		tdfx_outl(par, COLORBACK, image->bg_color);
 993		break;
 994	case FB_VISUAL_TRUECOLOR:
 995	default:
 996		tdfx_outl(par, COLORFORE,
 997			  par->palette[image->fg_color]);
 998		tdfx_outl(par, COLORBACK,
 999			  par->palette[image->bg_color]);
1000	}
1001#ifdef __BIG_ENDIAN
1002	srcfmt = 0x400000 | BIT(20);
1003#else
1004	srcfmt = 0x400000;
1005#endif
1006	/* assume always image->height < 4096 */
1007	if (dy + image->height > 4095) {
1008		dstbase = stride * dy;
1009		dy = 0;
1010	}
1011	/* assume always image->width < 4096 */
1012	if (dx + image->width > 4095) {
1013		dstbase += dx * bpp >> 3;
1014		dx = 0;
1015	}
1016
1017	tdfx_outl(par, DSTBASE, dstbase);
1018	tdfx_outl(par, SRCXY, 0);
1019	tdfx_outl(par, DSTXY, dx | (dy << 16));
1020	tdfx_outl(par, COMMAND_2D,
1021		  COMMAND_2D_H2S_BITBLT | (TDFX_ROP_COPY << 24));
1022	tdfx_outl(par, SRCFORMAT, srcfmt);
1023	tdfx_outl(par, DSTFORMAT, dstfmt);
1024	tdfx_outl(par, DSTSIZE, image->width | (image->height << 16));
1025
1026	/* A count of how many free FIFO entries we've requested.
1027	 * When this goes negative, we need to request more. */
1028	fifo_free = 0;
1029
1030	/* Send four bytes at a time of data */
1031	for (i = (size >> 2); i > 0; i--) {
1032		if (--fifo_free < 0) {
1033			fifo_free = 31;
1034			banshee_make_room(par, fifo_free);
1035		}
1036		tdfx_outl(par, LAUNCH_2D, *(u32 *)chardata);
1037		chardata += 4;
1038	}
1039
1040	/* Send the leftovers now */
1041	banshee_make_room(par, 3);
1042	switch (size % 4) {
1043	case 0:
1044		break;
1045	case 1:
1046		tdfx_outl(par, LAUNCH_2D, *chardata);
1047		break;
1048	case 2:
1049		tdfx_outl(par, LAUNCH_2D, *(u16 *)chardata);
1050		break;
1051	case 3:
1052		tdfx_outl(par, LAUNCH_2D,
1053			*(u16 *)chardata | (chardata[3] << 24));
1054		break;
1055	}
1056}
1057#endif /* CONFIG_FB_3DFX_ACCEL */
1058
1059static int tdfxfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1060{
1061	struct tdfx_par *par = info->par;
1062	u32 vidcfg;
1063
1064	if (!hwcursor)
1065		return -EINVAL;	/* just to force soft_cursor() call */
1066
1067	/* Too large of a cursor or wrong bpp :-( */
1068	if (cursor->image.width > 64 ||
1069	    cursor->image.height > 64 ||
1070	    cursor->image.depth > 1)
1071		return -EINVAL;
1072
1073	vidcfg = tdfx_inl(par, VIDPROCCFG);
1074	if (cursor->enable)
1075		tdfx_outl(par, VIDPROCCFG, vidcfg | VIDCFG_HWCURSOR_ENABLE);
1076	else
1077		tdfx_outl(par, VIDPROCCFG, vidcfg & ~VIDCFG_HWCURSOR_ENABLE);
1078
1079	/*
1080	 * If the cursor is not be changed this means either we want the
1081	 * current cursor state (if enable is set) or we want to query what
1082	 * we can do with the cursor (if enable is not set)
1083	 */
1084	if (!cursor->set)
1085		return 0;
1086
1087	/* fix cursor color - XFree86 forgets to restore it properly */
1088	if (cursor->set & FB_CUR_SETCMAP) {
1089		struct fb_cmap cmap = info->cmap;
1090		u32 bg_idx = cursor->image.bg_color;
1091		u32 fg_idx = cursor->image.fg_color;
1092		unsigned long bg_color, fg_color;
1093
1094		fg_color = (((u32)cmap.red[fg_idx]   & 0xff00) << 8) |
1095			   (((u32)cmap.green[fg_idx] & 0xff00) << 0) |
1096			   (((u32)cmap.blue[fg_idx]  & 0xff00) >> 8);
1097		bg_color = (((u32)cmap.red[bg_idx]   & 0xff00) << 8) |
1098			   (((u32)cmap.green[bg_idx] & 0xff00) << 0) |
1099			   (((u32)cmap.blue[bg_idx]  & 0xff00) >> 8);
1100		banshee_make_room(par, 2);
1101		tdfx_outl(par, HWCURC0, bg_color);
1102		tdfx_outl(par, HWCURC1, fg_color);
1103	}
1104
1105	if (cursor->set & FB_CUR_SETPOS) {
1106		int x = cursor->image.dx;
1107		int y = cursor->image.dy - info->var.yoffset;
1108
1109		x += 63;
1110		y += 63;
1111		banshee_make_room(par, 1);
1112		tdfx_outl(par, HWCURLOC, (y << 16) + x);
1113	}
1114	if (cursor->set & (FB_CUR_SETIMAGE | FB_CUR_SETSHAPE)) {
1115		/*
1116		 * Voodoo 3 and above cards use 2 monochrome cursor patterns.
1117		 *    The reason is so the card can fetch 8 words at a time
1118		 * and are stored on chip for use for the next 8 scanlines.
1119		 * This reduces the number of times for access to draw the
1120		 * cursor for each screen refresh.
1121		 *    Each pattern is a bitmap of 64 bit wide and 64 bit high
1122		 * (total of 8192 bits or 1024 bytes). The two patterns are
1123		 * stored in such a way that pattern 0 always resides in the
1124		 * lower half (least significant 64 bits) of a 128 bit word
1125		 * and pattern 1 the upper half. If you examine the data of
1126		 * the cursor image the graphics card uses then from the
1127		 * beginning you see line one of pattern 0, line one of
1128		 * pattern 1, line two of pattern 0, line two of pattern 1,
1129		 * etc etc. The linear stride for the cursor is always 16 bytes
1130		 * (128 bits) which is the maximum cursor width times two for
1131		 * the two monochrome patterns.
1132		 */
1133		u8 __iomem *cursorbase = info->screen_base + info->fix.smem_len;
1134		u8 *bitmap = (u8 *)cursor->image.data;
1135		u8 *mask = (u8 *)cursor->mask;
1136		int i;
1137
1138		fb_memset(cursorbase, 0, 1024);
1139
1140		for (i = 0; i < cursor->image.height; i++) {
1141			int h = 0;
1142			int j = (cursor->image.width + 7) >> 3;
1143
1144			for (; j > 0; j--) {
1145				u8 data = *mask ^ *bitmap;
1146				if (cursor->rop == ROP_COPY)
1147					data = *mask & *bitmap;
1148				/* Pattern 0. Copy the cursor mask to it */
1149				fb_writeb(*mask, cursorbase + h);
1150				mask++;
1151				/* Pattern 1. Copy the cursor bitmap to it */
1152				fb_writeb(data, cursorbase + h + 8);
1153				bitmap++;
1154				h++;
1155			}
1156			cursorbase += 16;
1157		}
1158	}
1159	return 0;
1160}
1161
1162static struct fb_ops tdfxfb_ops = {
1163	.owner		= THIS_MODULE,
1164	.fb_check_var	= tdfxfb_check_var,
1165	.fb_set_par	= tdfxfb_set_par,
1166	.fb_setcolreg	= tdfxfb_setcolreg,
1167	.fb_blank	= tdfxfb_blank,
1168	.fb_pan_display	= tdfxfb_pan_display,
1169	.fb_sync	= banshee_wait_idle,
1170	.fb_cursor	= tdfxfb_cursor,
1171#ifdef CONFIG_FB_3DFX_ACCEL
1172	.fb_fillrect	= tdfxfb_fillrect,
1173	.fb_copyarea	= tdfxfb_copyarea,
1174	.fb_imageblit	= tdfxfb_imageblit,
1175#else
1176	.fb_fillrect	= cfb_fillrect,
1177	.fb_copyarea	= cfb_copyarea,
1178	.fb_imageblit	= cfb_imageblit,
1179#endif
1180};
1181
1182#ifdef CONFIG_FB_3DFX_I2C
1183/* The voo GPIO registers don't have individual masks for each bit
1184   so we always have to read before writing. */
1185
1186static void tdfxfb_i2c_setscl(void *data, int val)
1187{
1188	struct tdfxfb_i2c_chan 	*chan = data;
1189	struct tdfx_par 	*par = chan->par;
1190	unsigned int r;
1191
1192	r = tdfx_inl(par, VIDSERPARPORT);
1193	if (val)
1194		r |= I2C_SCL_OUT;
1195	else
1196		r &= ~I2C_SCL_OUT;
1197	tdfx_outl(par, VIDSERPARPORT, r);
1198	tdfx_inl(par, VIDSERPARPORT);	/* flush posted write */
1199}
1200
1201static void tdfxfb_i2c_setsda(void *data, int val)
1202{
1203	struct tdfxfb_i2c_chan 	*chan = data;
1204	struct tdfx_par 	*par = chan->par;
1205	unsigned int r;
1206
1207	r = tdfx_inl(par, VIDSERPARPORT);
1208	if (val)
1209		r |= I2C_SDA_OUT;
1210	else
1211		r &= ~I2C_SDA_OUT;
1212	tdfx_outl(par, VIDSERPARPORT, r);
1213	tdfx_inl(par, VIDSERPARPORT);	/* flush posted write */
1214}
1215
1216/* The GPIO pins are open drain, so the pins always remain outputs.
1217   We rely on the i2c-algo-bit routines to set the pins high before
1218   reading the input from other chips. */
1219
1220static int tdfxfb_i2c_getscl(void *data)
1221{
1222	struct tdfxfb_i2c_chan 	*chan = data;
1223	struct tdfx_par 	*par = chan->par;
1224
1225	return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SCL_IN));
1226}
1227
1228static int tdfxfb_i2c_getsda(void *data)
1229{
1230	struct tdfxfb_i2c_chan 	*chan = data;
1231	struct tdfx_par 	*par = chan->par;
1232
1233	return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SDA_IN));
1234}
1235
1236static void tdfxfb_ddc_setscl(void *data, int val)
1237{
1238	struct tdfxfb_i2c_chan 	*chan = data;
1239	struct tdfx_par 	*par = chan->par;
1240	unsigned int r;
1241
1242	r = tdfx_inl(par, VIDSERPARPORT);
1243	if (val)
1244		r |= DDC_SCL_OUT;
1245	else
1246		r &= ~DDC_SCL_OUT;
1247	tdfx_outl(par, VIDSERPARPORT, r);
1248	tdfx_inl(par, VIDSERPARPORT);	/* flush posted write */
1249}
1250
1251static void tdfxfb_ddc_setsda(void *data, int val)
1252{
1253	struct tdfxfb_i2c_chan 	*chan = data;
1254	struct tdfx_par 	*par = chan->par;
1255	unsigned int r;
1256
1257	r = tdfx_inl(par, VIDSERPARPORT);
1258	if (val)
1259		r |= DDC_SDA_OUT;
1260	else
1261		r &= ~DDC_SDA_OUT;
1262	tdfx_outl(par, VIDSERPARPORT, r);
1263	tdfx_inl(par, VIDSERPARPORT);	/* flush posted write */
1264}
1265
1266static int tdfxfb_ddc_getscl(void *data)
1267{
1268	struct tdfxfb_i2c_chan 	*chan = data;
1269	struct tdfx_par 	*par = chan->par;
1270
1271	return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SCL_IN));
1272}
1273
1274static int tdfxfb_ddc_getsda(void *data)
1275{
1276	struct tdfxfb_i2c_chan 	*chan = data;
1277	struct tdfx_par 	*par = chan->par;
1278
1279	return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SDA_IN));
1280}
1281
1282static int __devinit tdfxfb_setup_ddc_bus(struct tdfxfb_i2c_chan *chan,
1283					  const char *name, struct device *dev)
1284{
1285	int rc;
1286
1287	strlcpy(chan->adapter.name, name, sizeof(chan->adapter.name));
1288	chan->adapter.owner		= THIS_MODULE;
1289	chan->adapter.class		= I2C_CLASS_DDC;
1290	chan->adapter.algo_data		= &chan->algo;
1291	chan->adapter.dev.parent	= dev;
1292	chan->algo.setsda		= tdfxfb_ddc_setsda;
1293	chan->algo.setscl		= tdfxfb_ddc_setscl;
1294	chan->algo.getsda		= tdfxfb_ddc_getsda;
1295	chan->algo.getscl		= tdfxfb_ddc_getscl;
1296	chan->algo.udelay		= 10;
1297	chan->algo.timeout		= msecs_to_jiffies(500);
1298	chan->algo.data 		= chan;
1299
1300	i2c_set_adapdata(&chan->adapter, chan);
1301
1302	rc = i2c_bit_add_bus(&chan->adapter);
1303	if (rc == 0)
1304		DPRINTK("I2C bus %s registered.\n", name);
1305	else
1306		chan->par = NULL;
1307
1308	return rc;
1309}
1310
1311static int __devinit tdfxfb_setup_i2c_bus(struct tdfxfb_i2c_chan *chan,
1312					  const char *name, struct device *dev)
1313{
1314	int rc;
1315
1316	strlcpy(chan->adapter.name, name, sizeof(chan->adapter.name));
1317	chan->adapter.owner		= THIS_MODULE;
1318	chan->adapter.algo_data		= &chan->algo;
1319	chan->adapter.dev.parent	= dev;
1320	chan->algo.setsda		= tdfxfb_i2c_setsda;
1321	chan->algo.setscl		= tdfxfb_i2c_setscl;
1322	chan->algo.getsda		= tdfxfb_i2c_getsda;
1323	chan->algo.getscl		= tdfxfb_i2c_getscl;
1324	chan->algo.udelay		= 10;
1325	chan->algo.timeout		= msecs_to_jiffies(500);
1326	chan->algo.data 		= chan;
1327
1328	i2c_set_adapdata(&chan->adapter, chan);
1329
1330	rc = i2c_bit_add_bus(&chan->adapter);
1331	if (rc == 0)
1332		DPRINTK("I2C bus %s registered.\n", name);
1333	else
1334		chan->par = NULL;
1335
1336	return rc;
1337}
1338
1339static void __devinit tdfxfb_create_i2c_busses(struct fb_info *info)
1340{
1341	struct tdfx_par *par = info->par;
1342
1343	tdfx_outl(par, VIDINFORMAT, 0x8160);
1344	tdfx_outl(par, VIDSERPARPORT, 0xcffc0020);
1345
1346	par->chan[0].par = par;
1347	par->chan[1].par = par;
1348
1349	tdfxfb_setup_ddc_bus(&par->chan[0], "Voodoo3-DDC", info->dev);
1350	tdfxfb_setup_i2c_bus(&par->chan[1], "Voodoo3-I2C", info->dev);
1351}
1352
1353static void tdfxfb_delete_i2c_busses(struct tdfx_par *par)
1354{
1355	if (par->chan[0].par)
1356		i2c_del_adapter(&par->chan[0].adapter);
1357	par->chan[0].par = NULL;
1358
1359	if (par->chan[1].par)
1360		i2c_del_adapter(&par->chan[1].adapter);
1361	par->chan[1].par = NULL;
1362}
1363
1364static int tdfxfb_probe_i2c_connector(struct tdfx_par *par,
1365				      struct fb_monspecs *specs)
1366{
1367	u8 *edid = NULL;
1368
1369	DPRINTK("Probe DDC Bus\n");
1370	if (par->chan[0].par)
1371		edid = fb_ddc_read(&par->chan[0].adapter);
1372
1373	if (edid) {
1374		fb_edid_to_monspecs(edid, specs);
1375		kfree(edid);
1376		return 0;
1377	}
1378	return 1;
1379}
1380#endif /* CONFIG_FB_3DFX_I2C */
1381
1382/**
1383 *      tdfxfb_probe - Device Initializiation
1384 *
1385 *      @pdev:  PCI Device to initialize
1386 *      @id:    PCI Device ID
1387 *
1388 *      Initializes and allocates resources for PCI device @pdev.
1389 *
1390 */
1391static int __devinit tdfxfb_probe(struct pci_dev *pdev,
1392				  const struct pci_device_id *id)
1393{
1394	struct tdfx_par *default_par;
1395	struct fb_info *info;
1396	int err, lpitch;
1397	struct fb_monspecs *specs;
1398	bool found;
1399
1400	err = pci_enable_device(pdev);
1401	if (err) {
1402		printk(KERN_ERR "tdfxfb: Can't enable pdev: %d\n", err);
1403		return err;
1404	}
1405
1406	info = framebuffer_alloc(sizeof(struct tdfx_par), &pdev->dev);
1407
1408	if (!info)
1409		return -ENOMEM;
1410
1411	default_par = info->par;
1412	info->fix = tdfx_fix;
1413
1414	/* Configure the default fb_fix_screeninfo first */
1415	switch (pdev->device) {
1416	case PCI_DEVICE_ID_3DFX_BANSHEE:
1417		strcpy(info->fix.id, "3Dfx Banshee");
1418		default_par->max_pixclock = BANSHEE_MAX_PIXCLOCK;
1419		break;
1420	case PCI_DEVICE_ID_3DFX_VOODOO3:
1421		strcpy(info->fix.id, "3Dfx Voodoo3");
1422		default_par->max_pixclock = VOODOO3_MAX_PIXCLOCK;
1423		break;
1424	case PCI_DEVICE_ID_3DFX_VOODOO5:
1425		strcpy(info->fix.id, "3Dfx Voodoo5");
1426		default_par->max_pixclock = VOODOO5_MAX_PIXCLOCK;
1427		break;
1428	}
1429
1430	info->fix.mmio_start = pci_resource_start(pdev, 0);
1431	info->fix.mmio_len = pci_resource_len(pdev, 0);
1432	if (!request_mem_region(info->fix.mmio_start, info->fix.mmio_len,
1433				"tdfx regbase")) {
1434		printk(KERN_ERR "tdfxfb: Can't reserve regbase\n");
1435		goto out_err;
1436	}
1437
1438	default_par->regbase_virt =
1439		ioremap_nocache(info->fix.mmio_start, info->fix.mmio_len);
1440	if (!default_par->regbase_virt) {
1441		printk(KERN_ERR "fb: Can't remap %s register area.\n",
1442				info->fix.id);
1443		goto out_err_regbase;
1444	}
1445
1446	info->fix.smem_start = pci_resource_start(pdev, 1);
1447	info->fix.smem_len = do_lfb_size(default_par, pdev->device);
1448	if (!info->fix.smem_len) {
1449		printk(KERN_ERR "fb: Can't count %s memory.\n", info->fix.id);
1450		goto out_err_regbase;
1451	}
1452
1453	if (!request_mem_region(info->fix.smem_start,
1454				pci_resource_len(pdev, 1), "tdfx smem")) {
1455		printk(KERN_ERR "tdfxfb: Can't reserve smem\n");
1456		goto out_err_regbase;
1457	}
1458
1459	info->screen_base = ioremap_nocache(info->fix.smem_start,
1460					    info->fix.smem_len);
1461	if (!info->screen_base) {
1462		printk(KERN_ERR "fb: Can't remap %s framebuffer.\n",
1463				info->fix.id);
1464		goto out_err_screenbase;
1465	}
1466
1467	default_par->iobase = pci_resource_start(pdev, 2);
1468
1469	if (!request_region(pci_resource_start(pdev, 2),
1470			    pci_resource_len(pdev, 2), "tdfx iobase")) {
1471		printk(KERN_ERR "tdfxfb: Can't reserve iobase\n");
1472		goto out_err_screenbase;
1473	}
1474
1475	printk(KERN_INFO "fb: %s memory = %dK\n", info->fix.id,
1476			info->fix.smem_len >> 10);
1477
1478	default_par->mtrr_handle = -1;
1479	if (!nomtrr)
1480		default_par->mtrr_handle =
1481			mtrr_add(info->fix.smem_start, info->fix.smem_len,
1482				 MTRR_TYPE_WRCOMB, 1);
1483
1484	info->fix.ypanstep	= nopan ? 0 : 1;
1485	info->fix.ywrapstep	= nowrap ? 0 : 1;
1486
1487	info->fbops		= &tdfxfb_ops;
1488	info->pseudo_palette	= default_par->palette;
1489	info->flags		= FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1490#ifdef CONFIG_FB_3DFX_ACCEL
1491	info->flags		|= FBINFO_HWACCEL_FILLRECT |
1492				   FBINFO_HWACCEL_COPYAREA |
1493				   FBINFO_HWACCEL_IMAGEBLIT |
1494				   FBINFO_READS_FAST;
1495#endif
1496	/* reserve 8192 bits for cursor */
1497	/* the 2.4 driver says PAGE_MASK boundary is not enough for Voodoo4 */
1498	if (hwcursor)
1499		info->fix.smem_len = (info->fix.smem_len - 1024) &
1500					(PAGE_MASK << 1);
1501	specs = &info->monspecs;
1502	found = false;
1503	info->var.bits_per_pixel = 8;
1504#ifdef CONFIG_FB_3DFX_I2C
1505	tdfxfb_create_i2c_busses(info);
1506	err = tdfxfb_probe_i2c_connector(default_par, specs);
1507
1508	if (!err) {
1509		if (specs->modedb == NULL)
1510			DPRINTK("Unable to get Mode Database\n");
1511		else {
1512			const struct fb_videomode *m;
1513
1514			fb_videomode_to_modelist(specs->modedb,
1515						 specs->modedb_len,
1516						 &info->modelist);
1517			m = fb_find_best_display(specs, &info->modelist);
1518			if (m) {
1519				fb_videomode_to_var(&info->var, m);
1520				/* fill all other info->var's fields */
1521				if (tdfxfb_check_var(&info->var, info) < 0)
1522					info->var = tdfx_var;
1523				else
1524					found = true;
1525			}
1526		}
1527	}
1528#endif
1529	if (!mode_option && !found)
1530		mode_option = "640x480@60";
1531
1532	if (mode_option) {
1533		err = fb_find_mode(&info->var, info, mode_option,
1534				   specs->modedb, specs->modedb_len,
1535				   NULL, info->var.bits_per_pixel);
1536		if (!err || err == 4)
1537			info->var = tdfx_var;
1538	}
1539
1540	if (found) {
1541		fb_destroy_modedb(specs->modedb);
1542		specs->modedb = NULL;
1543	}
1544
1545	/* maximize virtual vertical length */
1546	lpitch = info->var.xres_virtual * ((info->var.bits_per_pixel + 7) >> 3);
1547	info->var.yres_virtual = info->fix.smem_len / lpitch;
1548	if (info->var.yres_virtual < info->var.yres)
1549		goto out_err_iobase;
1550
1551	if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
1552		printk(KERN_ERR "tdfxfb: Can't allocate color map\n");
1553		goto out_err_iobase;
1554	}
1555
1556	if (register_framebuffer(info) < 0) {
1557		printk(KERN_ERR "tdfxfb: can't register framebuffer\n");
1558		fb_dealloc_cmap(&info->cmap);
1559		goto out_err_iobase;
1560	}
1561	/*
1562	 * Our driver data
1563	 */
1564	pci_set_drvdata(pdev, info);
1565	return 0;
1566
1567out_err_iobase:
1568#ifdef CONFIG_FB_3DFX_I2C
1569	tdfxfb_delete_i2c_busses(default_par);
1570#endif
1571	if (default_par->mtrr_handle >= 0)
1572		mtrr_del(default_par->mtrr_handle, info->fix.smem_start,
1573			 info->fix.smem_len);
1574	release_region(pci_resource_start(pdev, 2),
1575		       pci_resource_len(pdev, 2));
1576out_err_screenbase:
1577	if (info->screen_base)
1578		iounmap(info->screen_base);
1579	release_mem_region(info->fix.smem_start, pci_resource_len(pdev, 1));
1580out_err_regbase:
1581	/*
1582	 * Cleanup after anything that was remapped/allocated.
1583	 */
1584	if (default_par->regbase_virt)
1585		iounmap(default_par->regbase_virt);
1586	release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
1587out_err:
1588	framebuffer_release(info);
1589	return -ENXIO;
1590}
1591
1592#ifndef MODULE
1593static void __init tdfxfb_setup(char *options)
1594{
1595	char *this_opt;
1596
1597	if (!options || !*options)
1598		return;
1599
1600	while ((this_opt = strsep(&options, ",")) != NULL) {
1601		if (!*this_opt)
1602			continue;
1603		if (!strcmp(this_opt, "nopan")) {
1604			nopan = 1;
1605		} else if (!strcmp(this_opt, "nowrap")) {
1606			nowrap = 1;
1607		} else if (!strncmp(this_opt, "hwcursor=", 9)) {
1608			hwcursor = simple_strtoul(this_opt + 9, NULL, 0);
1609#ifdef CONFIG_MTRR
1610		} else if (!strncmp(this_opt, "nomtrr", 6)) {
1611			nomtrr = 1;
1612#endif
1613		} else {
1614			mode_option = this_opt;
1615		}
1616	}
1617}
1618#endif
1619
1620/**
1621 *      tdfxfb_remove - Device removal
1622 *
1623 *      @pdev:  PCI Device to cleanup
1624 *
1625 *      Releases all resources allocated during the course of the driver's
1626 *      lifetime for the PCI device @pdev.
1627 *
1628 */
1629static void __devexit tdfxfb_remove(struct pci_dev *pdev)
1630{
1631	struct fb_info *info = pci_get_drvdata(pdev);
1632	struct tdfx_par *par = info->par;
1633
1634	unregister_framebuffer(info);
1635#ifdef CONFIG_FB_3DFX_I2C
1636	tdfxfb_delete_i2c_busses(par);
1637#endif
1638	if (par->mtrr_handle >= 0)
1639		mtrr_del(par->mtrr_handle, info->fix.smem_start,
1640			 info->fix.smem_len);
1641	iounmap(par->regbase_virt);
1642	iounmap(info->screen_base);
1643
1644	/* Clean up after reserved regions */
1645	release_region(pci_resource_start(pdev, 2),
1646		       pci_resource_len(pdev, 2));
1647	release_mem_region(pci_resource_start(pdev, 1),
1648			   pci_resource_len(pdev, 1));
1649	release_mem_region(pci_resource_start(pdev, 0),
1650			   pci_resource_len(pdev, 0));
1651	pci_set_drvdata(pdev, NULL);
1652	fb_dealloc_cmap(&info->cmap);
1653	framebuffer_release(info);
1654}
1655
1656static int __init tdfxfb_init(void)
1657{
1658#ifndef MODULE
1659	char *option = NULL;
1660
1661	if (fb_get_options("tdfxfb", &option))
1662		return -ENODEV;
1663
1664	tdfxfb_setup(option);
1665#endif
1666	return pci_register_driver(&tdfxfb_driver);
1667}
1668
1669static void __exit tdfxfb_exit(void)
1670{
1671	pci_unregister_driver(&tdfxfb_driver);
1672}
1673
1674MODULE_AUTHOR("Hannu Mallat <hmallat@cc.hut.fi>");
1675MODULE_DESCRIPTION("3Dfx framebuffer device driver");
1676MODULE_LICENSE("GPL");
1677
1678module_param(hwcursor, int, 0644);
1679MODULE_PARM_DESC(hwcursor, "Enable hardware cursor "
1680			"(1=enable, 0=disable, default=1)");
1681module_param(mode_option, charp, 0);
1682MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
1683#ifdef CONFIG_MTRR
1684module_param(nomtrr, bool, 0);
1685MODULE_PARM_DESC(nomtrr, "Disable MTRR support (default: enabled)");
1686#endif
1687
1688module_init(tdfxfb_init);
1689module_exit(tdfxfb_exit);