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/drivers/video/msm/mddi_hw.h

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t
C Header | 305 lines | 200 code | 38 blank | 67 comment | 0 complexity | 1ef5a1817eae465a67bb7239428756fd MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
  1/* drivers/video/msm_fb/mddi_hw.h
  2 *
  3 * MSM MDDI Hardware Registers and Structures
  4 *
  5 * Copyright (C) 2007 QUALCOMM Incorporated
  6 * Copyright (C) 2007 Google Incorporated
  7 *
  8 * This software is licensed under the terms of the GNU General Public
  9 * License version 2, as published by the Free Software Foundation, and
 10 * may be copied, distributed, and modified under those terms.
 11 *
 12 * This program is distributed in the hope that it will be useful,
 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 15 * GNU General Public License for more details.
 16 */
 17
 18#ifndef _MDDI_HW_H_
 19#define _MDDI_HW_H_
 20
 21#include <linux/types.h>
 22
 23#define MDDI_CMD                0x0000
 24#define MDDI_VERSION            0x0004
 25#define MDDI_PRI_PTR            0x0008
 26#define MDDI_SEC_PTR            0x000c
 27#define MDDI_BPS                0x0010
 28#define MDDI_SPM                0x0014
 29#define MDDI_INT                0x0018
 30#define MDDI_INTEN              0x001c
 31#define MDDI_REV_PTR            0x0020
 32#define MDDI_REV_SIZE           0x0024
 33#define MDDI_STAT               0x0028
 34#define MDDI_REV_RATE_DIV       0x002c
 35#define MDDI_REV_CRC_ERR        0x0030
 36#define MDDI_TA1_LEN            0x0034
 37#define MDDI_TA2_LEN            0x0038
 38#define MDDI_TEST_BUS           0x003c
 39#define MDDI_TEST               0x0040
 40#define MDDI_REV_PKT_CNT        0x0044
 41#define MDDI_DRIVE_HI           0x0048
 42#define MDDI_DRIVE_LO           0x004c
 43#define MDDI_DISP_WAKE          0x0050
 44#define MDDI_REV_ENCAP_SZ       0x0054
 45#define MDDI_RTD_VAL            0x0058
 46#define MDDI_PAD_CTL            0x0068
 47#define MDDI_DRIVER_START_CNT   0x006c
 48#define MDDI_NEXT_PRI_PTR       0x0070
 49#define MDDI_NEXT_SEC_PTR       0x0074
 50#define MDDI_MISR_CTL           0x0078
 51#define MDDI_MISR_DATA          0x007c
 52#define MDDI_SF_CNT             0x0080
 53#define MDDI_MF_CNT             0x0084
 54#define MDDI_CURR_REV_PTR       0x0088
 55#define MDDI_CORE_VER           0x008c
 56
 57#define MDDI_INT_PRI_PTR_READ       0x0001
 58#define MDDI_INT_SEC_PTR_READ       0x0002
 59#define MDDI_INT_REV_DATA_AVAIL     0x0004
 60#define MDDI_INT_DISP_REQ           0x0008
 61#define MDDI_INT_PRI_UNDERFLOW      0x0010
 62#define MDDI_INT_SEC_UNDERFLOW      0x0020
 63#define MDDI_INT_REV_OVERFLOW       0x0040
 64#define MDDI_INT_CRC_ERROR          0x0080
 65#define MDDI_INT_MDDI_IN            0x0100
 66#define MDDI_INT_PRI_OVERWRITE      0x0200
 67#define MDDI_INT_SEC_OVERWRITE      0x0400
 68#define MDDI_INT_REV_OVERWRITE      0x0800
 69#define MDDI_INT_DMA_FAILURE        0x1000
 70#define MDDI_INT_LINK_ACTIVE        0x2000
 71#define MDDI_INT_IN_HIBERNATION     0x4000
 72#define MDDI_INT_PRI_LINK_LIST_DONE 0x8000
 73#define MDDI_INT_SEC_LINK_LIST_DONE 0x10000
 74#define MDDI_INT_NO_CMD_PKTS_PEND   0x20000
 75#define MDDI_INT_RTD_FAILURE        0x40000
 76#define MDDI_INT_REV_PKT_RECEIVED   0x80000
 77#define MDDI_INT_REV_PKTS_AVAIL     0x100000
 78
 79#define MDDI_INT_NEED_CLEAR ( \
 80	MDDI_INT_REV_DATA_AVAIL | \
 81	MDDI_INT_PRI_UNDERFLOW | \
 82	MDDI_INT_SEC_UNDERFLOW | \
 83	MDDI_INT_REV_OVERFLOW | \
 84	MDDI_INT_CRC_ERROR | \
 85	MDDI_INT_REV_PKT_RECEIVED)
 86
 87
 88#define MDDI_STAT_LINK_ACTIVE        0x0001
 89#define MDDI_STAT_NEW_REV_PTR        0x0002
 90#define MDDI_STAT_NEW_PRI_PTR        0x0004
 91#define MDDI_STAT_NEW_SEC_PTR        0x0008
 92#define MDDI_STAT_IN_HIBERNATION     0x0010
 93#define MDDI_STAT_PRI_LINK_LIST_DONE 0x0020
 94#define MDDI_STAT_SEC_LINK_LIST_DONE 0x0040
 95#define MDDI_STAT_PENDING_TIMING_PKT 0x0080
 96#define MDDI_STAT_PENDING_REV_ENCAP  0x0100
 97#define MDDI_STAT_PENDING_POWERDOWN  0x0200
 98#define MDDI_STAT_RTD_MEAS_FAIL      0x0800
 99#define MDDI_STAT_CLIENT_WAKEUP_REQ  0x1000
100
101
102#define MDDI_CMD_POWERDOWN           0x0100
103#define MDDI_CMD_POWERUP             0x0200
104#define MDDI_CMD_HIBERNATE           0x0300
105#define MDDI_CMD_RESET               0x0400
106#define MDDI_CMD_DISP_IGNORE         0x0501
107#define MDDI_CMD_DISP_LISTEN         0x0500
108#define MDDI_CMD_SEND_REV_ENCAP      0x0600
109#define MDDI_CMD_GET_CLIENT_CAP      0x0601
110#define MDDI_CMD_GET_CLIENT_STATUS   0x0602
111#define MDDI_CMD_SEND_RTD            0x0700
112#define MDDI_CMD_LINK_ACTIVE         0x0900
113#define MDDI_CMD_PERIODIC_REV_ENCAP  0x0A00
114#define MDDI_CMD_FORCE_NEW_REV_PTR   0x0C00
115
116
117
118#define MDDI_VIDEO_REV_PKT_SIZE              0x40
119#define MDDI_CLIENT_CAPABILITY_REV_PKT_SIZE  0x60
120#define MDDI_MAX_REV_PKT_SIZE                0x60
121
122/* #define MDDI_REV_BUFFER_SIZE 128 */
123#define MDDI_REV_BUFFER_SIZE (MDDI_MAX_REV_PKT_SIZE * 4)
124
125/* MDP sends 256 pixel packets, so lower value hibernates more without
126 * significantly increasing latency of waiting for next subframe */
127#define MDDI_HOST_BYTES_PER_SUBFRAME  0x3C00
128#define MDDI_HOST_TA2_LEN       0x000c
129#define MDDI_HOST_REV_RATE_DIV  0x0002
130
131
132struct __attribute__((packed)) mddi_rev_packet {
133	uint16_t length;
134	uint16_t type;
135	uint16_t client_id;
136};
137
138struct __attribute__((packed)) mddi_client_status {
139	uint16_t length;
140	uint16_t type;
141	uint16_t client_id;
142	uint16_t reverse_link_request;  /* bytes needed in rev encap message */
143	uint8_t  crc_error_count;
144	uint8_t  capability_change;
145	uint16_t graphics_busy_flags;
146	uint16_t crc16;
147};
148
149struct __attribute__((packed)) mddi_client_caps {
150	uint16_t length; /* length, exclusive of this field */
151	uint16_t type; /* 66 */
152	uint16_t client_id;
153
154	uint16_t Protocol_Version;
155	uint16_t Minimum_Protocol_Version;
156	uint16_t Data_Rate_Capability;
157	uint8_t  Interface_Type_Capability;
158	uint8_t  Number_of_Alt_Displays;
159	uint16_t PostCal_Data_Rate;
160	uint16_t Bitmap_Width;
161	uint16_t Bitmap_Height;
162	uint16_t Display_Window_Width;
163	uint16_t Display_Window_Height;
164	uint32_t Color_Map_Size;
165	uint16_t Color_Map_RGB_Width;
166	uint16_t RGB_Capability;
167	uint8_t  Monochrome_Capability;
168	uint8_t  Reserved_1;
169	uint16_t Y_Cb_Cr_Capability;
170	uint16_t Bayer_Capability;
171	uint16_t Alpha_Cursor_Image_Planes;
172	uint32_t Client_Feature_Capability_Indicators;
173	uint8_t  Maximum_Video_Frame_Rate_Capability;
174	uint8_t  Minimum_Video_Frame_Rate_Capability;
175	uint16_t Minimum_Sub_frame_Rate;
176	uint16_t Audio_Buffer_Depth;
177	uint16_t Audio_Channel_Capability;
178	uint16_t Audio_Sample_Rate_Capability;
179	uint8_t  Audio_Sample_Resolution;
180	uint8_t  Mic_Audio_Sample_Resolution;
181	uint16_t Mic_Sample_Rate_Capability;
182	uint8_t  Keyboard_Data_Format;
183	uint8_t  pointing_device_data_format;
184	uint16_t content_protection_type;
185	uint16_t Mfr_Name;
186	uint16_t Product_Code;
187	uint16_t Reserved_3;
188	uint32_t Serial_Number;
189	uint8_t  Week_of_Manufacture;
190	uint8_t  Year_of_Manufacture;
191
192	uint16_t crc16;
193} mddi_client_capability_type;
194
195
196struct __attribute__((packed)) mddi_video_stream {
197	uint16_t length;
198	uint16_t type; /* 16 */
199	uint16_t client_id; /* 0 */
200
201	uint16_t video_data_format_descriptor;
202/* format of each pixel in the Pixel Data in the present stream in the
203 * present packet.
204 * If bits [15:13] = 000 monochrome
205 * If bits [15:13] = 001 color pixels (palette).
206 * If bits [15:13] = 010 color pixels in raw RGB
207 * If bits [15:13] = 011 data in 4:2:2 Y Cb Cr format
208 * If bits [15:13] = 100 Bayer pixels
209 */
210
211	uint16_t pixel_data_attributes;
212/* interpreted as follows:
213 * Bits [1:0] = 11  pixel data is displayed to both eyes
214 * Bits [1:0] = 10  pixel data is routed to the left eye only.
215 * Bits [1:0] = 01  pixel data is routed to the right eye only.
216 * Bits [1:0] = 00  pixel data is routed to the alternate display.
217 * Bit 2 is 0  Pixel Data is in the standard progressive format.
218 * Bit 2 is 1  Pixel Data is in interlace format.
219 * Bit 3 is 0  Pixel Data is in the standard progressive format.
220 * Bit 3 is 1  Pixel Data is in alternate pixel format.
221 * Bit 4 is 0  Pixel Data is to or from the display frame buffer.
222 * Bit 4 is 1  Pixel Data is to or from the camera.
223 * Bit 5 is 0  pixel data contains the next consecutive row of pixels.
224 * Bit 5 is 1  X Left Edge, Y Top Edge, X Right Edge, Y Bottom Edge,
225 *             X Start, and Y Start parameters are not defined and
226 *             shall be ignored by the client.
227 * Bits [7:6] = 01  Pixel data is written to the offline image buffer.
228 * Bits [7:6] = 00  Pixel data is written to the buffer to refresh display.
229 * Bits [7:6] = 11  Pixel data is written to all image buffers.
230 * Bits [7:6] = 10  Invalid. Reserved for future use.
231 * Bits 8 through 11 alternate display number.
232 * Bits 12 through 14 are reserved for future use and shall be set to zero.
233 * Bit 15 is 1 the row of pixels is the last row of pixels in a frame.
234 */
235
236	uint16_t x_left_edge;
237	uint16_t y_top_edge;
238	/* X,Y coordinate of the top left edge of the screen window */
239
240	uint16_t x_right_edge;
241	uint16_t y_bottom_edge;
242	/* X,Y coordinate of the bottom right edge of the window being
243	 * updated. */
244
245	uint16_t x_start;
246	uint16_t y_start;
247	/* (X Start, Y Start) is the first pixel in the Pixel Data field
248	 * below. */
249
250	uint16_t pixel_count;
251	/* number of pixels in the Pixel Data field below. */
252
253	uint16_t parameter_CRC;
254	/* 16-bit CRC of all bytes from the Packet Length to the Pixel Count. */
255
256	uint16_t reserved;
257	/* 16-bit variable to make structure align on 4 byte boundary */
258};
259
260#define TYPE_VIDEO_STREAM      16
261#define TYPE_CLIENT_CAPS       66
262#define TYPE_REGISTER_ACCESS   146
263#define TYPE_CLIENT_STATUS     70
264
265struct __attribute__((packed)) mddi_register_access {
266	uint16_t length;
267	uint16_t type; /* 146 */
268	uint16_t client_id;
269
270	uint16_t read_write_info;
271	/* Bits 13:0  a 14-bit unsigned integer that specifies the number of
272	 *            32-bit Register Data List items to be transferred in the
273	 *            Register Data List field.
274	 * Bits[15:14] = 00  Write to register(s);
275	 * Bits[15:14] = 10  Read from register(s);
276	 * Bits[15:14] = 11  Response to a Read.
277	 * Bits[15:14] = 01  this value is reserved for future use. */
278#define MDDI_WRITE     (0 << 14)
279#define MDDI_READ      (2 << 14)
280#define MDDI_READ_RESP (3 << 14)
281
282	uint32_t register_address;
283	/* the register address that is to be written to or read from. */
284
285	uint16_t crc16;
286
287	uint32_t register_data_list;
288	/* list of 4-byte register data values for/from client registers */
289};
290
291struct __attribute__((packed)) mddi_llentry {
292	uint16_t flags;
293	uint16_t header_count;
294	uint16_t data_count;
295	dma_addr_t data; /* 32 bit */
296	struct mddi_llentry *next;
297	uint16_t reserved;
298	union {
299		struct mddi_video_stream v;
300		struct mddi_register_access r;
301		uint32_t _[12];
302	} u;
303};
304
305#endif