/drivers/usb/host/uhci-hcd.c
C | 928 lines | 569 code | 136 blank | 223 comment | 84 complexity | fbdcd63ff31474c5b3c56eb12606e9b1 MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
1/* 2 * Universal Host Controller Interface driver for USB. 3 * 4 * Maintainer: Alan Stern <stern@rowland.harvard.edu> 5 * 6 * (C) Copyright 1999 Linus Torvalds 7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com 8 * (C) Copyright 1999 Randy Dunlap 9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de 10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de 11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch 12 * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at 13 * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface 14 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com). 15 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c) 16 * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu 17 * 18 * Intel documents this fairly well, and as far as I know there 19 * are no royalties or anything like that, but even so there are 20 * people who decided that they want to do the same thing in a 21 * completely different way. 22 * 23 */ 24 25#include <linux/module.h> 26#include <linux/pci.h> 27#include <linux/kernel.h> 28#include <linux/init.h> 29#include <linux/delay.h> 30#include <linux/ioport.h> 31#include <linux/slab.h> 32#include <linux/errno.h> 33#include <linux/unistd.h> 34#include <linux/interrupt.h> 35#include <linux/spinlock.h> 36#include <linux/debugfs.h> 37#include <linux/pm.h> 38#include <linux/dmapool.h> 39#include <linux/dma-mapping.h> 40#include <linux/usb.h> 41#include <linux/usb/hcd.h> 42#include <linux/bitops.h> 43#include <linux/dmi.h> 44 45#include <asm/uaccess.h> 46#include <asm/io.h> 47#include <asm/irq.h> 48#include <asm/system.h> 49 50#include "uhci-hcd.h" 51 52/* 53 * Version Information 54 */ 55#define DRIVER_AUTHOR \ 56 "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, " \ 57 "Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, " \ 58 "Roman Weissgaerber, Alan Stern" 59#define DRIVER_DESC "USB Universal Host Controller Interface driver" 60 61/* for flakey hardware, ignore overcurrent indicators */ 62static int ignore_oc; 63module_param(ignore_oc, bool, S_IRUGO); 64MODULE_PARM_DESC(ignore_oc, "ignore hardware overcurrent indications"); 65 66/* 67 * debug = 0, no debugging messages 68 * debug = 1, dump failed URBs except for stalls 69 * debug = 2, dump all failed URBs (including stalls) 70 * show all queues in /sys/kernel/debug/uhci/[pci_addr] 71 * debug = 3, show all TDs in URBs when dumping 72 */ 73#ifdef DEBUG 74#define DEBUG_CONFIGURED 1 75static int debug = 1; 76module_param(debug, int, S_IRUGO | S_IWUSR); 77MODULE_PARM_DESC(debug, "Debug level"); 78 79#else 80#define DEBUG_CONFIGURED 0 81#define debug 0 82#endif 83 84static char *errbuf; 85#define ERRBUF_LEN (32 * 1024) 86 87static struct kmem_cache *uhci_up_cachep; /* urb_priv */ 88 89static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state); 90static void wakeup_rh(struct uhci_hcd *uhci); 91static void uhci_get_current_frame_number(struct uhci_hcd *uhci); 92 93/* 94 * Calculate the link pointer DMA value for the first Skeleton QH in a frame. 95 */ 96static __hc32 uhci_frame_skel_link(struct uhci_hcd *uhci, int frame) 97{ 98 int skelnum; 99 100 /* 101 * The interrupt queues will be interleaved as evenly as possible. 102 * There's not much to be done about period-1 interrupts; they have 103 * to occur in every frame. But we can schedule period-2 interrupts 104 * in odd-numbered frames, period-4 interrupts in frames congruent 105 * to 2 (mod 4), and so on. This way each frame only has two 106 * interrupt QHs, which will help spread out bandwidth utilization. 107 * 108 * ffs (Find First bit Set) does exactly what we need: 109 * 1,3,5,... => ffs = 0 => use period-2 QH = skelqh[8], 110 * 2,6,10,... => ffs = 1 => use period-4 QH = skelqh[7], etc. 111 * ffs >= 7 => not on any high-period queue, so use 112 * period-1 QH = skelqh[9]. 113 * Add in UHCI_NUMFRAMES to insure at least one bit is set. 114 */ 115 skelnum = 8 - (int) __ffs(frame | UHCI_NUMFRAMES); 116 if (skelnum <= 1) 117 skelnum = 9; 118 return LINK_TO_QH(uhci, uhci->skelqh[skelnum]); 119} 120 121#include "uhci-debug.c" 122#include "uhci-q.c" 123#include "uhci-hub.c" 124 125/* 126 * Finish up a host controller reset and update the recorded state. 127 */ 128static void finish_reset(struct uhci_hcd *uhci) 129{ 130 int port; 131 132 /* HCRESET doesn't affect the Suspend, Reset, and Resume Detect 133 * bits in the port status and control registers. 134 * We have to clear them by hand. 135 */ 136 for (port = 0; port < uhci->rh_numports; ++port) 137 uhci_writew(uhci, 0, USBPORTSC1 + (port * 2)); 138 139 uhci->port_c_suspend = uhci->resuming_ports = 0; 140 uhci->rh_state = UHCI_RH_RESET; 141 uhci->is_stopped = UHCI_IS_STOPPED; 142 clear_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); 143} 144 145/* 146 * Last rites for a defunct/nonfunctional controller 147 * or one we don't want to use any more. 148 */ 149static void uhci_hc_died(struct uhci_hcd *uhci) 150{ 151 uhci_get_current_frame_number(uhci); 152 uhci->reset_hc(uhci); 153 finish_reset(uhci); 154 uhci->dead = 1; 155 156 /* The current frame may already be partway finished */ 157 ++uhci->frame_number; 158} 159 160/* 161 * Initialize a controller that was newly discovered or has lost power 162 * or otherwise been reset while it was suspended. In none of these cases 163 * can we be sure of its previous state. 164 */ 165static void check_and_reset_hc(struct uhci_hcd *uhci) 166{ 167 if (uhci->check_and_reset_hc(uhci)) 168 finish_reset(uhci); 169} 170 171#if defined(CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC) 172/* 173 * The two functions below are generic reset functions that are used on systems 174 * that do not have keyboard and mouse legacy support. We assume that we are 175 * running on such a system if CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC is defined. 176 */ 177 178/* 179 * Make sure the controller is completely inactive, unable to 180 * generate interrupts or do DMA. 181 */ 182static void uhci_generic_reset_hc(struct uhci_hcd *uhci) 183{ 184 /* Reset the HC - this will force us to get a 185 * new notification of any already connected 186 * ports due to the virtual disconnect that it 187 * implies. 188 */ 189 uhci_writew(uhci, USBCMD_HCRESET, USBCMD); 190 mb(); 191 udelay(5); 192 if (uhci_readw(uhci, USBCMD) & USBCMD_HCRESET) 193 dev_warn(uhci_dev(uhci), "HCRESET not completed yet!\n"); 194 195 /* Just to be safe, disable interrupt requests and 196 * make sure the controller is stopped. 197 */ 198 uhci_writew(uhci, 0, USBINTR); 199 uhci_writew(uhci, 0, USBCMD); 200} 201 202/* 203 * Initialize a controller that was newly discovered or has just been 204 * resumed. In either case we can't be sure of its previous state. 205 * 206 * Returns: 1 if the controller was reset, 0 otherwise. 207 */ 208static int uhci_generic_check_and_reset_hc(struct uhci_hcd *uhci) 209{ 210 unsigned int cmd, intr; 211 212 /* 213 * When restarting a suspended controller, we expect all the 214 * settings to be the same as we left them: 215 * 216 * Controller is stopped and configured with EGSM set; 217 * No interrupts enabled except possibly Resume Detect. 218 * 219 * If any of these conditions are violated we do a complete reset. 220 */ 221 222 cmd = uhci_readw(uhci, USBCMD); 223 if ((cmd & USBCMD_RS) || !(cmd & USBCMD_CF) || !(cmd & USBCMD_EGSM)) { 224 dev_dbg(uhci_dev(uhci), "%s: cmd = 0x%04x\n", 225 __func__, cmd); 226 goto reset_needed; 227 } 228 229 intr = uhci_readw(uhci, USBINTR); 230 if (intr & (~USBINTR_RESUME)) { 231 dev_dbg(uhci_dev(uhci), "%s: intr = 0x%04x\n", 232 __func__, intr); 233 goto reset_needed; 234 } 235 return 0; 236 237reset_needed: 238 dev_dbg(uhci_dev(uhci), "Performing full reset\n"); 239 uhci_generic_reset_hc(uhci); 240 return 1; 241} 242#endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */ 243 244/* 245 * Store the basic register settings needed by the controller. 246 */ 247static void configure_hc(struct uhci_hcd *uhci) 248{ 249 /* Set the frame length to the default: 1 ms exactly */ 250 uhci_writeb(uhci, USBSOF_DEFAULT, USBSOF); 251 252 /* Store the frame list base address */ 253 uhci_writel(uhci, uhci->frame_dma_handle, USBFLBASEADD); 254 255 /* Set the current frame number */ 256 uhci_writew(uhci, uhci->frame_number & UHCI_MAX_SOF_NUMBER, 257 USBFRNUM); 258 259 /* perform any arch/bus specific configuration */ 260 if (uhci->configure_hc) 261 uhci->configure_hc(uhci); 262} 263 264static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci) 265{ 266 /* If we have to ignore overcurrent events then almost by definition 267 * we can't depend on resume-detect interrupts. */ 268 if (ignore_oc) 269 return 1; 270 271 return uhci->resume_detect_interrupts_are_broken ? 272 uhci->resume_detect_interrupts_are_broken(uhci) : 0; 273} 274 275static int global_suspend_mode_is_broken(struct uhci_hcd *uhci) 276{ 277 return uhci->global_suspend_mode_is_broken ? 278 uhci->global_suspend_mode_is_broken(uhci) : 0; 279} 280 281static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state) 282__releases(uhci->lock) 283__acquires(uhci->lock) 284{ 285 int auto_stop; 286 int int_enable, egsm_enable, wakeup_enable; 287 struct usb_device *rhdev = uhci_to_hcd(uhci)->self.root_hub; 288 289 auto_stop = (new_state == UHCI_RH_AUTO_STOPPED); 290 dev_dbg(&rhdev->dev, "%s%s\n", __func__, 291 (auto_stop ? " (auto-stop)" : "")); 292 293 /* Start off by assuming Resume-Detect interrupts and EGSM work 294 * and that remote wakeups should be enabled. 295 */ 296 egsm_enable = USBCMD_EGSM; 297 uhci->RD_enable = 1; 298 int_enable = USBINTR_RESUME; 299 wakeup_enable = 1; 300 301 /* In auto-stop mode wakeups must always be detected, but 302 * Resume-Detect interrupts may be prohibited. (In the absence 303 * of CONFIG_PM, they are always disallowed.) 304 */ 305 if (auto_stop) { 306 if (!device_may_wakeup(&rhdev->dev)) 307 int_enable = 0; 308 309 /* In bus-suspend mode wakeups may be disabled, but if they are 310 * allowed then so are Resume-Detect interrupts. 311 */ 312 } else { 313#ifdef CONFIG_PM 314 if (!rhdev->do_remote_wakeup) 315 wakeup_enable = 0; 316#endif 317 } 318 319 /* EGSM causes the root hub to echo a 'K' signal (resume) out any 320 * port which requests a remote wakeup. According to the USB spec, 321 * every hub is supposed to do this. But if we are ignoring 322 * remote-wakeup requests anyway then there's no point to it. 323 * We also shouldn't enable EGSM if it's broken. 324 */ 325 if (!wakeup_enable || global_suspend_mode_is_broken(uhci)) 326 egsm_enable = 0; 327 328 /* If we're ignoring wakeup events then there's no reason to 329 * enable Resume-Detect interrupts. We also shouldn't enable 330 * them if they are broken or disallowed. 331 * 332 * This logic may lead us to enabling RD but not EGSM. The UHCI 333 * spec foolishly says that RD works only when EGSM is on, but 334 * there's no harm in enabling it anyway -- perhaps some chips 335 * will implement it! 336 */ 337 if (!wakeup_enable || resume_detect_interrupts_are_broken(uhci) || 338 !int_enable) 339 uhci->RD_enable = int_enable = 0; 340 341 uhci_writew(uhci, int_enable, USBINTR); 342 uhci_writew(uhci, egsm_enable | USBCMD_CF, USBCMD); 343 mb(); 344 udelay(5); 345 346 /* If we're auto-stopping then no devices have been attached 347 * for a while, so there shouldn't be any active URBs and the 348 * controller should stop after a few microseconds. Otherwise 349 * we will give the controller one frame to stop. 350 */ 351 if (!auto_stop && !(uhci_readw(uhci, USBSTS) & USBSTS_HCH)) { 352 uhci->rh_state = UHCI_RH_SUSPENDING; 353 spin_unlock_irq(&uhci->lock); 354 msleep(1); 355 spin_lock_irq(&uhci->lock); 356 if (uhci->dead) 357 return; 358 } 359 if (!(uhci_readw(uhci, USBSTS) & USBSTS_HCH)) 360 dev_warn(uhci_dev(uhci), "Controller not stopped yet!\n"); 361 362 uhci_get_current_frame_number(uhci); 363 364 uhci->rh_state = new_state; 365 uhci->is_stopped = UHCI_IS_STOPPED; 366 367 /* If interrupts don't work and remote wakeup is enabled then 368 * the suspended root hub needs to be polled. 369 */ 370 if (!int_enable && wakeup_enable) 371 set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); 372 else 373 clear_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); 374 375 uhci_scan_schedule(uhci); 376 uhci_fsbr_off(uhci); 377} 378 379static void start_rh(struct uhci_hcd *uhci) 380{ 381 uhci->is_stopped = 0; 382 383 /* Mark it configured and running with a 64-byte max packet. 384 * All interrupts are enabled, even though RESUME won't do anything. 385 */ 386 uhci_writew(uhci, USBCMD_RS | USBCMD_CF | USBCMD_MAXP, USBCMD); 387 uhci_writew(uhci, USBINTR_TIMEOUT | USBINTR_RESUME | 388 USBINTR_IOC | USBINTR_SP, USBINTR); 389 mb(); 390 uhci->rh_state = UHCI_RH_RUNNING; 391 set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); 392} 393 394static void wakeup_rh(struct uhci_hcd *uhci) 395__releases(uhci->lock) 396__acquires(uhci->lock) 397{ 398 dev_dbg(&uhci_to_hcd(uhci)->self.root_hub->dev, 399 "%s%s\n", __func__, 400 uhci->rh_state == UHCI_RH_AUTO_STOPPED ? 401 " (auto-start)" : ""); 402 403 /* If we are auto-stopped then no devices are attached so there's 404 * no need for wakeup signals. Otherwise we send Global Resume 405 * for 20 ms. 406 */ 407 if (uhci->rh_state == UHCI_RH_SUSPENDED) { 408 unsigned egsm; 409 410 /* Keep EGSM on if it was set before */ 411 egsm = uhci_readw(uhci, USBCMD) & USBCMD_EGSM; 412 uhci->rh_state = UHCI_RH_RESUMING; 413 uhci_writew(uhci, USBCMD_FGR | USBCMD_CF | egsm, USBCMD); 414 spin_unlock_irq(&uhci->lock); 415 msleep(20); 416 spin_lock_irq(&uhci->lock); 417 if (uhci->dead) 418 return; 419 420 /* End Global Resume and wait for EOP to be sent */ 421 uhci_writew(uhci, USBCMD_CF, USBCMD); 422 mb(); 423 udelay(4); 424 if (uhci_readw(uhci, USBCMD) & USBCMD_FGR) 425 dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n"); 426 } 427 428 start_rh(uhci); 429 430 /* Restart root hub polling */ 431 mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies); 432} 433 434static irqreturn_t uhci_irq(struct usb_hcd *hcd) 435{ 436 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 437 unsigned short status; 438 439 /* 440 * Read the interrupt status, and write it back to clear the 441 * interrupt cause. Contrary to the UHCI specification, the 442 * "HC Halted" status bit is persistent: it is RO, not R/WC. 443 */ 444 status = uhci_readw(uhci, USBSTS); 445 if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */ 446 return IRQ_NONE; 447 uhci_writew(uhci, status, USBSTS); /* Clear it */ 448 449 if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) { 450 if (status & USBSTS_HSE) 451 dev_err(uhci_dev(uhci), "host system error, " 452 "PCI problems?\n"); 453 if (status & USBSTS_HCPE) 454 dev_err(uhci_dev(uhci), "host controller process " 455 "error, something bad happened!\n"); 456 if (status & USBSTS_HCH) { 457 spin_lock(&uhci->lock); 458 if (uhci->rh_state >= UHCI_RH_RUNNING) { 459 dev_err(uhci_dev(uhci), 460 "host controller halted, " 461 "very bad!\n"); 462 if (debug > 1 && errbuf) { 463 /* Print the schedule for debugging */ 464 uhci_sprint_schedule(uhci, 465 errbuf, ERRBUF_LEN); 466 lprintk(errbuf); 467 } 468 uhci_hc_died(uhci); 469 usb_hc_died(hcd); 470 471 /* Force a callback in case there are 472 * pending unlinks */ 473 mod_timer(&hcd->rh_timer, jiffies); 474 } 475 spin_unlock(&uhci->lock); 476 } 477 } 478 479 if (status & USBSTS_RD) 480 usb_hcd_poll_rh_status(hcd); 481 else { 482 spin_lock(&uhci->lock); 483 uhci_scan_schedule(uhci); 484 spin_unlock(&uhci->lock); 485 } 486 487 return IRQ_HANDLED; 488} 489 490/* 491 * Store the current frame number in uhci->frame_number if the controller 492 * is running. Expand from 11 bits (of which we use only 10) to a 493 * full-sized integer. 494 * 495 * Like many other parts of the driver, this code relies on being polled 496 * more than once per second as long as the controller is running. 497 */ 498static void uhci_get_current_frame_number(struct uhci_hcd *uhci) 499{ 500 if (!uhci->is_stopped) { 501 unsigned delta; 502 503 delta = (uhci_readw(uhci, USBFRNUM) - uhci->frame_number) & 504 (UHCI_NUMFRAMES - 1); 505 uhci->frame_number += delta; 506 } 507} 508 509/* 510 * De-allocate all resources 511 */ 512static void release_uhci(struct uhci_hcd *uhci) 513{ 514 int i; 515 516 if (DEBUG_CONFIGURED) { 517 spin_lock_irq(&uhci->lock); 518 uhci->is_initialized = 0; 519 spin_unlock_irq(&uhci->lock); 520 521 debugfs_remove(uhci->dentry); 522 } 523 524 for (i = 0; i < UHCI_NUM_SKELQH; i++) 525 uhci_free_qh(uhci, uhci->skelqh[i]); 526 527 uhci_free_td(uhci, uhci->term_td); 528 529 dma_pool_destroy(uhci->qh_pool); 530 531 dma_pool_destroy(uhci->td_pool); 532 533 kfree(uhci->frame_cpu); 534 535 dma_free_coherent(uhci_dev(uhci), 536 UHCI_NUMFRAMES * sizeof(*uhci->frame), 537 uhci->frame, uhci->frame_dma_handle); 538} 539 540/* 541 * Allocate a frame list, and then setup the skeleton 542 * 543 * The hardware doesn't really know any difference 544 * in the queues, but the order does matter for the 545 * protocols higher up. The order in which the queues 546 * are encountered by the hardware is: 547 * 548 * - All isochronous events are handled before any 549 * of the queues. We don't do that here, because 550 * we'll create the actual TD entries on demand. 551 * - The first queue is the high-period interrupt queue. 552 * - The second queue is the period-1 interrupt and async 553 * (low-speed control, full-speed control, then bulk) queue. 554 * - The third queue is the terminating bandwidth reclamation queue, 555 * which contains no members, loops back to itself, and is present 556 * only when FSBR is on and there are no full-speed control or bulk QHs. 557 */ 558static int uhci_start(struct usb_hcd *hcd) 559{ 560 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 561 int retval = -EBUSY; 562 int i; 563 struct dentry __maybe_unused *dentry; 564 565 hcd->uses_new_polling = 1; 566 567 spin_lock_init(&uhci->lock); 568 setup_timer(&uhci->fsbr_timer, uhci_fsbr_timeout, 569 (unsigned long) uhci); 570 INIT_LIST_HEAD(&uhci->idle_qh_list); 571 init_waitqueue_head(&uhci->waitqh); 572 573#ifdef UHCI_DEBUG_OPS 574 dentry = debugfs_create_file(hcd->self.bus_name, 575 S_IFREG|S_IRUGO|S_IWUSR, uhci_debugfs_root, 576 uhci, &uhci_debug_operations); 577 if (!dentry) { 578 dev_err(uhci_dev(uhci), "couldn't create uhci debugfs entry\n"); 579 return -ENOMEM; 580 } 581 uhci->dentry = dentry; 582#endif 583 584 uhci->frame = dma_alloc_coherent(uhci_dev(uhci), 585 UHCI_NUMFRAMES * sizeof(*uhci->frame), 586 &uhci->frame_dma_handle, 0); 587 if (!uhci->frame) { 588 dev_err(uhci_dev(uhci), "unable to allocate " 589 "consistent memory for frame list\n"); 590 goto err_alloc_frame; 591 } 592 memset(uhci->frame, 0, UHCI_NUMFRAMES * sizeof(*uhci->frame)); 593 594 uhci->frame_cpu = kcalloc(UHCI_NUMFRAMES, sizeof(*uhci->frame_cpu), 595 GFP_KERNEL); 596 if (!uhci->frame_cpu) { 597 dev_err(uhci_dev(uhci), "unable to allocate " 598 "memory for frame pointers\n"); 599 goto err_alloc_frame_cpu; 600 } 601 602 uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci), 603 sizeof(struct uhci_td), 16, 0); 604 if (!uhci->td_pool) { 605 dev_err(uhci_dev(uhci), "unable to create td dma_pool\n"); 606 goto err_create_td_pool; 607 } 608 609 uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci), 610 sizeof(struct uhci_qh), 16, 0); 611 if (!uhci->qh_pool) { 612 dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n"); 613 goto err_create_qh_pool; 614 } 615 616 uhci->term_td = uhci_alloc_td(uhci); 617 if (!uhci->term_td) { 618 dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n"); 619 goto err_alloc_term_td; 620 } 621 622 for (i = 0; i < UHCI_NUM_SKELQH; i++) { 623 uhci->skelqh[i] = uhci_alloc_qh(uhci, NULL, NULL); 624 if (!uhci->skelqh[i]) { 625 dev_err(uhci_dev(uhci), "unable to allocate QH\n"); 626 goto err_alloc_skelqh; 627 } 628 } 629 630 /* 631 * 8 Interrupt queues; link all higher int queues to int1 = async 632 */ 633 for (i = SKEL_ISO + 1; i < SKEL_ASYNC; ++i) 634 uhci->skelqh[i]->link = LINK_TO_QH(uhci, uhci->skel_async_qh); 635 uhci->skel_async_qh->link = UHCI_PTR_TERM(uhci); 636 uhci->skel_term_qh->link = LINK_TO_QH(uhci, uhci->skel_term_qh); 637 638 /* This dummy TD is to work around a bug in Intel PIIX controllers */ 639 uhci_fill_td(uhci, uhci->term_td, 0, uhci_explen(0) | 640 (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0); 641 uhci->term_td->link = UHCI_PTR_TERM(uhci); 642 uhci->skel_async_qh->element = uhci->skel_term_qh->element = 643 LINK_TO_TD(uhci, uhci->term_td); 644 645 /* 646 * Fill the frame list: make all entries point to the proper 647 * interrupt queue. 648 */ 649 for (i = 0; i < UHCI_NUMFRAMES; i++) { 650 651 /* Only place we don't use the frame list routines */ 652 uhci->frame[i] = uhci_frame_skel_link(uhci, i); 653 } 654 655 /* 656 * Some architectures require a full mb() to enforce completion of 657 * the memory writes above before the I/O transfers in configure_hc(). 658 */ 659 mb(); 660 661 configure_hc(uhci); 662 uhci->is_initialized = 1; 663 spin_lock_irq(&uhci->lock); 664 start_rh(uhci); 665 spin_unlock_irq(&uhci->lock); 666 return 0; 667 668/* 669 * error exits: 670 */ 671err_alloc_skelqh: 672 for (i = 0; i < UHCI_NUM_SKELQH; i++) { 673 if (uhci->skelqh[i]) 674 uhci_free_qh(uhci, uhci->skelqh[i]); 675 } 676 677 uhci_free_td(uhci, uhci->term_td); 678 679err_alloc_term_td: 680 dma_pool_destroy(uhci->qh_pool); 681 682err_create_qh_pool: 683 dma_pool_destroy(uhci->td_pool); 684 685err_create_td_pool: 686 kfree(uhci->frame_cpu); 687 688err_alloc_frame_cpu: 689 dma_free_coherent(uhci_dev(uhci), 690 UHCI_NUMFRAMES * sizeof(*uhci->frame), 691 uhci->frame, uhci->frame_dma_handle); 692 693err_alloc_frame: 694 debugfs_remove(uhci->dentry); 695 696 return retval; 697} 698 699static void uhci_stop(struct usb_hcd *hcd) 700{ 701 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 702 703 spin_lock_irq(&uhci->lock); 704 if (HCD_HW_ACCESSIBLE(hcd) && !uhci->dead) 705 uhci_hc_died(uhci); 706 uhci_scan_schedule(uhci); 707 spin_unlock_irq(&uhci->lock); 708 synchronize_irq(hcd->irq); 709 710 del_timer_sync(&uhci->fsbr_timer); 711 release_uhci(uhci); 712} 713 714#ifdef CONFIG_PM 715static int uhci_rh_suspend(struct usb_hcd *hcd) 716{ 717 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 718 int rc = 0; 719 720 spin_lock_irq(&uhci->lock); 721 if (!HCD_HW_ACCESSIBLE(hcd)) 722 rc = -ESHUTDOWN; 723 else if (uhci->dead) 724 ; /* Dead controllers tell no tales */ 725 726 /* Once the controller is stopped, port resumes that are already 727 * in progress won't complete. Hence if remote wakeup is enabled 728 * for the root hub and any ports are in the middle of a resume or 729 * remote wakeup, we must fail the suspend. 730 */ 731 else if (hcd->self.root_hub->do_remote_wakeup && 732 uhci->resuming_ports) { 733 dev_dbg(uhci_dev(uhci), "suspend failed because a port " 734 "is resuming\n"); 735 rc = -EBUSY; 736 } else 737 suspend_rh(uhci, UHCI_RH_SUSPENDED); 738 spin_unlock_irq(&uhci->lock); 739 return rc; 740} 741 742static int uhci_rh_resume(struct usb_hcd *hcd) 743{ 744 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 745 int rc = 0; 746 747 spin_lock_irq(&uhci->lock); 748 if (!HCD_HW_ACCESSIBLE(hcd)) 749 rc = -ESHUTDOWN; 750 else if (!uhci->dead) 751 wakeup_rh(uhci); 752 spin_unlock_irq(&uhci->lock); 753 return rc; 754} 755 756#endif 757 758/* Wait until a particular device/endpoint's QH is idle, and free it */ 759static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd, 760 struct usb_host_endpoint *hep) 761{ 762 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 763 struct uhci_qh *qh; 764 765 spin_lock_irq(&uhci->lock); 766 qh = (struct uhci_qh *) hep->hcpriv; 767 if (qh == NULL) 768 goto done; 769 770 while (qh->state != QH_STATE_IDLE) { 771 ++uhci->num_waiting; 772 spin_unlock_irq(&uhci->lock); 773 wait_event_interruptible(uhci->waitqh, 774 qh->state == QH_STATE_IDLE); 775 spin_lock_irq(&uhci->lock); 776 --uhci->num_waiting; 777 } 778 779 uhci_free_qh(uhci, qh); 780done: 781 spin_unlock_irq(&uhci->lock); 782} 783 784static int uhci_hcd_get_frame_number(struct usb_hcd *hcd) 785{ 786 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 787 unsigned frame_number; 788 unsigned delta; 789 790 /* Minimize latency by avoiding the spinlock */ 791 frame_number = uhci->frame_number; 792 barrier(); 793 delta = (uhci_readw(uhci, USBFRNUM) - frame_number) & 794 (UHCI_NUMFRAMES - 1); 795 return frame_number + delta; 796} 797 798/* Determines number of ports on controller */ 799static int uhci_count_ports(struct usb_hcd *hcd) 800{ 801 struct uhci_hcd *uhci = hcd_to_uhci(hcd); 802 unsigned io_size = (unsigned) hcd->rsrc_len; 803 int port; 804 805 /* The UHCI spec says devices must have 2 ports, and goes on to say 806 * they may have more but gives no way to determine how many there 807 * are. However according to the UHCI spec, Bit 7 of the port 808 * status and control register is always set to 1. So we try to 809 * use this to our advantage. Another common failure mode when 810 * a nonexistent register is addressed is to return all ones, so 811 * we test for that also. 812 */ 813 for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) { 814 unsigned int portstatus; 815 816 portstatus = uhci_readw(uhci, USBPORTSC1 + (port * 2)); 817 if (!(portstatus & 0x0080) || portstatus == 0xffff) 818 break; 819 } 820 if (debug) 821 dev_info(uhci_dev(uhci), "detected %d ports\n", port); 822 823 /* Anything greater than 7 is weird so we'll ignore it. */ 824 if (port > UHCI_RH_MAXCHILD) { 825 dev_info(uhci_dev(uhci), "port count misdetected? " 826 "forcing to 2 ports\n"); 827 port = 2; 828 } 829 830 return port; 831} 832 833static const char hcd_name[] = "uhci_hcd"; 834 835#ifdef CONFIG_PCI 836#include "uhci-pci.c" 837#define PCI_DRIVER uhci_pci_driver 838#endif 839 840#ifdef CONFIG_SPARC_LEON 841#include "uhci-grlib.c" 842#define PLATFORM_DRIVER uhci_grlib_driver 843#endif 844 845#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) 846#error "missing bus glue for uhci-hcd" 847#endif 848 849static int __init uhci_hcd_init(void) 850{ 851 int retval = -ENOMEM; 852 853 if (usb_disabled()) 854 return -ENODEV; 855 856 printk(KERN_INFO "uhci_hcd: " DRIVER_DESC "%s\n", 857 ignore_oc ? ", overcurrent ignored" : ""); 858 set_bit(USB_UHCI_LOADED, &usb_hcds_loaded); 859 860 if (DEBUG_CONFIGURED) { 861 errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL); 862 if (!errbuf) 863 goto errbuf_failed; 864 uhci_debugfs_root = debugfs_create_dir("uhci", usb_debug_root); 865 if (!uhci_debugfs_root) 866 goto debug_failed; 867 } 868 869 uhci_up_cachep = kmem_cache_create("uhci_urb_priv", 870 sizeof(struct urb_priv), 0, 0, NULL); 871 if (!uhci_up_cachep) 872 goto up_failed; 873 874#ifdef PLATFORM_DRIVER 875 retval = platform_driver_register(&PLATFORM_DRIVER); 876 if (retval < 0) 877 goto clean0; 878#endif 879 880#ifdef PCI_DRIVER 881 retval = pci_register_driver(&PCI_DRIVER); 882 if (retval < 0) 883 goto clean1; 884#endif 885 886 return 0; 887 888#ifdef PCI_DRIVER 889clean1: 890#endif 891#ifdef PLATFORM_DRIVER 892 platform_driver_unregister(&PLATFORM_DRIVER); 893clean0: 894#endif 895 kmem_cache_destroy(uhci_up_cachep); 896 897up_failed: 898 debugfs_remove(uhci_debugfs_root); 899 900debug_failed: 901 kfree(errbuf); 902 903errbuf_failed: 904 905 clear_bit(USB_UHCI_LOADED, &usb_hcds_loaded); 906 return retval; 907} 908 909static void __exit uhci_hcd_cleanup(void) 910{ 911#ifdef PLATFORM_DRIVER 912 platform_driver_unregister(&PLATFORM_DRIVER); 913#endif 914#ifdef PCI_DRIVER 915 pci_unregister_driver(&PCI_DRIVER); 916#endif 917 kmem_cache_destroy(uhci_up_cachep); 918 debugfs_remove(uhci_debugfs_root); 919 kfree(errbuf); 920 clear_bit(USB_UHCI_LOADED, &usb_hcds_loaded); 921} 922 923module_init(uhci_hcd_init); 924module_exit(uhci_hcd_cleanup); 925 926MODULE_AUTHOR(DRIVER_AUTHOR); 927MODULE_DESCRIPTION(DRIVER_DESC); 928MODULE_LICENSE("GPL");