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/drivers/tty/serial/msm_serial.c

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t
C | 966 lines | 753 code | 172 blank | 41 comment | 105 complexity | 79afb9bf6e8b0ee795a2e66814ac52ff MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
  1/*
  2 * Driver for msm7k serial device and console
  3 *
  4 * Copyright (C) 2007 Google, Inc.
  5 * Author: Robert Love <rlove@google.com>
  6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
  7 *
  8 * This software is licensed under the terms of the GNU General Public
  9 * License version 2, as published by the Free Software Foundation, and
 10 * may be copied, distributed, and modified under those terms.
 11 *
 12 * This program is distributed in the hope that it will be useful,
 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 15 * GNU General Public License for more details.
 16 */
 17
 18#if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
 19# define SUPPORT_SYSRQ
 20#endif
 21
 22#include <linux/hrtimer.h>
 23#include <linux/module.h>
 24#include <linux/io.h>
 25#include <linux/ioport.h>
 26#include <linux/irq.h>
 27#include <linux/init.h>
 28#include <linux/console.h>
 29#include <linux/tty.h>
 30#include <linux/tty_flip.h>
 31#include <linux/serial_core.h>
 32#include <linux/serial.h>
 33#include <linux/clk.h>
 34#include <linux/platform_device.h>
 35#include <linux/delay.h>
 36
 37#include "msm_serial.h"
 38
 39struct msm_port {
 40	struct uart_port	uart;
 41	char			name[16];
 42	struct clk		*clk;
 43	struct clk		*pclk;
 44	unsigned int		imr;
 45	unsigned int            *gsbi_base;
 46	int			is_uartdm;
 47	unsigned int		old_snap_state;
 48};
 49
 50static inline void wait_for_xmitr(struct uart_port *port, int bits)
 51{
 52	if (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY))
 53		while ((msm_read(port, UART_ISR) & bits) != bits)
 54			cpu_relax();
 55}
 56
 57static void msm_stop_tx(struct uart_port *port)
 58{
 59	struct msm_port *msm_port = UART_TO_MSM(port);
 60
 61	msm_port->imr &= ~UART_IMR_TXLEV;
 62	msm_write(port, msm_port->imr, UART_IMR);
 63}
 64
 65static void msm_start_tx(struct uart_port *port)
 66{
 67	struct msm_port *msm_port = UART_TO_MSM(port);
 68
 69	msm_port->imr |= UART_IMR_TXLEV;
 70	msm_write(port, msm_port->imr, UART_IMR);
 71}
 72
 73static void msm_stop_rx(struct uart_port *port)
 74{
 75	struct msm_port *msm_port = UART_TO_MSM(port);
 76
 77	msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
 78	msm_write(port, msm_port->imr, UART_IMR);
 79}
 80
 81static void msm_enable_ms(struct uart_port *port)
 82{
 83	struct msm_port *msm_port = UART_TO_MSM(port);
 84
 85	msm_port->imr |= UART_IMR_DELTA_CTS;
 86	msm_write(port, msm_port->imr, UART_IMR);
 87}
 88
 89static void handle_rx_dm(struct uart_port *port, unsigned int misr)
 90{
 91	struct tty_struct *tty = port->state->port.tty;
 92	unsigned int sr;
 93	int count = 0;
 94	struct msm_port *msm_port = UART_TO_MSM(port);
 95
 96	if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
 97		port->icount.overrun++;
 98		tty_insert_flip_char(tty, 0, TTY_OVERRUN);
 99		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
100	}
101
102	if (misr & UART_IMR_RXSTALE) {
103		count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
104			msm_port->old_snap_state;
105		msm_port->old_snap_state = 0;
106	} else {
107		count = 4 * (msm_read(port, UART_RFWR));
108		msm_port->old_snap_state += count;
109	}
110
111	/* TODO: Precise error reporting */
112
113	port->icount.rx += count;
114
115	while (count > 0) {
116		unsigned int c;
117
118		sr = msm_read(port, UART_SR);
119		if ((sr & UART_SR_RX_READY) == 0) {
120			msm_port->old_snap_state -= count;
121			break;
122		}
123		c = msm_read(port, UARTDM_RF);
124		if (sr & UART_SR_RX_BREAK) {
125			port->icount.brk++;
126			if (uart_handle_break(port))
127				continue;
128		} else if (sr & UART_SR_PAR_FRAME_ERR)
129			port->icount.frame++;
130
131		/* TODO: handle sysrq */
132		tty_insert_flip_string(tty, (char *) &c,
133				       (count > 4) ? 4 : count);
134		count -= 4;
135	}
136
137	tty_flip_buffer_push(tty);
138	if (misr & (UART_IMR_RXSTALE))
139		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
140	msm_write(port, 0xFFFFFF, UARTDM_DMRX);
141	msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
142}
143
144static void handle_rx(struct uart_port *port)
145{
146	struct tty_struct *tty = port->state->port.tty;
147	unsigned int sr;
148
149	/*
150	 * Handle overrun. My understanding of the hardware is that overrun
151	 * is not tied to the RX buffer, so we handle the case out of band.
152	 */
153	if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
154		port->icount.overrun++;
155		tty_insert_flip_char(tty, 0, TTY_OVERRUN);
156		msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
157	}
158
159	/* and now the main RX loop */
160	while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
161		unsigned int c;
162		char flag = TTY_NORMAL;
163
164		c = msm_read(port, UART_RF);
165
166		if (sr & UART_SR_RX_BREAK) {
167			port->icount.brk++;
168			if (uart_handle_break(port))
169				continue;
170		} else if (sr & UART_SR_PAR_FRAME_ERR) {
171			port->icount.frame++;
172		} else {
173			port->icount.rx++;
174		}
175
176		/* Mask conditions we're ignorning. */
177		sr &= port->read_status_mask;
178
179		if (sr & UART_SR_RX_BREAK) {
180			flag = TTY_BREAK;
181		} else if (sr & UART_SR_PAR_FRAME_ERR) {
182			flag = TTY_FRAME;
183		}
184
185		if (!uart_handle_sysrq_char(port, c))
186			tty_insert_flip_char(tty, c, flag);
187	}
188
189	tty_flip_buffer_push(tty);
190}
191
192static void reset_dm_count(struct uart_port *port)
193{
194	wait_for_xmitr(port, UART_ISR_TX_READY);
195	msm_write(port, 1, UARTDM_NCF_TX);
196}
197
198static void handle_tx(struct uart_port *port)
199{
200	struct circ_buf *xmit = &port->state->xmit;
201	struct msm_port *msm_port = UART_TO_MSM(port);
202	int sent_tx;
203
204	if (port->x_char) {
205		if (msm_port->is_uartdm)
206			reset_dm_count(port);
207
208		msm_write(port, port->x_char,
209			  msm_port->is_uartdm ? UARTDM_TF : UART_TF);
210		port->icount.tx++;
211		port->x_char = 0;
212	}
213
214	if (msm_port->is_uartdm)
215		reset_dm_count(port);
216
217	while (msm_read(port, UART_SR) & UART_SR_TX_READY) {
218		if (uart_circ_empty(xmit)) {
219			/* disable tx interrupts */
220			msm_port->imr &= ~UART_IMR_TXLEV;
221			msm_write(port, msm_port->imr, UART_IMR);
222			break;
223		}
224		msm_write(port, xmit->buf[xmit->tail],
225			  msm_port->is_uartdm ? UARTDM_TF : UART_TF);
226
227		if (msm_port->is_uartdm)
228			reset_dm_count(port);
229
230		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
231		port->icount.tx++;
232		sent_tx = 1;
233	}
234
235	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
236		uart_write_wakeup(port);
237}
238
239static void handle_delta_cts(struct uart_port *port)
240{
241	msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
242	port->icount.cts++;
243	wake_up_interruptible(&port->state->port.delta_msr_wait);
244}
245
246static irqreturn_t msm_irq(int irq, void *dev_id)
247{
248	struct uart_port *port = dev_id;
249	struct msm_port *msm_port = UART_TO_MSM(port);
250	unsigned int misr;
251
252	spin_lock(&port->lock);
253	misr = msm_read(port, UART_MISR);
254	msm_write(port, 0, UART_IMR); /* disable interrupt */
255
256	if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
257		if (msm_port->is_uartdm)
258			handle_rx_dm(port, misr);
259		else
260			handle_rx(port);
261	}
262	if (misr & UART_IMR_TXLEV)
263		handle_tx(port);
264	if (misr & UART_IMR_DELTA_CTS)
265		handle_delta_cts(port);
266
267	msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
268	spin_unlock(&port->lock);
269
270	return IRQ_HANDLED;
271}
272
273static unsigned int msm_tx_empty(struct uart_port *port)
274{
275	return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
276}
277
278static unsigned int msm_get_mctrl(struct uart_port *port)
279{
280	return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
281}
282
283
284static void msm_reset(struct uart_port *port)
285{
286	/* reset everything */
287	msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
288	msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
289	msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
290	msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
291	msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
292	msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
293}
294
295void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
296{
297	unsigned int mr;
298	mr = msm_read(port, UART_MR1);
299
300	if (!(mctrl & TIOCM_RTS)) {
301		mr &= ~UART_MR1_RX_RDY_CTL;
302		msm_write(port, mr, UART_MR1);
303		msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
304	} else {
305		mr |= UART_MR1_RX_RDY_CTL;
306		msm_write(port, mr, UART_MR1);
307	}
308}
309
310static void msm_break_ctl(struct uart_port *port, int break_ctl)
311{
312	if (break_ctl)
313		msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
314	else
315		msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
316}
317
318static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
319{
320	unsigned int baud_code, rxstale, watermark;
321	struct msm_port *msm_port = UART_TO_MSM(port);
322
323	switch (baud) {
324	case 300:
325		baud_code = UART_CSR_300;
326		rxstale = 1;
327		break;
328	case 600:
329		baud_code = UART_CSR_600;
330		rxstale = 1;
331		break;
332	case 1200:
333		baud_code = UART_CSR_1200;
334		rxstale = 1;
335		break;
336	case 2400:
337		baud_code = UART_CSR_2400;
338		rxstale = 1;
339		break;
340	case 4800:
341		baud_code = UART_CSR_4800;
342		rxstale = 1;
343		break;
344	case 9600:
345		baud_code = UART_CSR_9600;
346		rxstale = 2;
347		break;
348	case 14400:
349		baud_code = UART_CSR_14400;
350		rxstale = 3;
351		break;
352	case 19200:
353		baud_code = UART_CSR_19200;
354		rxstale = 4;
355		break;
356	case 28800:
357		baud_code = UART_CSR_28800;
358		rxstale = 6;
359		break;
360	case 38400:
361		baud_code = UART_CSR_38400;
362		rxstale = 8;
363		break;
364	case 57600:
365		baud_code = UART_CSR_57600;
366		rxstale = 16;
367		break;
368	case 115200:
369	default:
370		baud_code = UART_CSR_115200;
371		baud = 115200;
372		rxstale = 31;
373		break;
374	}
375
376	if (msm_port->is_uartdm)
377		msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
378
379	msm_write(port, baud_code, UART_CSR);
380
381	/* RX stale watermark */
382	watermark = UART_IPR_STALE_LSB & rxstale;
383	watermark |= UART_IPR_RXSTALE_LAST;
384	watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2);
385	msm_write(port, watermark, UART_IPR);
386
387	/* set RX watermark */
388	watermark = (port->fifosize * 3) / 4;
389	msm_write(port, watermark, UART_RFWR);
390
391	/* set TX watermark */
392	msm_write(port, 10, UART_TFWR);
393
394	if (msm_port->is_uartdm) {
395		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
396		msm_write(port, 0xFFFFFF, UARTDM_DMRX);
397		msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
398	}
399
400	return baud;
401}
402
403
404static void msm_init_clock(struct uart_port *port)
405{
406	struct msm_port *msm_port = UART_TO_MSM(port);
407
408	clk_enable(msm_port->clk);
409	if (!IS_ERR(msm_port->pclk))
410		clk_enable(msm_port->pclk);
411	msm_serial_set_mnd_regs(port);
412}
413
414static int msm_startup(struct uart_port *port)
415{
416	struct msm_port *msm_port = UART_TO_MSM(port);
417	unsigned int data, rfr_level;
418	int ret;
419
420	snprintf(msm_port->name, sizeof(msm_port->name),
421		 "msm_serial%d", port->line);
422
423	ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
424			  msm_port->name, port);
425	if (unlikely(ret))
426		return ret;
427
428	msm_init_clock(port);
429
430	if (likely(port->fifosize > 12))
431		rfr_level = port->fifosize - 12;
432	else
433		rfr_level = port->fifosize;
434
435	/* set automatic RFR level */
436	data = msm_read(port, UART_MR1);
437	data &= ~UART_MR1_AUTO_RFR_LEVEL1;
438	data &= ~UART_MR1_AUTO_RFR_LEVEL0;
439	data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
440	data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
441	msm_write(port, data, UART_MR1);
442
443	/* make sure that RXSTALE count is non-zero */
444	data = msm_read(port, UART_IPR);
445	if (unlikely(!data)) {
446		data |= UART_IPR_RXSTALE_LAST;
447		data |= UART_IPR_STALE_LSB;
448		msm_write(port, data, UART_IPR);
449	}
450
451	data = 0;
452	if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) {
453		msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
454		msm_reset(port);
455		data = UART_CR_TX_ENABLE;
456	}
457
458	data |= UART_CR_RX_ENABLE;
459	msm_write(port, data, UART_CR);	/* enable TX & RX */
460
461	/* Make sure IPR is not 0 to start with*/
462	if (msm_port->is_uartdm)
463		msm_write(port, UART_IPR_STALE_LSB, UART_IPR);
464
465	/* turn on RX and CTS interrupts */
466	msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
467			UART_IMR_CURRENT_CTS;
468
469	if (msm_port->is_uartdm) {
470		msm_write(port, 0xFFFFFF, UARTDM_DMRX);
471		msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
472		msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
473	}
474
475	msm_write(port, msm_port->imr, UART_IMR);
476	return 0;
477}
478
479static void msm_shutdown(struct uart_port *port)
480{
481	struct msm_port *msm_port = UART_TO_MSM(port);
482
483	msm_port->imr = 0;
484	msm_write(port, 0, UART_IMR); /* disable interrupts */
485
486	clk_disable(msm_port->clk);
487
488	free_irq(port->irq, port);
489}
490
491static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
492			    struct ktermios *old)
493{
494	unsigned long flags;
495	unsigned int baud, mr;
496
497	spin_lock_irqsave(&port->lock, flags);
498
499	/* calculate and set baud rate */
500	baud = uart_get_baud_rate(port, termios, old, 300, 115200);
501	baud = msm_set_baud_rate(port, baud);
502	if (tty_termios_baud_rate(termios))
503		tty_termios_encode_baud_rate(termios, baud, baud);
504
505	/* calculate parity */
506	mr = msm_read(port, UART_MR2);
507	mr &= ~UART_MR2_PARITY_MODE;
508	if (termios->c_cflag & PARENB) {
509		if (termios->c_cflag & PARODD)
510			mr |= UART_MR2_PARITY_MODE_ODD;
511		else if (termios->c_cflag & CMSPAR)
512			mr |= UART_MR2_PARITY_MODE_SPACE;
513		else
514			mr |= UART_MR2_PARITY_MODE_EVEN;
515	}
516
517	/* calculate bits per char */
518	mr &= ~UART_MR2_BITS_PER_CHAR;
519	switch (termios->c_cflag & CSIZE) {
520	case CS5:
521		mr |= UART_MR2_BITS_PER_CHAR_5;
522		break;
523	case CS6:
524		mr |= UART_MR2_BITS_PER_CHAR_6;
525		break;
526	case CS7:
527		mr |= UART_MR2_BITS_PER_CHAR_7;
528		break;
529	case CS8:
530	default:
531		mr |= UART_MR2_BITS_PER_CHAR_8;
532		break;
533	}
534
535	/* calculate stop bits */
536	mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
537	if (termios->c_cflag & CSTOPB)
538		mr |= UART_MR2_STOP_BIT_LEN_TWO;
539	else
540		mr |= UART_MR2_STOP_BIT_LEN_ONE;
541
542	/* set parity, bits per char, and stop bit */
543	msm_write(port, mr, UART_MR2);
544
545	/* calculate and set hardware flow control */
546	mr = msm_read(port, UART_MR1);
547	mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
548	if (termios->c_cflag & CRTSCTS) {
549		mr |= UART_MR1_CTS_CTL;
550		mr |= UART_MR1_RX_RDY_CTL;
551	}
552	msm_write(port, mr, UART_MR1);
553
554	/* Configure status bits to ignore based on termio flags. */
555	port->read_status_mask = 0;
556	if (termios->c_iflag & INPCK)
557		port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
558	if (termios->c_iflag & (BRKINT | PARMRK))
559		port->read_status_mask |= UART_SR_RX_BREAK;
560
561	uart_update_timeout(port, termios->c_cflag, baud);
562
563	spin_unlock_irqrestore(&port->lock, flags);
564}
565
566static const char *msm_type(struct uart_port *port)
567{
568	return "MSM";
569}
570
571static void msm_release_port(struct uart_port *port)
572{
573	struct platform_device *pdev = to_platform_device(port->dev);
574	struct msm_port *msm_port = UART_TO_MSM(port);
575	struct resource *uart_resource;
576	struct resource *gsbi_resource;
577	resource_size_t size;
578
579	uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
580	if (unlikely(!uart_resource))
581		return;
582	size = resource_size(uart_resource);
583
584	release_mem_region(port->mapbase, size);
585	iounmap(port->membase);
586	port->membase = NULL;
587
588	if (msm_port->gsbi_base) {
589		iowrite32(GSBI_PROTOCOL_IDLE, msm_port->gsbi_base +
590			  GSBI_CONTROL);
591
592		gsbi_resource = platform_get_resource_byname(pdev,
593							     IORESOURCE_MEM,
594							     "gsbi_resource");
595
596		if (unlikely(!gsbi_resource))
597			return;
598
599		size = resource_size(gsbi_resource);
600		release_mem_region(gsbi_resource->start, size);
601		iounmap(msm_port->gsbi_base);
602		msm_port->gsbi_base = NULL;
603	}
604}
605
606static int msm_request_port(struct uart_port *port)
607{
608	struct msm_port *msm_port = UART_TO_MSM(port);
609	struct platform_device *pdev = to_platform_device(port->dev);
610	struct resource *uart_resource;
611	struct resource *gsbi_resource;
612	resource_size_t size;
613	int ret;
614
615	uart_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
616						     "uart_resource");
617	if (unlikely(!uart_resource))
618		return -ENXIO;
619
620	size = resource_size(uart_resource);
621
622	if (!request_mem_region(port->mapbase, size, "msm_serial"))
623		return -EBUSY;
624
625	port->membase = ioremap(port->mapbase, size);
626	if (!port->membase) {
627		ret = -EBUSY;
628		goto fail_release_port;
629	}
630
631	gsbi_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
632						     "gsbi_resource");
633	/* Is this a GSBI-based port? */
634	if (gsbi_resource) {
635		size = resource_size(gsbi_resource);
636
637		if (!request_mem_region(gsbi_resource->start, size,
638						 "msm_serial")) {
639			ret = -EBUSY;
640			goto fail_release_port;
641		}
642
643		msm_port->gsbi_base = ioremap(gsbi_resource->start, size);
644		if (!msm_port->gsbi_base) {
645			ret = -EBUSY;
646			goto fail_release_gsbi;
647		}
648	}
649
650	return 0;
651
652fail_release_gsbi:
653	release_mem_region(gsbi_resource->start, size);
654fail_release_port:
655	release_mem_region(port->mapbase, size);
656	return ret;
657}
658
659static void msm_config_port(struct uart_port *port, int flags)
660{
661	struct msm_port *msm_port = UART_TO_MSM(port);
662	int ret;
663	if (flags & UART_CONFIG_TYPE) {
664		port->type = PORT_MSM;
665		ret = msm_request_port(port);
666		if (ret)
667			return;
668	}
669
670	if (msm_port->is_uartdm)
671		iowrite32(GSBI_PROTOCOL_UART, msm_port->gsbi_base +
672			  GSBI_CONTROL);
673}
674
675static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
676{
677	if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
678		return -EINVAL;
679	if (unlikely(port->irq != ser->irq))
680		return -EINVAL;
681	return 0;
682}
683
684static void msm_power(struct uart_port *port, unsigned int state,
685		      unsigned int oldstate)
686{
687	struct msm_port *msm_port = UART_TO_MSM(port);
688
689	switch (state) {
690	case 0:
691		clk_enable(msm_port->clk);
692		if (!IS_ERR(msm_port->pclk))
693			clk_enable(msm_port->pclk);
694		break;
695	case 3:
696		clk_disable(msm_port->clk);
697		if (!IS_ERR(msm_port->pclk))
698			clk_disable(msm_port->pclk);
699		break;
700	default:
701		printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state);
702	}
703}
704
705static struct uart_ops msm_uart_pops = {
706	.tx_empty = msm_tx_empty,
707	.set_mctrl = msm_set_mctrl,
708	.get_mctrl = msm_get_mctrl,
709	.stop_tx = msm_stop_tx,
710	.start_tx = msm_start_tx,
711	.stop_rx = msm_stop_rx,
712	.enable_ms = msm_enable_ms,
713	.break_ctl = msm_break_ctl,
714	.startup = msm_startup,
715	.shutdown = msm_shutdown,
716	.set_termios = msm_set_termios,
717	.type = msm_type,
718	.release_port = msm_release_port,
719	.request_port = msm_request_port,
720	.config_port = msm_config_port,
721	.verify_port = msm_verify_port,
722	.pm = msm_power,
723};
724
725static struct msm_port msm_uart_ports[] = {
726	{
727		.uart = {
728			.iotype = UPIO_MEM,
729			.ops = &msm_uart_pops,
730			.flags = UPF_BOOT_AUTOCONF,
731			.fifosize = 64,
732			.line = 0,
733		},
734	},
735	{
736		.uart = {
737			.iotype = UPIO_MEM,
738			.ops = &msm_uart_pops,
739			.flags = UPF_BOOT_AUTOCONF,
740			.fifosize = 64,
741			.line = 1,
742		},
743	},
744	{
745		.uart = {
746			.iotype = UPIO_MEM,
747			.ops = &msm_uart_pops,
748			.flags = UPF_BOOT_AUTOCONF,
749			.fifosize = 64,
750			.line = 2,
751		},
752	},
753};
754
755#define UART_NR	ARRAY_SIZE(msm_uart_ports)
756
757static inline struct uart_port *get_port_from_line(unsigned int line)
758{
759	return &msm_uart_ports[line].uart;
760}
761
762#ifdef CONFIG_SERIAL_MSM_CONSOLE
763
764static void msm_console_putchar(struct uart_port *port, int c)
765{
766	struct msm_port *msm_port = UART_TO_MSM(port);
767
768	if (msm_port->is_uartdm)
769		reset_dm_count(port);
770
771	while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
772		;
773	msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
774}
775
776static void msm_console_write(struct console *co, const char *s,
777			      unsigned int count)
778{
779	struct uart_port *port;
780	struct msm_port *msm_port;
781
782	BUG_ON(co->index < 0 || co->index >= UART_NR);
783
784	port = get_port_from_line(co->index);
785	msm_port = UART_TO_MSM(port);
786
787	spin_lock(&port->lock);
788	uart_console_write(port, s, count, msm_console_putchar);
789	spin_unlock(&port->lock);
790}
791
792static int __init msm_console_setup(struct console *co, char *options)
793{
794	struct uart_port *port;
795	struct msm_port *msm_port;
796	int baud, flow, bits, parity;
797
798	if (unlikely(co->index >= UART_NR || co->index < 0))
799		return -ENXIO;
800
801	port = get_port_from_line(co->index);
802	msm_port = UART_TO_MSM(port);
803
804	if (unlikely(!port->membase))
805		return -ENXIO;
806
807	port->cons = co;
808
809	msm_init_clock(port);
810
811	if (options)
812		uart_parse_options(options, &baud, &parity, &bits, &flow);
813
814	bits = 8;
815	parity = 'n';
816	flow = 'n';
817	msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE,
818		  UART_MR2);	/* 8N1 */
819
820	if (baud < 300 || baud > 115200)
821		baud = 115200;
822	msm_set_baud_rate(port, baud);
823
824	msm_reset(port);
825
826	if (msm_port->is_uartdm) {
827		msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
828		msm_write(port, UART_CR_TX_ENABLE, UART_CR);
829	}
830
831	printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line);
832
833	return uart_set_options(port, co, baud, parity, bits, flow);
834}
835
836static struct uart_driver msm_uart_driver;
837
838static struct console msm_console = {
839	.name = "ttyMSM",
840	.write = msm_console_write,
841	.device = uart_console_device,
842	.setup = msm_console_setup,
843	.flags = CON_PRINTBUFFER,
844	.index = -1,
845	.data = &msm_uart_driver,
846};
847
848#define MSM_CONSOLE	(&msm_console)
849
850#else
851#define MSM_CONSOLE	NULL
852#endif
853
854static struct uart_driver msm_uart_driver = {
855	.owner = THIS_MODULE,
856	.driver_name = "msm_serial",
857	.dev_name = "ttyMSM",
858	.nr = UART_NR,
859	.cons = MSM_CONSOLE,
860};
861
862static int __init msm_serial_probe(struct platform_device *pdev)
863{
864	struct msm_port *msm_port;
865	struct resource *resource;
866	struct uart_port *port;
867	int irq;
868
869	if (unlikely(pdev->id < 0 || pdev->id >= UART_NR))
870		return -ENXIO;
871
872	printk(KERN_INFO "msm_serial: detected port #%d\n", pdev->id);
873
874	port = get_port_from_line(pdev->id);
875	port->dev = &pdev->dev;
876	msm_port = UART_TO_MSM(port);
877
878	if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "gsbi_resource"))
879		msm_port->is_uartdm = 1;
880	else
881		msm_port->is_uartdm = 0;
882
883	if (msm_port->is_uartdm) {
884		msm_port->clk = clk_get(&pdev->dev, "gsbi_uart_clk");
885		msm_port->pclk = clk_get(&pdev->dev, "gsbi_pclk");
886	} else {
887		msm_port->clk = clk_get(&pdev->dev, "uart_clk");
888		msm_port->pclk = ERR_PTR(-ENOENT);
889	}
890
891	if (unlikely(IS_ERR(msm_port->clk) || (IS_ERR(msm_port->pclk) &&
892					       msm_port->is_uartdm)))
893			return PTR_ERR(msm_port->clk);
894
895	if (msm_port->is_uartdm)
896		clk_set_rate(msm_port->clk, 7372800);
897
898	port->uartclk = clk_get_rate(msm_port->clk);
899	printk(KERN_INFO "uartclk = %d\n", port->uartclk);
900
901
902	resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
903						     "uart_resource");
904	if (unlikely(!resource))
905		return -ENXIO;
906	port->mapbase = resource->start;
907
908	irq = platform_get_irq(pdev, 0);
909	if (unlikely(irq < 0))
910		return -ENXIO;
911	port->irq = irq;
912
913	platform_set_drvdata(pdev, port);
914
915	return uart_add_one_port(&msm_uart_driver, port);
916}
917
918static int __devexit msm_serial_remove(struct platform_device *pdev)
919{
920	struct msm_port *msm_port = platform_get_drvdata(pdev);
921
922	clk_put(msm_port->clk);
923
924	return 0;
925}
926
927static struct platform_driver msm_platform_driver = {
928	.remove = msm_serial_remove,
929	.driver = {
930		.name = "msm_serial",
931		.owner = THIS_MODULE,
932	},
933};
934
935static int __init msm_serial_init(void)
936{
937	int ret;
938
939	ret = uart_register_driver(&msm_uart_driver);
940	if (unlikely(ret))
941		return ret;
942
943	ret = platform_driver_probe(&msm_platform_driver, msm_serial_probe);
944	if (unlikely(ret))
945		uart_unregister_driver(&msm_uart_driver);
946
947	printk(KERN_INFO "msm_serial: driver initialized\n");
948
949	return ret;
950}
951
952static void __exit msm_serial_exit(void)
953{
954#ifdef CONFIG_SERIAL_MSM_CONSOLE
955	unregister_console(&msm_console);
956#endif
957	platform_driver_unregister(&msm_platform_driver);
958	uart_unregister_driver(&msm_uart_driver);
959}
960
961module_init(msm_serial_init);
962module_exit(msm_serial_exit);
963
964MODULE_AUTHOR("Robert Love <rlove@google.com>");
965MODULE_DESCRIPTION("Driver for msm7x serial device");
966MODULE_LICENSE("GPL");