/drivers/staging/vt6656/rf.c

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t · C · 1151 lines · 890 code · 112 blank · 149 comment · 37 complexity · 0192106507b8597ed62d63090e4cca81 MD5 · raw file 

    

  1. /*
    2. 

  2.  * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
    3. 

  3.  * All rights reserved.
    4. 

  4.  *
    5. 

  5.  * This program is free software; you can redistribute it and/or modify
    6. 

  6.  * it under the terms of the GNU General Public License as published by
    7. 

  7.  * the Free Software Foundation; either version 2 of the License, or
    8. 

  8.  * (at your option) any later version.
    9. 

  9.  *
    10. 

  10.  * This program is distributed in the hope that it will be useful,
    11. 

  11.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    12. 

  12.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    13. 

  13.  * GNU General Public License for more details.
    14. 

  14.  *
    15. 

  15.  * You should have received a copy of the GNU General Public License along
    16. 

  16.  * with this program; if not, write to the Free Software Foundation, Inc.,
    17. 

  17.  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
    18. 

  18.  *
    19. 

  19.  *
    20. 

  20.  * File: rf.c
    21. 

  21.  *
    22. 

  22.  * Purpose: rf function code
    23. 

  23.  *
    24. 

  24.  * Author: Jerry Chen
    25. 

  25.  *
    26. 

  26.  * Date: Feb. 19, 2004
    27. 

  27.  *
    28. 

  28.  * Functions:
    29. 

  29.  *      IFRFbWriteEmbeded      - Embeded write RF register via MAC
    30. 

  30.  *
    31. 

  31.  * Revision History:
    32. 

  32.  *
    33. 

  33.  */
    34. 

  34. 

  35. #include "mac.h"
    36. 

  36. #include "rf.h"
    37. 

  37. #include "baseband.h"
    38. 

  38. #include "control.h"
    39. 

  39. #include "rndis.h"
    40. 

  40. #include "datarate.h"
    41. 

  41. 

  42. static int          msglevel                =MSG_LEVEL_INFO;
    43. 

  43. //static int          msglevel                =MSG_LEVEL_DEBUG;
    44. 

  44. /*---------------------  Static Definitions -------------------------*/
    45. 

  45. #define BY_AL2230_REG_LEN     23 //24bit
    46. 

  46. #define CB_AL2230_INIT_SEQ    15
    47. 

  47. #define AL2230_PWR_IDX_LEN    64
    48. 

  48. 

  49. #define BY_AL7230_REG_LEN     23 //24bit
    50. 

  50. #define CB_AL7230_INIT_SEQ    16
    51. 

  51. #define AL7230_PWR_IDX_LEN    64
    52. 

  52. 

  53. //{{RobertYu:20051111
    54. 

  54. #define BY_VT3226_REG_LEN     23
    55. 

  55. #define CB_VT3226_INIT_SEQ    11
    56. 

  56. #define VT3226_PWR_IDX_LEN    64
    57. 

  57. //}}
    58. 

  58. 

  59. //{{RobertYu:20060609
    60. 

  60. #define BY_VT3342_REG_LEN     23
    61. 

  61. #define CB_VT3342_INIT_SEQ    13
    62. 

  62. #define VT3342_PWR_IDX_LEN    64
    63. 

  63. //}}
    64. 

  64. 

  65. /*---------------------  Static Classes  ----------------------------*/
    66. 

  66. 

  67. /*---------------------  Static Variables  --------------------------*/
    68. 

  68. 

  69. 

  70. 

  71. 

  72. BYTE abyAL2230InitTable[CB_AL2230_INIT_SEQ][3] = {
    73. 

  73.     {0x03, 0xF7, 0x90},
    74. 

  74.     {0x03, 0x33, 0x31},
    75. 

  75.     {0x01, 0xB8, 0x02},
    76. 

  76.     {0x00, 0xFF, 0xF3},
    77. 

  77.     {0x00, 0x05, 0xA4},
    78. 

  78.     {0x0F, 0x4D, 0xC5},   //RobertYu:20060814
    79. 

  79.     {0x08, 0x05, 0xB6},
    80. 

  80.     {0x01, 0x47, 0xC7},
    81. 

  81.     {0x00, 0x06, 0x88},
    82. 

  82.     {0x04, 0x03, 0xB9},
    83. 

  83.     {0x00, 0xDB, 0xBA},
    84. 

  84.     {0x00, 0x09, 0x9B},
    85. 

  85.     {0x0B, 0xDF, 0xFC},
    86. 

  86.     {0x00, 0x00, 0x0D},
    87. 

  87.     {0x00, 0x58, 0x0F}
    88. 

  88.     };
    89. 

  89. 

  90. BYTE abyAL2230ChannelTable0[CB_MAX_CHANNEL_24G][3] = {
    91. 

  91.     {0x03, 0xF7, 0x90}, // channel = 1, Tf = 2412MHz
    92. 

  92.     {0x03, 0xF7, 0x90}, // channel = 2, Tf = 2417MHz
    93. 

  93.     {0x03, 0xE7, 0x90}, // channel = 3, Tf = 2422MHz
    94. 

  94.     {0x03, 0xE7, 0x90}, // channel = 4, Tf = 2427MHz
    95. 

  95.     {0x03, 0xF7, 0xA0}, // channel = 5, Tf = 2432MHz
    96. 

  96.     {0x03, 0xF7, 0xA0}, // channel = 6, Tf = 2437MHz
    97. 

  97.     {0x03, 0xE7, 0xA0}, // channel = 7, Tf = 2442MHz
    98. 

  98.     {0x03, 0xE7, 0xA0}, // channel = 8, Tf = 2447MHz
    99. 

  99.     {0x03, 0xF7, 0xB0}, // channel = 9, Tf = 2452MHz
    100. 

  100.     {0x03, 0xF7, 0xB0}, // channel = 10, Tf = 2457MHz
    101. 

  101.     {0x03, 0xE7, 0xB0}, // channel = 11, Tf = 2462MHz
    102. 

  102.     {0x03, 0xE7, 0xB0}, // channel = 12, Tf = 2467MHz
    103. 

  103.     {0x03, 0xF7, 0xC0}, // channel = 13, Tf = 2472MHz
    104. 

  104.     {0x03, 0xE7, 0xC0}  // channel = 14, Tf = 2412M
    105. 

  105.     };
    106. 

  106. 

  107. BYTE abyAL2230ChannelTable1[CB_MAX_CHANNEL_24G][3] = {
    108. 

  108.     {0x03, 0x33, 0x31}, // channel = 1, Tf = 2412MHz
    109. 

  109.     {0x0B, 0x33, 0x31}, // channel = 2, Tf = 2417MHz
    110. 

  110.     {0x03, 0x33, 0x31}, // channel = 3, Tf = 2422MHz
    111. 

  111.     {0x0B, 0x33, 0x31}, // channel = 4, Tf = 2427MHz
    112. 

  112.     {0x03, 0x33, 0x31}, // channel = 5, Tf = 2432MHz
    113. 

  113.     {0x0B, 0x33, 0x31}, // channel = 6, Tf = 2437MHz
    114. 

  114.     {0x03, 0x33, 0x31}, // channel = 7, Tf = 2442MHz
    115. 

  115.     {0x0B, 0x33, 0x31}, // channel = 8, Tf = 2447MHz
    116. 

  116.     {0x03, 0x33, 0x31}, // channel = 9, Tf = 2452MHz
    117. 

  117.     {0x0B, 0x33, 0x31}, // channel = 10, Tf = 2457MHz
    118. 

  118.     {0x03, 0x33, 0x31}, // channel = 11, Tf = 2462MHz
    119. 

  119.     {0x0B, 0x33, 0x31}, // channel = 12, Tf = 2467MHz
    120. 

  120.     {0x03, 0x33, 0x31}, // channel = 13, Tf = 2472MHz
    121. 

  121.     {0x06, 0x66, 0x61}  // channel = 14, Tf = 2412M
    122. 

  122.     };
    123. 

  123. 

  124. // 40MHz reference frequency
    125. 

  125. // Need to Pull PLLON(PE3) low when writing channel registers through 3-wire.
    126. 

  126. BYTE abyAL7230InitTable[CB_AL7230_INIT_SEQ][3] = {
    127. 

  127.     {0x20, 0x37, 0x90}, // Channel1 // Need modify for 11a
    128. 

  128.     {0x13, 0x33, 0x31}, // Channel1 // Need modify for 11a
    129. 

  129.     {0x84, 0x1F, 0xF2}, // Need modify for 11a: 451FE2
    130. 

  130.     {0x3F, 0xDF, 0xA3}, // Need modify for 11a: 5FDFA3
    131. 

  131.     {0x7F, 0xD7, 0x84}, // 11b/g    // Need modify for 11a
    132. 

  132.     //0x802B4500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 8D1B45
    133. 

  133.     // RoberYu:20050113, Rev0.47 Regsiter Setting Guide
    134. 

  134.     {0x80, 0x2B, 0x55}, // Need modify for 11a: 8D1B55
    135. 

  135.     {0x56, 0xAF, 0x36},
    136. 

  136.     {0xCE, 0x02, 0x07}, // Need modify for 11a: 860207
    137. 

  137.     {0x6E, 0xBC, 0x98},
    138. 

  138.     {0x22, 0x1B, 0xB9},
    139. 

  139.     {0xE0, 0x00, 0x0A}, // Need modify for 11a: E0600A
    140. 

  140.     {0x08, 0x03, 0x1B}, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10)
    141. 

  141.     //0x00093C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, // Need modify for 11a: 00143C
    142. 

  142.     // RoberYu:20050113, Rev0.47 Regsiter Setting Guide
    143. 

  143.     {0x00, 0x0A, 0x3C}, // Need modify for 11a: 00143C
    144. 

  144.     {0xFF, 0xFF, 0xFD},
    145. 

  145.     {0x00, 0x00, 0x0E},
    146. 

  146.     {0x1A, 0xBA, 0x8F} // Need modify for 11a: 12BACF
    147. 

  147.     };
    148. 

  148. 

  149. BYTE abyAL7230InitTableAMode[CB_AL7230_INIT_SEQ][3] = {
    150. 

  150.     {0x2F, 0xF5, 0x20}, // Channel184 // Need modify for 11b/g
    151. 

  151.     {0x00, 0x00, 0x01}, // Channel184 // Need modify for 11b/g
    152. 

  152.     {0x45, 0x1F, 0xE2}, // Need modify for 11b/g
    153. 

  153.     {0x5F, 0xDF, 0xA3}, // Need modify for 11b/g
    154. 

  154.     {0x6F, 0xD7, 0x84}, // 11a    // Need modify for 11b/g
    155. 

  155.     {0x85, 0x3F, 0x55}, // Need modify for 11b/g, RoberYu:20050113
    156. 

  156.     {0x56, 0xAF, 0x36},
    157. 

  157.     {0xCE, 0x02, 0x07}, // Need modify for 11b/g
    158. 

  158.     {0x6E, 0xBC, 0x98},
    159. 

  159.     {0x22, 0x1B, 0xB9},
    160. 

  160.     {0xE0, 0x60, 0x0A}, // Need modify for 11b/g
    161. 

  161.     {0x08, 0x03, 0x1B}, // init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10)
    162. 

  162.     {0x00, 0x14, 0x7C}, // Need modify for 11b/g
    163. 

  163.     {0xFF, 0xFF, 0xFD},
    164. 

  164.     {0x00, 0x00, 0x0E},
    165. 

  165.     {0x12, 0xBA, 0xCF} // Need modify for 11b/g
    166. 

  166.     };
    167. 

  167. 

  168. BYTE abyAL7230ChannelTable0[CB_MAX_CHANNEL][3] = {
    169. 

  169.     {0x20, 0x37, 0x90}, // channel =  1, Tf = 2412MHz
    170. 

  170.     {0x20, 0x37, 0x90}, // channel =  2, Tf = 2417MHz
    171. 

  171.     {0x20, 0x37, 0x90}, // channel =  3, Tf = 2422MHz
    172. 

  172.     {0x20, 0x37, 0x90}, // channel =  4, Tf = 2427MHz
    173. 

  173.     {0x20, 0x37, 0xA0}, // channel =  5, Tf = 2432MHz
    174. 

  174.     {0x20, 0x37, 0xA0}, // channel =  6, Tf = 2437MHz
    175. 

  175.     {0x20, 0x37, 0xA0}, // channel =  7, Tf = 2442MHz
    176. 

  176.     {0x20, 0x37, 0xA0}, // channel =  8, Tf = 2447MHz //RobertYu: 20050218, update for APNode 0.49
    177. 

  177.     {0x20, 0x37, 0xB0}, // channel =  9, Tf = 2452MHz //RobertYu: 20050218, update for APNode 0.49
    178. 

  178.     {0x20, 0x37, 0xB0}, // channel = 10, Tf = 2457MHz //RobertYu: 20050218, update for APNode 0.49
    179. 

  179.     {0x20, 0x37, 0xB0}, // channel = 11, Tf = 2462MHz //RobertYu: 20050218, update for APNode 0.49
    180. 

  180.     {0x20, 0x37, 0xB0}, // channel = 12, Tf = 2467MHz //RobertYu: 20050218, update for APNode 0.49
    181. 

  181.     {0x20, 0x37, 0xC0}, // channel = 13, Tf = 2472MHz //RobertYu: 20050218, update for APNode 0.49
    182. 

  182.     {0x20, 0x37, 0xC0}, // channel = 14, Tf = 2484MHz
    183. 

  183. 

  184.     // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196  (Value:15 ~ 22)
    185. 

  185.     {0x0F, 0xF5, 0x20}, // channel = 183, Tf = 4915MHz (15)
    186. 

  186.     {0x2F, 0xF5, 0x20}, // channel = 184, Tf = 4920MHz (16)
    187. 

  187.     {0x0F, 0xF5, 0x20}, // channel = 185, Tf = 4925MHz (17)
    188. 

  188.     {0x0F, 0xF5, 0x20}, // channel = 187, Tf = 4935MHz (18)
    189. 

  189.     {0x2F, 0xF5, 0x20}, // channel = 188, Tf = 4940MHz (19)
    190. 

  190.     {0x0F, 0xF5, 0x20}, // channel = 189, Tf = 4945MHz (20)
    191. 

  191.     {0x2F, 0xF5, 0x30}, // channel = 192, Tf = 4960MHz (21)
    192. 

  192.     {0x2F, 0xF5, 0x30}, // channel = 196, Tf = 4980MHz (22)
    193. 

  193. 

  194.     // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
    195. 

  195.     // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165  (Value 23 ~ 56)
    196. 

  196. 

  197.     {0x0F, 0xF5, 0x40}, // channel =   7, Tf = 5035MHz (23)
    198. 

  198.     {0x2F, 0xF5, 0x40}, // channel =   8, Tf = 5040MHz (24)
    199. 

  199.     {0x0F, 0xF5, 0x40}, // channel =   9, Tf = 5045MHz (25)
    200. 

  200.     {0x0F, 0xF5, 0x40}, // channel =  11, Tf = 5055MHz (26)
    201. 

  201.     {0x2F, 0xF5, 0x40}, // channel =  12, Tf = 5060MHz (27)
    202. 

  202.     {0x2F, 0xF5, 0x50}, // channel =  16, Tf = 5080MHz (28)
    203. 

  203.     {0x2F, 0xF5, 0x60}, // channel =  34, Tf = 5170MHz (29)
    204. 

  204.     {0x2F, 0xF5, 0x60}, // channel =  36, Tf = 5180MHz (30)
    205. 

  205.     {0x2F, 0xF5, 0x70}, // channel =  38, Tf = 5190MHz (31) //RobertYu: 20050218, update for APNode 0.49
    206. 

  206.     {0x2F, 0xF5, 0x70}, // channel =  40, Tf = 5200MHz (32)
    207. 

  207.     {0x2F, 0xF5, 0x70}, // channel =  42, Tf = 5210MHz (33)
    208. 

  208.     {0x2F, 0xF5, 0x70}, // channel =  44, Tf = 5220MHz (34)
    209. 

  209.     {0x2F, 0xF5, 0x70}, // channel =  46, Tf = 5230MHz (35)
    210. 

  210.     {0x2F, 0xF5, 0x70}, // channel =  48, Tf = 5240MHz (36)
    211. 

  211.     {0x2F, 0xF5, 0x80}, // channel =  52, Tf = 5260MHz (37)
    212. 

  212.     {0x2F, 0xF5, 0x80}, // channel =  56, Tf = 5280MHz (38)
    213. 

  213.     {0x2F, 0xF5, 0x80}, // channel =  60, Tf = 5300MHz (39)
    214. 

  214.     {0x2F, 0xF5, 0x90}, // channel =  64, Tf = 5320MHz (40)
    215. 

  215. 

  216.     {0x2F, 0xF5, 0xC0}, // channel = 100, Tf = 5500MHz (41)
    217. 

  217.     {0x2F, 0xF5, 0xC0}, // channel = 104, Tf = 5520MHz (42)
    218. 

  218.     {0x2F, 0xF5, 0xC0}, // channel = 108, Tf = 5540MHz (43)
    219. 

  219.     {0x2F, 0xF5, 0xD0}, // channel = 112, Tf = 5560MHz (44)
    220. 

  220.     {0x2F, 0xF5, 0xD0}, // channel = 116, Tf = 5580MHz (45)
    221. 

  221.     {0x2F, 0xF5, 0xD0}, // channel = 120, Tf = 5600MHz (46)
    222. 

  222.     {0x2F, 0xF5, 0xE0}, // channel = 124, Tf = 5620MHz (47)
    223. 

  223.     {0x2F, 0xF5, 0xE0}, // channel = 128, Tf = 5640MHz (48)
    224. 

  224.     {0x2F, 0xF5, 0xE0}, // channel = 132, Tf = 5660MHz (49)
    225. 

  225.     {0x2F, 0xF5, 0xF0}, // channel = 136, Tf = 5680MHz (50)
    226. 

  226.     {0x2F, 0xF5, 0xF0}, // channel = 140, Tf = 5700MHz (51)
    227. 

  227.     {0x2F, 0xF6, 0x00}, // channel = 149, Tf = 5745MHz (52)
    228. 

  228.     {0x2F, 0xF6, 0x00}, // channel = 153, Tf = 5765MHz (53)
    229. 

  229.     {0x2F, 0xF6, 0x00}, // channel = 157, Tf = 5785MHz (54)
    230. 

  230.     {0x2F, 0xF6, 0x10}, // channel = 161, Tf = 5805MHz (55)
    231. 

  231.     {0x2F, 0xF6, 0x10} // channel = 165, Tf = 5825MHz (56)
    232. 

  232.     };
    233. 

  233. 

  234. BYTE abyAL7230ChannelTable1[CB_MAX_CHANNEL][3] = {
    235. 

  235.     {0x13, 0x33, 0x31}, // channel =  1, Tf = 2412MHz
    236. 

  236.     {0x1B, 0x33, 0x31}, // channel =  2, Tf = 2417MHz
    237. 

  237.     {0x03, 0x33, 0x31}, // channel =  3, Tf = 2422MHz
    238. 

  238.     {0x0B, 0x33, 0x31}, // channel =  4, Tf = 2427MHz
    239. 

  239.     {0x13, 0x33, 0x31}, // channel =  5, Tf = 2432MHz
    240. 

  240.     {0x1B, 0x33, 0x31}, // channel =  6, Tf = 2437MHz
    241. 

  241.     {0x03, 0x33, 0x31}, // channel =  7, Tf = 2442MHz
    242. 

  242.     {0x0B, 0x33, 0x31}, // channel =  8, Tf = 2447MHz
    243. 

  243.     {0x13, 0x33, 0x31}, // channel =  9, Tf = 2452MHz
    244. 

  244.     {0x1B, 0x33, 0x31}, // channel = 10, Tf = 2457MHz
    245. 

  245.     {0x03, 0x33, 0x31}, // channel = 11, Tf = 2462MHz
    246. 

  246.     {0x0B, 0x33, 0x31}, // channel = 12, Tf = 2467MHz
    247. 

  247.     {0x13, 0x33, 0x31}, // channel = 13, Tf = 2472MHz
    248. 

  248.     {0x06, 0x66, 0x61}, // channel = 14, Tf = 2484MHz
    249. 

  249. 

  250.     // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196  (Value:15 ~ 22)
    251. 

  251.     {0x1D, 0x55, 0x51}, // channel = 183, Tf = 4915MHz (15)
    252. 

  252.     {0x00, 0x00, 0x01}, // channel = 184, Tf = 4920MHz (16)
    253. 

  253.     {0x02, 0xAA, 0xA1}, // channel = 185, Tf = 4925MHz (17)
    254. 

  254.     {0x08, 0x00, 0x01}, // channel = 187, Tf = 4935MHz (18)
    255. 

  255.     {0x0A, 0xAA, 0xA1}, // channel = 188, Tf = 4940MHz (19)
    256. 

  256.     {0x0D, 0x55, 0x51}, // channel = 189, Tf = 4945MHz (20)
    257. 

  257.     {0x15, 0x55, 0x51}, // channel = 192, Tf = 4960MHz (21)
    258. 

  258.     {0x00, 0x00, 0x01}, // channel = 196, Tf = 4980MHz (22)
    259. 

  259. 

  260.     // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
    261. 

  261.     // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165  (Value 23 ~ 56)
    262. 

  262.     {0x1D, 0x55, 0x51}, // channel =   7, Tf = 5035MHz (23)
    263. 

  263.     {0x00, 0x00, 0x01}, // channel =   8, Tf = 5040MHz (24)
    264. 

  264.     {0x02, 0xAA, 0xA1}, // channel =   9, Tf = 5045MHz (25)
    265. 

  265.     {0x08, 0x00, 0x01}, // channel =  11, Tf = 5055MHz (26)
    266. 

  266.     {0x0A, 0xAA, 0xA1}, // channel =  12, Tf = 5060MHz (27)
    267. 

  267.     {0x15, 0x55, 0x51}, // channel =  16, Tf = 5080MHz (28)
    268. 

  268.     {0x05, 0x55, 0x51}, // channel =  34, Tf = 5170MHz (29)
    269. 

  269.     {0x0A, 0xAA, 0xA1}, // channel =  36, Tf = 5180MHz (30)
    270. 

  270.     {0x10, 0x00, 0x01}, // channel =  38, Tf = 5190MHz (31)
    271. 

  271.     {0x15, 0x55, 0x51}, // channel =  40, Tf = 5200MHz (32)
    272. 

  272.     {0x1A, 0xAA, 0xA1}, // channel =  42, Tf = 5210MHz (33)
    273. 

  273.     {0x00, 0x00, 0x01}, // channel =  44, Tf = 5220MHz (34)
    274. 

  274.     {0x05, 0x55, 0x51}, // channel =  46, Tf = 5230MHz (35)
    275. 

  275.     {0x0A, 0xAA, 0xA1}, // channel =  48, Tf = 5240MHz (36)
    276. 

  276.     {0x15, 0x55, 0x51}, // channel =  52, Tf = 5260MHz (37)
    277. 

  277.     {0x00, 0x00, 0x01}, // channel =  56, Tf = 5280MHz (38)
    278. 

  278.     {0x0A, 0xAA, 0xA1}, // channel =  60, Tf = 5300MHz (39)
    279. 

  279.     {0x15, 0x55, 0x51}, // channel =  64, Tf = 5320MHz (40)
    280. 

  280.     {0x15, 0x55, 0x51}, // channel = 100, Tf = 5500MHz (41)
    281. 

  281.     {0x00, 0x00, 0x01}, // channel = 104, Tf = 5520MHz (42)
    282. 

  282.     {0x0A, 0xAA, 0xA1}, // channel = 108, Tf = 5540MHz (43)
    283. 

  283.     {0x15, 0x55, 0x51}, // channel = 112, Tf = 5560MHz (44)
    284. 

  284.     {0x00, 0x00, 0x01}, // channel = 116, Tf = 5580MHz (45)
    285. 

  285.     {0x0A, 0xAA, 0xA1}, // channel = 120, Tf = 5600MHz (46)
    286. 

  286.     {0x15, 0x55, 0x51}, // channel = 124, Tf = 5620MHz (47)
    287. 

  287.     {0x00, 0x00, 0x01}, // channel = 128, Tf = 5640MHz (48)
    288. 

  288.     {0x0A, 0xAA, 0xA1}, // channel = 132, Tf = 5660MHz (49)
    289. 

  289.     {0x15, 0x55, 0x51}, // channel = 136, Tf = 5680MHz (50)
    290. 

  290.     {0x00, 0x00, 0x01}, // channel = 140, Tf = 5700MHz (51)
    291. 

  291.     {0x18, 0x00, 0x01}, // channel = 149, Tf = 5745MHz (52)
    292. 

  292.     {0x02, 0xAA, 0xA1}, // channel = 153, Tf = 5765MHz (53)
    293. 

  293.     {0x0D, 0x55, 0x51}, // channel = 157, Tf = 5785MHz (54)
    294. 

  294.     {0x18, 0x00, 0x01}, // channel = 161, Tf = 5805MHz (55)
    295. 

  295.     {0x02, 0xAA, 0xB1}  // channel = 165, Tf = 5825MHz (56)
    296. 

  296.     };
    297. 

  297. 

  298. BYTE abyAL7230ChannelTable2[CB_MAX_CHANNEL][3] = {
    299. 

  299.     {0x7F, 0xD7, 0x84}, // channel =  1, Tf = 2412MHz
    300. 

  300.     {0x7F, 0xD7, 0x84}, // channel =  2, Tf = 2417MHz
    301. 

  301.     {0x7F, 0xD7, 0x84}, // channel =  3, Tf = 2422MHz
    302. 

  302.     {0x7F, 0xD7, 0x84}, // channel =  4, Tf = 2427MHz
    303. 

  303.     {0x7F, 0xD7, 0x84}, // channel =  5, Tf = 2432MHz
    304. 

  304.     {0x7F, 0xD7, 0x84}, // channel =  6, Tf = 2437MHz
    305. 

  305.     {0x7F, 0xD7, 0x84}, // channel =  7, Tf = 2442MHz
    306. 

  306.     {0x7F, 0xD7, 0x84}, // channel =  8, Tf = 2447MHz
    307. 

  307.     {0x7F, 0xD7, 0x84}, // channel =  9, Tf = 2452MHz
    308. 

  308.     {0x7F, 0xD7, 0x84}, // channel = 10, Tf = 2457MHz
    309. 

  309.     {0x7F, 0xD7, 0x84}, // channel = 11, Tf = 2462MHz
    310. 

  310.     {0x7F, 0xD7, 0x84}, // channel = 12, Tf = 2467MHz
    311. 

  311.     {0x7F, 0xD7, 0x84}, // channel = 13, Tf = 2472MHz
    312. 

  312.     {0x7F, 0xD7, 0x84}, // channel = 14, Tf = 2484MHz
    313. 

  313. 

  314.     // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196  (Value:15 ~ 22)
    315. 

  315.     {0x7F, 0xD7, 0x84}, // channel = 183, Tf = 4915MHz (15)
    316. 

  316.     {0x6F, 0xD7, 0x84}, // channel = 184, Tf = 4920MHz (16)
    317. 

  317.     {0x7F, 0xD7, 0x84}, // channel = 185, Tf = 4925MHz (17)
    318. 

  318.     {0x7F, 0xD7, 0x84}, // channel = 187, Tf = 4935MHz (18)
    319. 

  319.     {0x7F, 0xD7, 0x84}, // channel = 188, Tf = 4940MHz (19)
    320. 

  320.     {0x7F, 0xD7, 0x84}, // channel = 189, Tf = 4945MHz (20)
    321. 

  321.     {0x7F, 0xD7, 0x84}, // channel = 192, Tf = 4960MHz (21)
    322. 

  322.     {0x6F, 0xD7, 0x84}, // channel = 196, Tf = 4980MHz (22)
    323. 

  323. 

  324.     // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
    325. 

  325.     // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165  (Value 23 ~ 56)
    326. 

  326.     {0x7F, 0xD7, 0x84}, // channel =   7, Tf = 5035MHz (23)
    327. 

  327.     {0x6F, 0xD7, 0x84}, // channel =   8, Tf = 5040MHz (24)
    328. 

  328.     {0x7F, 0xD7, 0x84}, // channel =   9, Tf = 5045MHz (25)
    329. 

  329.     {0x7F, 0xD7, 0x84}, // channel =  11, Tf = 5055MHz (26)
    330. 

  330.     {0x7F, 0xD7, 0x84}, // channel =  12, Tf = 5060MHz (27)
    331. 

  331.     {0x7F, 0xD7, 0x84}, // channel =  16, Tf = 5080MHz (28)
    332. 

  332.     {0x7F, 0xD7, 0x84}, // channel =  34, Tf = 5170MHz (29)
    333. 

  333.     {0x7F, 0xD7, 0x84}, // channel =  36, Tf = 5180MHz (30)
    334. 

  334.     {0x7F, 0xD7, 0x84}, // channel =  38, Tf = 5190MHz (31)
    335. 

  335.     {0x7F, 0xD7, 0x84}, // channel =  40, Tf = 5200MHz (32)
    336. 

  336.     {0x7F, 0xD7, 0x84}, // channel =  42, Tf = 5210MHz (33)
    337. 

  337.     {0x6F, 0xD7, 0x84}, // channel =  44, Tf = 5220MHz (34)
    338. 

  338.     {0x7F, 0xD7, 0x84}, // channel =  46, Tf = 5230MHz (35)
    339. 

  339.     {0x7F, 0xD7, 0x84}, // channel =  48, Tf = 5240MHz (36)
    340. 

  340.     {0x7F, 0xD7, 0x84}, // channel =  52, Tf = 5260MHz (37)
    341. 

  341.     {0x6F, 0xD7, 0x84}, // channel =  56, Tf = 5280MHz (38)
    342. 

  342.     {0x7F, 0xD7, 0x84}, // channel =  60, Tf = 5300MHz (39)
    343. 

  343.     {0x7F, 0xD7, 0x84}, // channel =  64, Tf = 5320MHz (40)
    344. 

  344.     {0x7F, 0xD7, 0x84}, // channel = 100, Tf = 5500MHz (41)
    345. 

  345.     {0x6F, 0xD7, 0x84}, // channel = 104, Tf = 5520MHz (42)
    346. 

  346.     {0x7F, 0xD7, 0x84}, // channel = 108, Tf = 5540MHz (43)
    347. 

  347.     {0x7F, 0xD7, 0x84}, // channel = 112, Tf = 5560MHz (44)
    348. 

  348.     {0x6F, 0xD7, 0x84}, // channel = 116, Tf = 5580MHz (45)
    349. 

  349.     {0x7F, 0xD7, 0x84}, // channel = 120, Tf = 5600MHz (46)
    350. 

  350.     {0x7F, 0xD7, 0x84}, // channel = 124, Tf = 5620MHz (47)
    351. 

  351.     {0x6F, 0xD7, 0x84}, // channel = 128, Tf = 5640MHz (48)
    352. 

  352.     {0x7F, 0xD7, 0x84}, // channel = 132, Tf = 5660MHz (49)
    353. 

  353.     {0x7F, 0xD7, 0x84}, // channel = 136, Tf = 5680MHz (50)
    354. 

  354.     {0x6F, 0xD7, 0x84}, // channel = 140, Tf = 5700MHz (51)
    355. 

  355.     {0x7F, 0xD7, 0x84}, // channel = 149, Tf = 5745MHz (52)
    356. 

  356.     {0x7F, 0xD7, 0x84}, // channel = 153, Tf = 5765MHz (53)
    357. 

  357.     {0x7F, 0xD7, 0x84}, // channel = 157, Tf = 5785MHz (54)
    358. 

  358.     {0x7F, 0xD7, 0x84}, // channel = 161, Tf = 5805MHz (55)
    359. 

  359.     {0x7F, 0xD7, 0x84}  // channel = 165, Tf = 5825MHz (56)
    360. 

  360.     };
    361. 

  361. 

  362. ///{{RobertYu:20051111
    363. 

  363. BYTE abyVT3226_InitTable[CB_VT3226_INIT_SEQ][3] = {
    364. 

  364.     {0x03, 0xFF, 0x80},
    365. 

  365.     {0x02, 0x82, 0xA1},
    366. 

  366.     {0x03, 0xC6, 0xA2},
    367. 

  367.     {0x01, 0x97, 0x93},
    368. 

  368.     {0x03, 0x66, 0x64},
    369. 

  369.     {0x00, 0x61, 0xA5},
    370. 

  370.     {0x01, 0x7B, 0xD6},
    371. 

  371.     {0x00, 0x80, 0x17},
    372. 

  372.     {0x03, 0xF8, 0x08},
    373. 

  373.     {0x00, 0x02, 0x39},   //RobertYu:20051116
    374. 

  374.     {0x02, 0x00, 0x2A}
    375. 

  375.     };
    376. 

  376. 

  377. BYTE abyVT3226D0_InitTable[CB_VT3226_INIT_SEQ][3] = {
    378. 

  378.     {0x03, 0xFF, 0x80},
    379. 

  379.     {0x03, 0x02, 0x21}, //RobertYu:20060327
    380. 

  380.     {0x03, 0xC6, 0xA2},
    381. 

  381.     {0x01, 0x97, 0x93},
    382. 

  382.     {0x03, 0x66, 0x64},
    383. 

  383.     {0x00, 0x71, 0xA5}, //RobertYu:20060103
    384. 

  384.     {0x01, 0x15, 0xC6}, //RobertYu:20060420
    385. 

  385.     {0x01, 0x2E, 0x07}, //RobertYu:20060420
    386. 

  386.     {0x00, 0x58, 0x08}, //RobertYu:20060111
    387. 

  387.     {0x00, 0x02, 0x79}, //RobertYu:20060420
    388. 

  388.     {0x02, 0x01, 0xAA}  //RobertYu:20060523
    389. 

  389.     };
    390. 

  390. 

  391. 

  392. BYTE abyVT3226_ChannelTable0[CB_MAX_CHANNEL_24G][3] = {
    393. 

  393.     {0x01, 0x97, 0x83}, // channel = 1, Tf = 2412MHz
    394. 

  394.     {0x01, 0x97, 0x83}, // channel = 2, Tf = 2417MHz
    395. 

  395.     {0x01, 0x97, 0x93}, // channel = 3, Tf = 2422MHz
    396. 

  396.     {0x01, 0x97, 0x93}, // channel = 4, Tf = 2427MHz
    397. 

  397.     {0x01, 0x97, 0x93}, // channel = 5, Tf = 2432MHz
    398. 

  398.     {0x01, 0x97, 0x93}, // channel = 6, Tf = 2437MHz
    399. 

  399.     {0x01, 0x97, 0xA3}, // channel = 7, Tf = 2442MHz
    400. 

  400.     {0x01, 0x97, 0xA3}, // channel = 8, Tf = 2447MHz
    401. 

  401.     {0x01, 0x97, 0xA3}, // channel = 9, Tf = 2452MHz
    402. 

  402.     {0x01, 0x97, 0xA3}, // channel = 10, Tf = 2457MHz
    403. 

  403.     {0x01, 0x97, 0xB3}, // channel = 11, Tf = 2462MHz
    404. 

  404.     {0x01, 0x97, 0xB3}, // channel = 12, Tf = 2467MHz
    405. 

  405.     {0x01, 0x97, 0xB3}, // channel = 13, Tf = 2472MHz
    406. 

  406.     {0x03, 0x37, 0xC3}  // channel = 14, Tf = 2484MHz
    407. 

  407.     };
    408. 

  408. 

  409. BYTE abyVT3226_ChannelTable1[CB_MAX_CHANNEL_24G][3] = {
    410. 

  410.     {0x02, 0x66, 0x64}, // channel = 1, Tf = 2412MHz
    411. 

  411.     {0x03, 0x66, 0x64}, // channel = 2, Tf = 2417MHz
    412. 

  412.     {0x00, 0x66, 0x64}, // channel = 3, Tf = 2422MHz
    413. 

  413.     {0x01, 0x66, 0x64}, // channel = 4, Tf = 2427MHz
    414. 

  414.     {0x02, 0x66, 0x64}, // channel = 5, Tf = 2432MHz
    415. 

  415.     {0x03, 0x66, 0x64}, // channel = 6, Tf = 2437MHz
    416. 

  416.     {0x00, 0x66, 0x64}, // channel = 7, Tf = 2442MHz
    417. 

  417.     {0x01, 0x66, 0x64}, // channel = 8, Tf = 2447MHz
    418. 

  418.     {0x02, 0x66, 0x64}, // channel = 9, Tf = 2452MHz
    419. 

  419.     {0x03, 0x66, 0x64}, // channel = 10, Tf = 2457MHz
    420. 

  420.     {0x00, 0x66, 0x64}, // channel = 11, Tf = 2462MHz
    421. 

  421.     {0x01, 0x66, 0x64}, // channel = 12, Tf = 2467MHz
    422. 

  422.     {0x02, 0x66, 0x64}, // channel = 13, Tf = 2472MHz
    423. 

  423.     {0x00, 0xCC, 0xC4}  // channel = 14, Tf = 2484MHz
    424. 

  424.     };
    425. 

  425. ///}}RobertYu
    426. 

  426. 

  427. 

  428. //{{RobertYu:20060502, TWIF 1.14, LO Current for 11b mode
    429. 

  429. DWORD dwVT3226D0LoCurrentTable[CB_MAX_CHANNEL_24G] = {
    430. 

  430.     0x0135C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 1, Tf = 2412MHz
    431. 

  431.     0x0135C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 2, Tf = 2417MHz
    432. 

  432.     0x0235C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 3, Tf = 2422MHz
    433. 

  433.     0x0235C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 4, Tf = 2427MHz
    434. 

  434.     0x0235C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 5, Tf = 2432MHz
    435. 

  435.     0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 6, Tf = 2437MHz
    436. 

  436.     0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 7, Tf = 2442MHz
    437. 

  437.     0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 8, Tf = 2447MHz
    438. 

  438.     0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 9, Tf = 2452MHz
    439. 

  439.     0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 10, Tf = 2457MHz
    440. 

  440.     0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 11, Tf = 2462MHz
    441. 

  441.     0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 12, Tf = 2467MHz
    442. 

  442.     0x0335C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW, // channel = 13, Tf = 2472MHz
    443. 

  443.     0x0135C600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW  // channel = 14, Tf = 2484MHz
    444. 

  444. };
    445. 

  445. //}}
    446. 

  446. 

  447. 

  448. //{{RobertYu:20060609
    449. 

  449. BYTE abyVT3342A0_InitTable[CB_VT3342_INIT_SEQ][3] = { // 11b/g mode
    450. 

  450.     {0x03, 0xFF, 0x80}, //update for mode//
    451. 

  451.     {0x02, 0x08, 0x81},
    452. 

  452.     {0x00, 0xC6, 0x02},
    453. 

  453.     {0x03, 0xC5, 0x13}, // channel6
    454. 

  454.     {0x00, 0xEE, 0xE4}, // channel6
    455. 

  455.     {0x00, 0x71, 0xA5},
    456. 

  456.     {0x01, 0x75, 0x46},
    457. 

  457.     {0x01, 0x40, 0x27},
    458. 

  458.     {0x01, 0x54, 0x08},
    459. 

  459.     {0x00, 0x01, 0x69},
    460. 

  460.     {0x02, 0x00, 0xAA},
    461. 

  461.     {0x00, 0x08, 0xCB},
    462. 

  462.     {0x01, 0x70, 0x0C}
    463. 

  463.     };
    464. 

  464. 

  465.  //11b/g mode: 0x03, 0xFF, 0x80,
    466. 

  466.  //11a mode:   0x03, 0xFF, 0xC0,
    467. 

  467. 

  468.  // channel44, 5220MHz  0x00C402
    469. 

  469.  // channel56, 5280MHz  0x00C402 for disable Frac
    470. 

  470.  // other channels 0x00C602
    471. 

  471. 

  472. BYTE abyVT3342_ChannelTable0[CB_MAX_CHANNEL][3] = {
    473. 

  473.     {0x02, 0x05, 0x03}, // channel = 1, Tf = 2412MHz
    474. 

  474.     {0x01, 0x15, 0x03}, // channel = 2, Tf = 2417MHz
    475. 

  475.     {0x03, 0xC5, 0x03}, // channel = 3, Tf = 2422MHz
    476. 

  476.     {0x02, 0x65, 0x03}, // channel = 4, Tf = 2427MHz
    477. 

  477.     {0x01, 0x15, 0x13}, // channel = 5, Tf = 2432MHz
    478. 

  478.     {0x03, 0xC5, 0x13}, // channel = 6, Tf = 2437MHz
    479. 

  479.     {0x02, 0x05, 0x13}, // channel = 7, Tf = 2442MHz
    480. 

  480.     {0x01, 0x15, 0x13}, // channel = 8, Tf = 2447MHz
    481. 

  481.     {0x03, 0xC5, 0x13}, // channel = 9, Tf = 2452MHz
    482. 

  482.     {0x02, 0x65, 0x13}, // channel = 10, Tf = 2457MHz
    483. 

  483.     {0x01, 0x15, 0x23}, // channel = 11, Tf = 2462MHz
    484. 

  484.     {0x03, 0xC5, 0x23}, // channel = 12, Tf = 2467MHz
    485. 

  485.     {0x02, 0x05, 0x23}, // channel = 13, Tf = 2472MHz
    486. 

  486.     {0x00, 0xD5, 0x23}, // channel = 14, Tf = 2484MHz
    487. 

  487. 

  488.     // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196  (Value:15 ~ 22)
    489. 

  489.     {0x01, 0x15, 0x13}, // channel = 183, Tf = 4915MHz (15), TBD
    490. 

  490.     {0x01, 0x15, 0x13}, // channel = 184, Tf = 4920MHz (16), TBD
    491. 

  491.     {0x01, 0x15, 0x13}, // channel = 185, Tf = 4925MHz (17), TBD
    492. 

  492.     {0x01, 0x15, 0x13}, // channel = 187, Tf = 4935MHz (18), TBD
    493. 

  493.     {0x01, 0x15, 0x13}, // channel = 188, Tf = 4940MHz (19), TBD
    494. 

  494.     {0x01, 0x15, 0x13}, // channel = 189, Tf = 4945MHz (20), TBD
    495. 

  495.     {0x01, 0x15, 0x13}, // channel = 192, Tf = 4960MHz (21), TBD
    496. 

  496.     {0x01, 0x15, 0x13}, // channel = 196, Tf = 4980MHz (22), TBD
    497. 

  497. 

  498.     // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
    499. 

  499.     // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165  (Value 23 ~ 56)
    500. 

  500.     {0x01, 0x15, 0x13}, // channel =   7, Tf = 5035MHz (23), TBD
    501. 

  501.     {0x01, 0x15, 0x13}, // channel =   8, Tf = 5040MHz (24), TBD
    502. 

  502.     {0x01, 0x15, 0x13}, // channel =   9, Tf = 5045MHz (25), TBD
    503. 

  503.     {0x01, 0x15, 0x13}, // channel =  11, Tf = 5055MHz (26), TBD
    504. 

  504.     {0x01, 0x15, 0x13}, // channel =  12, Tf = 5060MHz (27), TBD
    505. 

  505.     {0x01, 0x15, 0x13}, // channel =  16, Tf = 5080MHz (28), TBD
    506. 

  506.     {0x01, 0x15, 0x13}, // channel =  34, Tf = 5170MHz (29), TBD
    507. 

  507.     {0x01, 0x55, 0x63}, // channel =  36, Tf = 5180MHz (30)
    508. 

  508.     {0x01, 0x55, 0x63}, // channel =  38, Tf = 5190MHz (31), TBD
    509. 

  509.     {0x02, 0xA5, 0x63}, // channel =  40, Tf = 5200MHz (32)
    510. 

  510.     {0x02, 0xA5, 0x63}, // channel =  42, Tf = 5210MHz (33), TBD
    511. 

  511.     {0x00, 0x05, 0x73}, // channel =  44, Tf = 5220MHz (34)
    512. 

  512.     {0x00, 0x05, 0x73}, // channel =  46, Tf = 5230MHz (35), TBD
    513. 

  513.     {0x01, 0x55, 0x73}, // channel =  48, Tf = 5240MHz (36)
    514. 

  514.     {0x02, 0xA5, 0x73}, // channel =  52, Tf = 5260MHz (37)
    515. 

  515.     {0x00, 0x05, 0x83}, // channel =  56, Tf = 5280MHz (38)
    516. 

  516.     {0x01, 0x55, 0x83}, // channel =  60, Tf = 5300MHz (39)
    517. 

  517.     {0x02, 0xA5, 0x83}, // channel =  64, Tf = 5320MHz (40)
    518. 

  518. 

  519.     {0x02, 0xA5, 0x83}, // channel = 100, Tf = 5500MHz (41), TBD
    520. 

  520.     {0x02, 0xA5, 0x83}, // channel = 104, Tf = 5520MHz (42), TBD
    521. 

  521.     {0x02, 0xA5, 0x83}, // channel = 108, Tf = 5540MHz (43), TBD
    522. 

  522.     {0x02, 0xA5, 0x83}, // channel = 112, Tf = 5560MHz (44), TBD
    523. 

  523.     {0x02, 0xA5, 0x83}, // channel = 116, Tf = 5580MHz (45), TBD
    524. 

  524.     {0x02, 0xA5, 0x83}, // channel = 120, Tf = 5600MHz (46), TBD
    525. 

  525.     {0x02, 0xA5, 0x83}, // channel = 124, Tf = 5620MHz (47), TBD
    526. 

  526.     {0x02, 0xA5, 0x83}, // channel = 128, Tf = 5640MHz (48), TBD
    527. 

  527.     {0x02, 0xA5, 0x83}, // channel = 132, Tf = 5660MHz (49), TBD
    528. 

  528.     {0x02, 0xA5, 0x83}, // channel = 136, Tf = 5680MHz (50), TBD
    529. 

  529.     {0x02, 0xA5, 0x83}, // channel = 140, Tf = 5700MHz (51), TBD
    530. 

  530. 

  531.     {0x00, 0x05, 0xF3}, // channel = 149, Tf = 5745MHz (52)
    532. 

  532.     {0x01, 0x56, 0x03}, // channel = 153, Tf = 5765MHz (53)
    533. 

  533.     {0x02, 0xA6, 0x03}, // channel = 157, Tf = 5785MHz (54)
    534. 

  534.     {0x00, 0x06, 0x03}, // channel = 161, Tf = 5805MHz (55)
    535. 

  535.     {0x00, 0x06, 0x03}  // channel = 165, Tf = 5825MHz (56), TBD
    536. 

  536.     };
    537. 

  537. 

  538. BYTE abyVT3342_ChannelTable1[CB_MAX_CHANNEL][3] = {
    539. 

  539.     {0x01, 0x99, 0x94}, // channel = 1, Tf = 2412MHz
    540. 

  540.     {0x02, 0x44, 0x44}, // channel = 2, Tf = 2417MHz
    541. 

  541.     {0x02, 0xEE, 0xE4}, // channel = 3, Tf = 2422MHz
    542. 

  542.     {0x03, 0x99, 0x94}, // channel = 4, Tf = 2427MHz
    543. 

  543.     {0x00, 0x44, 0x44}, // channel = 5, Tf = 2432MHz
    544. 

  544.     {0x00, 0xEE, 0xE4}, // channel = 6, Tf = 2437MHz
    545. 

  545.     {0x01, 0x99, 0x94}, // channel = 7, Tf = 2442MHz
    546. 

  546.     {0x02, 0x44, 0x44}, // channel = 8, Tf = 2447MHz
    547. 

  547.     {0x02, 0xEE, 0xE4}, // channel = 9, Tf = 2452MHz
    548. 

  548.     {0x03, 0x99, 0x94}, // channel = 10, Tf = 2457MHz
    549. 

  549.     {0x00, 0x44, 0x44}, // channel = 11, Tf = 2462MHz
    550. 

  550.     {0x00, 0xEE, 0xE4}, // channel = 12, Tf = 2467MHz
    551. 

  551.     {0x01, 0x99, 0x94}, // channel = 13, Tf = 2472MHz
    552. 

  552.     {0x03, 0x33, 0x34}, // channel = 14, Tf = 2484MHz
    553. 

  553. 

  554.     // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196  (Value:15 ~ 22)
    555. 

  555.     {0x00, 0x44, 0x44}, // channel = 183, Tf = 4915MHz (15), TBD
    556. 

  556.     {0x00, 0x44, 0x44}, // channel = 184, Tf = 4920MHz (16), TBD
    557. 

  557.     {0x00, 0x44, 0x44}, // channel = 185, Tf = 4925MHz (17), TBD
    558. 

  558.     {0x00, 0x44, 0x44}, // channel = 187, Tf = 4935MHz (18), TBD
    559. 

  559.     {0x00, 0x44, 0x44}, // channel = 188, Tf = 4940MHz (19), TBD
    560. 

  560.     {0x00, 0x44, 0x44}, // channel = 189, Tf = 4945MHz (20), TBD
    561. 

  561.     {0x00, 0x44, 0x44}, // channel = 192, Tf = 4960MHz (21), TBD
    562. 

  562.     {0x00, 0x44, 0x44}, // channel = 196, Tf = 4980MHz (22), TBD
    563. 

  563. 

  564.     // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
    565. 

  565.     // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165  (Value 23 ~ 56)
    566. 

  566.     {0x00, 0x44, 0x44}, // channel =   7, Tf = 5035MHz (23), TBD
    567. 

  567.     {0x00, 0x44, 0x44}, // channel =   8, Tf = 5040MHz (24), TBD
    568. 

  568.     {0x00, 0x44, 0x44}, // channel =   9, Tf = 5045MHz (25), TBD
    569. 

  569.     {0x00, 0x44, 0x44}, // channel =  11, Tf = 5055MHz (26), TBD
    570. 

  570.     {0x00, 0x44, 0x44}, // channel =  12, Tf = 5060MHz (27), TBD
    571. 

  571.     {0x00, 0x44, 0x44}, // channel =  16, Tf = 5080MHz (28), TBD
    572. 

  572.     {0x00, 0x44, 0x44}, // channel =  34, Tf = 5170MHz (29), TBD
    573. 

  573.     {0x01, 0x55, 0x54}, // channel =  36, Tf = 5180MHz (30)
    574. 

  574.     {0x01, 0x55, 0x54}, // channel =  38, Tf = 5190MHz (31), TBD
    575. 

  575.     {0x02, 0xAA, 0xA4}, // channel =  40, Tf = 5200MHz (32)
    576. 

  576.     {0x02, 0xAA, 0xA4}, // channel =  42, Tf = 5210MHz (33), TBD
    577. 

  577.     {0x00, 0x00, 0x04}, // channel =  44, Tf = 5220MHz (34)
    578. 

  578.     {0x00, 0x00, 0x04}, // channel =  46, Tf = 5230MHz (35), TBD
    579. 

  579.     {0x01, 0x55, 0x54}, // channel =  48, Tf = 5240MHz (36)
    580. 

  580.     {0x02, 0xAA, 0xA4}, // channel =  52, Tf = 5260MHz (37)
    581. 

  581.     {0x00, 0x00, 0x04}, // channel =  56, Tf = 5280MHz (38)
    582. 

  582.     {0x01, 0x55, 0x54}, // channel =  60, Tf = 5300MHz (39)
    583. 

  583.     {0x02, 0xAA, 0xA4}, // channel =  64, Tf = 5320MHz (40)
    584. 

  584.     {0x02, 0xAA, 0xA4}, // channel = 100, Tf = 5500MHz (41), TBD
    585. 

  585.     {0x02, 0xAA, 0xA4}, // channel = 104, Tf = 5520MHz (42), TBD
    586. 

  586.     {0x02, 0xAA, 0xA4}, // channel = 108, Tf = 5540MHz (43), TBD
    587. 

  587.     {0x02, 0xAA, 0xA4}, // channel = 112, Tf = 5560MHz (44), TBD
    588. 

  588.     {0x02, 0xAA, 0xA4}, // channel = 116, Tf = 5580MHz (45), TBD
    589. 

  589.     {0x02, 0xAA, 0xA4}, // channel = 120, Tf = 5600MHz (46), TBD
    590. 

  590.     {0x02, 0xAA, 0xA4}, // channel = 124, Tf = 5620MHz (47), TBD
    591. 

  591.     {0x02, 0xAA, 0xA4}, // channel = 128, Tf = 5640MHz (48), TBD
    592. 

  592.     {0x02, 0xAA, 0xA4}, // channel = 132, Tf = 5660MHz (49), TBD
    593. 

  593.     {0x02, 0xAA, 0xA4}, // channel = 136, Tf = 5680MHz (50), TBD
    594. 

  594.     {0x02, 0xAA, 0xA4}, // channel = 140, Tf = 5700MHz (51), TBD
    595. 

  595.     {0x03, 0x00, 0x04}, // channel = 149, Tf = 5745MHz (52)
    596. 

  596.     {0x00, 0x55, 0x54}, // channel = 153, Tf = 5765MHz (53)
    597. 

  597.     {0x01, 0xAA, 0xA4}, // channel = 157, Tf = 5785MHz (54)
    598. 

  598.     {0x03, 0x00, 0x04}, // channel = 161, Tf = 5805MHz (55)
    599. 

  599.     {0x03, 0x00, 0x04}  // channel = 165, Tf = 5825MHz (56), TBD
    600. 

  600.     };
    601. 

  601. 

  602. 

  603. /*+
    604. 

  604.  *
    605. 

  605.  * Power Table
    606. 

  606.  *
    607. 

  607. -*/
    608. 

  608. 

  609. const DWORD dwAL2230PowerTable[AL2230_PWR_IDX_LEN] = {
    610. 

  610.     0x04040900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    611. 

  611.     0x04041900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    612. 

  612.     0x04042900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    613. 

  613.     0x04043900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    614. 

  614.     0x04044900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    615. 

  615.     0x04045900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    616. 

  616.     0x04046900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    617. 

  617.     0x04047900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    618. 

  618.     0x04048900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    619. 

  619.     0x04049900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    620. 

  620.     0x0404A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    621. 

  621.     0x0404B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    622. 

  622.     0x0404C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    623. 

  623.     0x0404D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    624. 

  624.     0x0404E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    625. 

  625.     0x0404F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    626. 

  626.     0x04050900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    627. 

  627.     0x04051900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    628. 

  628.     0x04052900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    629. 

  629.     0x04053900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    630. 

  630.     0x04054900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    631. 

  631.     0x04055900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    632. 

  632.     0x04056900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    633. 

  633.     0x04057900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    634. 

  634.     0x04058900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    635. 

  635.     0x04059900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    636. 

  636.     0x0405A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    637. 

  637.     0x0405B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    638. 

  638.     0x0405C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    639. 

  639.     0x0405D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    640. 

  640.     0x0405E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    641. 

  641.     0x0405F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    642. 

  642.     0x04060900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    643. 

  643.     0x04061900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    644. 

  644.     0x04062900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    645. 

  645.     0x04063900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    646. 

  646.     0x04064900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    647. 

  647.     0x04065900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    648. 

  648.     0x04066900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    649. 

  649.     0x04067900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    650. 

  650.     0x04068900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    651. 

  651.     0x04069900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    652. 

  652.     0x0406A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    653. 

  653.     0x0406B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    654. 

  654.     0x0406C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    655. 

  655.     0x0406D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    656. 

  656.     0x0406E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    657. 

  657.     0x0406F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    658. 

  658.     0x04070900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    659. 

  659.     0x04071900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    660. 

  660.     0x04072900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    661. 

  661.     0x04073900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    662. 

  662.     0x04074900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    663. 

  663.     0x04075900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    664. 

  664.     0x04076900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    665. 

  665.     0x04077900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    666. 

  666.     0x04078900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    667. 

  667.     0x04079900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    668. 

  668.     0x0407A900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    669. 

  669.     0x0407B900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    670. 

  670.     0x0407C900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    671. 

  671.     0x0407D900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    672. 

  672.     0x0407E900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW,
    673. 

  673.     0x0407F900+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW
    674. 

  674.     };
    675. 

  675. 

  676. /*---------------------  Static Functions  --------------------------*/
    677. 

  677. 

  678. /*---------------------  Export Variables  --------------------------*/
    679. 

  679. 

  680. //{{ RobertYu:20050103, Channel 11a Number To Index
    681. 

  681. // 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196  (Value:15 ~ 22)
    682. 

  682. // 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64,
    683. 

  683. // 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165  (Value 23 ~ 56)
    684. 

  684. 

  685. const BYTE RFaby11aChannelIndex[200] = {
    686. 

  686.   // 1   2   3   4   5   6   7   8   9  10
    687. 

  687.     00, 00, 00, 00, 00, 00, 23, 24, 25, 00,  // 10
    688. 

  688.     26, 27, 00, 00, 00, 28, 00, 00, 00, 00,  // 20
    689. 

  689.     00, 00, 00, 00, 00, 00, 00, 00, 00, 00,  // 30
    690. 

  690.     00, 00, 00, 29, 00, 30, 00, 31, 00, 32,  // 40
    691. 

  691.     00, 33, 00, 34, 00, 35, 00, 36, 00, 00,  // 50
    692. 

  692.     00, 37, 00, 00, 00, 38, 00, 00, 00, 39,  // 60
    693. 

  693.     00, 00, 00, 40, 00, 00, 00, 00, 00, 00,  // 70
    694. 

  694.     00, 00, 00, 00, 00, 00, 00, 00, 00, 00,  // 80
    695. 

  695.     00, 00, 00, 00, 00, 00, 00, 00, 00, 00,  // 90
    696. 

  696.     00, 00, 00, 00, 00, 00, 00, 00, 00, 41,  //100
    697. 

  697. 

  698.     00, 00, 00, 42, 00, 00, 00, 43, 00, 00,  //110
    699. 

  699.     00, 44, 00, 00, 00, 45, 00, 00, 00, 46,  //120
    700. 

  700.     00, 00, 00, 47, 00, 00, 00, 48, 00, 00,  //130
    701. 

  701.     00, 49, 00, 00, 00, 50, 00, 00, 00, 51,  //140
    702. 

  702.     00, 00, 00, 00, 00, 00, 00, 00, 52, 00,  //150
    703. 

  703.     00, 00, 53, 00, 00, 00, 54, 00, 00, 00,  //160
    704. 

  704.     55, 00, 00, 00, 56, 00, 00, 00, 00, 00,  //170
    705. 

  705.     00, 00, 00, 00, 00, 00, 00, 00, 00, 00,  //180
    706. 

  706.     00, 00, 15, 16, 17, 00, 18, 19, 20, 00,  //190
    707. 

  707.     00, 21, 00, 00, 00, 22, 00, 00, 00, 00   //200
    708. 

  708. };
    709. 

  709. //}} RobertYu
    710. 

  710. 

  711. /*---------------------  Export Functions  --------------------------*/
    712. 

  712. 

  713. /*
    714. 

  714.  * Description: Write to IF/RF, by embeded programming
    715. 

  715.  *
    716. 

  716.  * Parameters:
    717. 

  717.  *  In:
    718. 

  718.  *      dwData      - data to write
    719. 

  719.  *  Out:
    720. 

  720.  *      none
    721. 

  721.  *
    722. 

  722.  * Return Value: TRUE if succeeded; FALSE if failed.
    723. 

  723.  *
    724. 

  724.  */
    725. 

  725. BOOL IFRFbWriteEmbeded (PSDevice pDevice, DWORD dwData)
    726. 

  726. {
    727. 

  727.     BYTE        pbyData[4];
    728. 

  728. 

  729.     pbyData[0] = (BYTE)dwData;
    730. 

  730.     pbyData[1] = (BYTE)(dwData>>8);
    731. 

  731.     pbyData[2] = (BYTE)(dwData>>16);
    732. 

  732.     pbyData[3] = (BYTE)(dwData>>24);
    733. 

  733.     CONTROLnsRequestOut(pDevice,
    734. 

  734.                     MESSAGE_TYPE_WRITE_IFRF,
    735. 

  735.                     0,
    736. 

  736.                     0,
    737. 

  737.                     4,
    738. 

  738.                     pbyData
    739. 

  739.                         );
    740. 

  740. 

  741. 

  742.     return TRUE;
    743. 

  743. }
    744. 

  744. 

  745. 

  746. /*
    747. 

  747.  * Description: Set Tx power
    748. 

  748.  *
    749. 

  749.  * Parameters:
    750. 

  750.  *  In:
    751. 

  751.  *      dwIoBase       - I/O base address
    752. 

  752.  *      dwRFPowerTable - RF Tx Power Setting
    753. 

  753.  *  Out:
    754. 

  754.  *      none
    755. 

  755.  *
    756. 

  756.  * Return Value: TRUE if succeeded; FALSE if failed.
    757. 

  757.  *
    758. 

  758.  */
    759. 

  759. BOOL RFbSetPower (
    760. 

  760.       PSDevice  pDevice,
    761. 

  761.       unsigned int      uRATE,
    762. 

  762.       unsigned int      uCH
    763. 

  763.     )
    764. 

  764. {
    765. 

  765. BOOL    bResult = TRUE;
    766. 

  766. BYTE    byPwr = pDevice->byCCKPwr;
    767. 

  767. 

  768.     if (pDevice->dwDiagRefCount != 0) {
    769. 

  769.         return TRUE;
    770. 

  770.     }
    771. 

  771. 

  772.     switch (uRATE) {
    773. 

  773.     case RATE_1M:
    774. 

  774.     case RATE_2M:
    775. 

  775.     case RATE_5M:
    776. 

  776.     case RATE_11M:
    777. 

  777.         byPwr = pDevice->abyCCKPwrTbl[uCH-1];
    778. 

  778.         break;
    779. 

  779.     case RATE_6M:
    780. 

  780.     case RATE_9M:
    781. 

  781.     case RATE_18M:
    782. 

  782.     case RATE_24M:
    783. 

  783.     case RATE_36M:
    784. 

  784.     case RATE_48M:
    785. 

  785.     case RATE_54M:
    786. 

  786.         if (uCH > CB_MAX_CHANNEL_24G) {
    787. 

  787.             byPwr = pDevice->abyOFDMAPwrTbl[uCH-15];
    788. 

  788.         } else {
    789. 

  789.             byPwr = pDevice->abyOFDMPwrTbl[uCH-1];
    790. 

  790.         }
    791. 

  791.         break;
    792. 

  792.     }
    793. 

  793. 

  794.     bResult = RFbRawSetPower(pDevice, byPwr, uRATE);
    795. 

  795. 

  796.     return bResult;
    797. 

  797. }
    798. 

  798. 

  799. 

  800. /*
    801. 

  801.  * Description: Set Tx power
    802. 

  802.  *
    803. 

  803.  * Parameters:
    804. 

  804.  *  In:
    805. 

  805.  *      dwIoBase       - I/O base address
    806. 

  806.  *      dwRFPowerTable - RF Tx Power Setting
    807. 

  807.  *  Out:
    808. 

  808.  *      none
    809. 

  809.  *
    810. 

  810.  * Return Value: TRUE if succeeded; FALSE if failed.
    811. 

  811.  *
    812. 

  812.  */
    813. 

  813. BOOL RFbRawSetPower (
    814. 

  814.       PSDevice  pDevice,
    815. 

  815.       BYTE      byPwr,
    816. 

  816.       unsigned int      uRATE
    817. 

  817.     )
    818. 

  818. {
    819. 

  819. BOOL        bResult = TRUE;
    820. 

  820. 

  821.     if (pDevice->byCurPwr == byPwr)
    822. 

  822.         return TRUE;
    823. 

  823. 

  824.     pDevice->byCurPwr = byPwr;
    825. 

  825. 

  826.     switch (pDevice->byRFType) {
    827. 

  827. 

  828.         case RF_AL2230 :
    829. 

  829.             if (pDevice->byCurPwr >= AL2230_PWR_IDX_LEN)
    830. 

  830.                 return FALSE;
    831. 

  831.             bResult &= IFRFbWriteEmbeded(pDevice, dwAL2230PowerTable[pDevice->byCurPwr]);
    832. 

  832.             if (uRATE <= RATE_11M)
    833. 

  833.                 bResult &= IFRFbWriteEmbeded(pDevice, 0x0001B400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
    834. 

  834.             else
    835. 

  835.                 bResult &= IFRFbWriteEmbeded(pDevice, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
    836. 

  836.             break;
    837. 

  837. 

  838.         case RF_AL2230S :
    839. 

  839.             if (pDevice->byCurPwr >= AL2230_PWR_IDX_LEN)
    840. 

  840.                 return FALSE;
    841. 

  841.             bResult &= IFRFbWriteEmbeded(pDevice, dwAL2230PowerTable[pDevice->byCurPwr]);
    842. 

  842.             if (uRATE <= RATE_11M) {
    843. 

  843.                 bResult &= IFRFbWriteEmbeded(pDevice, 0x040C1400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
    844. 

  844.                 bResult &= IFRFbWriteEmbeded(pDevice, 0x00299B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
    845. 

  845.             }else {
    846. 

  846.                 bResult &= IFRFbWriteEmbeded(pDevice, 0x0005A400+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
    847. 

  847.                 bResult &= IFRFbWriteEmbeded(pDevice, 0x00099B00+(BY_AL2230_REG_LEN<<3)+IFREGCTL_REGW);
    848. 

  848.             }
    849. 

  849.             break;
    850. 

  850. 

  851. 

  852.         case RF_AIROHA7230:
    853. 

  853.             {
    854. 

  854.                 DWORD       dwMax7230Pwr;
    855. 

  855. 

  856.                 if (uRATE <= RATE_11M) { //RobertYu:20060426, for better 11b mask
    857. 

  857.                     bResult &= IFRFbWriteEmbeded(pDevice, 0x111BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW);
    858. 

  858.                 }
    859. 

  859.                 else {
    860. 

  860.                     bResult &= IFRFbWriteEmbeded(pDevice, 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW);
    861. 

  861.                 }
    862. 

  862. 

  863.                 if (pDevice->byCurPwr > AL7230_PWR_IDX_LEN) return FALSE;
    864. 

  864. 

  865.                 //  0x080F1B00 for 3 wire control TxGain(D10) and 0x31 as TX Gain value
    866. 

  866.                 dwMax7230Pwr = 0x080C0B00 | ( (pDevice->byCurPwr) << 12 ) |
    867. 

  867.                                  (BY_AL7230_REG_LEN << 3 )  | IFREGCTL_REGW;
    868. 

  868. 

  869.                 bResult &= IFRFbWriteEmbeded(pDevice, dwMax7230Pwr);
    870. 

  870.                 break;
    871. 

  871.             }
    872. 

  872.             break;
    873. 

  873. 

  874.         case RF_VT3226: //RobertYu:20051111, VT3226C0 and before
    875. 

  875.         {
    876. 

  876.             DWORD       dwVT3226Pwr;
    877. 

  877. 

  878.             if (pDevice->byCurPwr >= VT3226_PWR_IDX_LEN)
    879. 

  879.                 return FALSE;
    880. 

  880.             dwVT3226Pwr = ((0x3F-pDevice->byCurPwr) << 20 ) | ( 0x17 << 8 ) /* Reg7 */ |
    881. 

  881.                            (BY_VT3226_REG_LEN << 3 )  | IFREGCTL_REGW;
    882. 

  882.             bResult &= IFRFbWriteEmbeded(pDevice, dwVT3226Pwr);
    883. 

  883.             break;
    884. 

  884.         }
    885. 

  885. 

  886.         case RF_VT3226D0: //RobertYu:20051228
    887. 

  887.         {
    888. 

  888.             DWORD       dwVT3226Pwr;
    889. 

  889. 

  890.             if (pDevice->byCurPwr >= VT3226_PWR_IDX_LEN)
    891. 

  891.                 return FALSE;
    892. 

  892. 

  893.             if (uRATE <= RATE_11M) {
    894. 

  894. 

  895.                 dwVT3226Pwr = ((0x3F-pDevice->byCurPwr) << 20 ) | ( 0xE07 << 8 ) /* Reg7 */ |   //RobertYu:20060420, TWIF 1.10
    896. 

  896.                                (BY_VT3226_REG_LEN << 3 )  | IFREGCTL_REGW;
    897. 

  897.                 bResult &= IFRFbWriteEmbeded(pDevice, dwVT3226Pwr);
    898. 

  898. 

  899.                 bResult &= IFRFbWriteEmbeded(pDevice, 0x03C6A200+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW);
    900. 

  900.                 if (pDevice->sMgmtObj.eScanState != WMAC_NO_SCANNING) {
    901. 

  901.                     // scanning, the channel number is pDevice->uScanChannel
    902. 

  902.                     DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"@@@@ RFbRawSetPower> 11B mode uCurrChannel[%d]\n", pDevice->sMgmtObj.uScanChannel);
    903. 

  903.                     bResult &= IFRFbWriteEmbeded(pDevice, dwVT3226D0LoCurrentTable[pDevice->sMgmtObj.uScanChannel-1]); //RobertYu:20060420, sometimes didn't change channel just set power with different rate
    904. 

  904.                 } else {
    905. 

  905.                     DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"@@@@ RFbRawSetPower> 11B mode uCurrChannel[%d]\n", pDevice->sMgmtObj.uCurrChannel);
    906. 

  906.                     bResult &= IFRFbWriteEmbeded(pDevice, dwVT3226D0LoCurrentTable[pDevice->sMgmtObj.uCurrChannel-1]); //RobertYu:20060420, sometimes didn't change channel just set power with different rate
    907. 

  907.                 }
    908. 

  908. 

  909.                 bResult &= IFRFbWriteEmbeded(pDevice, 0x015C0800+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); //RobertYu:20060420, ok now, new switching power (mini-pci can have bigger power consumption)
    910. 

  910.             } else {
    911. 

  911.                 DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO"@@@@ RFbRawSetPower> 11G mode\n");
    912. 

  912.                 dwVT3226Pwr = ((0x3F-pDevice->byCurPwr) << 20 ) | ( 0x7 << 8 ) /* Reg7 */ |   //RobertYu:20060420, TWIF 1.10
    913. 

  913.                                (BY_VT3226_REG_LEN << 3 )  | IFREGCTL_REGW;
    914. 

  914.                 bResult &= IFRFbWriteEmbeded(pDevice, dwVT3226Pwr);
    915. 

  915.                 bResult &= IFRFbWriteEmbeded(pDevice, 0x00C6A200+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); //RobertYu:20060327
    916. 

  916.                 bResult &= IFRFbWriteEmbeded(pDevice, 0x016BC600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); //RobertYu:20060111
    917. 

  917.                 bResult &= IFRFbWriteEmbeded(pDevice, 0x00900800+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); //RobertYu:20060111
    918. 

  918.             }
    919. 

  919.             break;
    920. 

  920.         }
    921. 

  921. 

  922.         //{{RobertYu:20060609
    923. 

  923.         case RF_VT3342A0:
    924. 

  924.         {
    925. 

  925.             DWORD       dwVT3342Pwr;
    926. 

  926. 

  927.             if (pDevice->byCurPwr >= VT3342_PWR_IDX_LEN)
    928. 

  928.                 return FALSE;
    929. 

  929. 

  930.             dwVT3342Pwr =  ((0x3F-pDevice->byCurPwr) << 20 ) | ( 0x27 << 8 ) /* Reg7 */ |
    931. 

  931.                             (BY_VT3342_REG_LEN << 3 )  | IFREGCTL_REGW;
    932. 

  932.             bResult &= IFRFbWriteEmbeded(pDevice, dwVT3342Pwr);
    933. 

  933.             break;
    934. 

  934.         }
    935. 

  935. 

  936.         default :
    937. 

  937.             break;
    938. 

  938.     }
    939. 

  939.     return bResult;
    940. 

  940. }
    941. 

  941. 

  942. /*+
    943. 

  943.  *
    944. 

  944.  * Routine Description:
    945. 

  945.  *     Translate RSSI to dBm
    946. 

  946.  *
    947. 

  947.  * Parameters:
    948. 

  948.  *  In:
    949. 

  949.  *      pDevice         - The adapter to be translated
    950. 

  950.  *      byCurrRSSI      - RSSI to be translated
    951. 

  951.  *  Out:
    952. 

  952.  *      pdwdbm          - Translated dbm number
    953. 

  953.  *
    954. 

  954.  * Return Value: none
    955. 

  955.  *
    956. 

  956. -*/
    957. 

  957. void
    958. 

  958. RFvRSSITodBm (
    959. 

  959.       PSDevice pDevice,
    960. 

  960.       BYTE     byCurrRSSI,
    961. 

  961.     long *    pldBm
    962. 

  962.     )
    963. 

  963. {
    964. 

  964.     BYTE byIdx = (((byCurrRSSI & 0xC0) >> 6) & 0x03);
    965. 

  965.     signed long b = (byCurrRSSI & 0x3F);
    966. 

  966.     signed long a = 0;
    967. 

  967.     BYTE abyAIROHARF[4] = {0, 18, 0, 40};
    968. 

  968. 

  969.     switch (pDevice->byRFType) {
    970. 

  970.         case RF_AL2230:
    971. 

  971.         case RF_AL2230S:
    972. 

  972.         case RF_AIROHA7230:
    973. 

  973.         case RF_VT3226: //RobertYu:20051111
    974. 

  974.         case RF_VT3226D0:
    975. 

  975.         case RF_VT3342A0:   //RobertYu:20060609
    976. 

  976.             a = abyAIROHARF[byIdx];
    977. 

  977.             break;
    978. 

  978.         default:
    979. 

  979.             break;
    980. 

  980.     }
    981. 

  981. 

  982.     *pldBm = -1 * (a + b * 2);
    983. 

  983. }
    984. 

  984. 

  985. 

  986. 

  987. void
    988. 

  988. RFbRFTableDownload (
    989. 

  989.       PSDevice pDevice
    990. 

  990.     )
    991. 

  991. {
    992. 

  992. WORD    wLength1 = 0,wLength2 = 0 ,wLength3 = 0;
    993. 

  993. PBYTE   pbyAddr1 = NULL,pbyAddr2 = NULL,pbyAddr3 = NULL;
    994. 

  994. WORD    wLength,wValue;
    995. 

  995. BYTE    abyArray[256];
    996. 

  996. 

  997.     switch ( pDevice->byRFType ) {
    998. 

  998.         case RF_AL2230:
    999. 

  999.         case RF_AL2230S:
    1000. 

  1000.             wLength1 = CB_AL2230_INIT_SEQ * 3;
    1001. 

  1001.             wLength2 = CB_MAX_CHANNEL_24G * 3;
    1002. 

  1002.             wLength3 = CB_MAX_CHANNEL_24G * 3;
    1003. 

  1003.             pbyAddr1 = &(abyAL2230InitTable[0][0]);
    1004. 

  1004.             pbyAddr2 = &(abyAL2230ChannelTable0[0][0]);
    1005. 

  1005.             pbyAddr3 = &(abyAL2230ChannelTable1[0][0]);
    1006. 

  1006.             break;
    1007. 

  1007.         case RF_AIROHA7230:
    1008. 

  1008.             wLength1 = CB_AL7230_INIT_SEQ * 3;
    1009. 

  1009.             wLength2 = CB_MAX_CHANNEL * 3;
    1010. 

  1010.             wLength3 = CB_MAX_CHANNEL * 3;
    1011. 

  1011.             pbyAddr1 = &(abyAL7230InitTable[0][0]);
    1012. 

  1012.             pbyAddr2 = &(abyAL7230ChannelTable0[0][0]);
    1013. 

  1013.             pbyAddr3 = &(abyAL7230ChannelTable1[0][0]);
    1014. 

  1014.             break;
    1015. 

  1015.         case RF_VT3226: //RobertYu:20051111
    1016. 

  1016.             wLength1 = CB_VT3226_INIT_SEQ * 3;
    1017. 

  1017.             wLength2 = CB_MAX_CHANNEL_24G * 3;
    1018. 

  1018.             wLength3 = CB_MAX_CHANNEL_24G * 3;
    1019. 

  1019.             pbyAddr1 = &(abyVT3226_InitTable[0][0]);
    1020. 

  1020.             pbyAddr2 = &(abyVT3226_ChannelTable0[0][0]);
    1021. 

  1021.             pbyAddr3 = &(abyVT3226_ChannelTable1[0][0]);
    1022. 

  1022.             break;
    1023. 

  1023.         case RF_VT3226D0: //RobertYu:20051114
    1024. 

  1024.             wLength1 = CB_VT3226_INIT_SEQ * 3;
    1025. 

  1025.             wLength2 = CB_MAX_CHANNEL_24G * 3;
    1026. 

  1026.             wLength3 = CB_MAX_CHANNEL_24G * 3;
    1027. 

  1027.             pbyAddr1 = &(abyVT3226D0_InitTable[0][0]);
    1028. 

  1028.             pbyAddr2 = &(abyVT3226_ChannelTable0[0][0]);
    1029. 

  1029.             pbyAddr3 = &(abyVT3226_ChannelTable1[0][0]);
    1030. 

  1030.             break;
    1031. 

  1031.         case RF_VT3342A0: //RobertYu:20060609
    1032. 

  1032.             wLength1 = CB_VT3342_INIT_SEQ * 3;
    1033. 

  1033.             wLength2 = CB_MAX_CHANNEL * 3;
    1034. 

  1034.             wLength3 = CB_MAX_CHANNEL * 3;
    1035. 

  1035.             pbyAddr1 = &(abyVT3342A0_InitTable[0][0]);
    1036. 

  1036.             pbyAddr2 = &(abyVT3342_ChannelTable0[0][0]);
    1037. 

  1037.             pbyAddr3 = &(abyVT3342_ChannelTable1[0][0]);
    1038. 

  1038.             break;
    1039. 

  1039. 

  1040.     }
    1041. 

  1041.     //Init Table
    1042. 

  1042. 

  1043.     memcpy(abyArray, pbyAddr1, wLength1);
    1044. 

  1044.     CONTROLnsRequestOut(pDevice,
    1045. 

  1045.                     MESSAGE_TYPE_WRITE,
    1046. 

  1046.                     0,
    1047. 

  1047.                     MESSAGE_REQUEST_RF_INIT,
    1048. 

  1048.                     wLength1,
    1049. 

  1049.                     abyArray
    1050. 

  1050.                     );
    1051. 

  1051.     //Channle Table 0
    1052. 

  1052.     wValue = 0;
    1053. 

  1053.     while ( wLength2 > 0 ) {
    1054. 

  1054. 

  1055.         if ( wLength2 >= 64 ) {
    1056. 

  1056.             wLength = 64;
    1057. 

  1057.         } else {
    1058. 

  1058.             wLength = wLength2;
    1059. 

  1059.         }
    1060. 

  1060.         memcpy(abyArray, pbyAddr2, wLength);
    1061. 

  1061.         CONTROLnsRequestOut(pDevice,
    1062. 

  1062.                         MESSAGE_TYPE_WRITE,
    1063. 

  1063.                         wValue,
    1064. 

  1064.                         MESSAGE_REQUEST_RF_CH0,
    1065. 

  1065.                         wLength,
    1066. 

  1066.                         abyArray);
    1067. 

  1067. 

  1068.         wLength2 -= wLength;
    1069. 

  1069.         wValue += wLength;
    1070. 

  1070.         pbyAddr2 += wLength;
    1071. 

  1071.     }
    1072. 

  1072.     //Channel table 1
    1073. 

  1073.     wValue = 0;
    1074. 

  1074.     while ( wLength3 > 0 ) {
    1075. 

  1075. 

  1076.         if ( wLength3 >= 64 ) {
    1077. 

  1077.             wLength = 64;
    1078. 

  1078.         } else {
    1079. 

  1079.             wLength = wLength3;
    1080. 

  1080.         }
    1081. 

  1081.         memcpy(abyArray, pbyAddr3, wLength);
    1082. 

  1082.         CONTROLnsRequestOut(pDevice,
    1083. 

  1083.                         MESSAGE_TYPE_WRITE,
    1084. 

  1084.                         wValue,
    1085. 

  1085.                         MESSAGE_REQUEST_RF_CH1,
    1086. 

  1086.                         wLength,
    1087. 

  1087.                         abyArray);
    1088. 

  1088. 

  1089.         wLength3 -= wLength;
    1090. 

  1090.         wValue += wLength;
    1091. 

  1091.         pbyAddr3 += wLength;
    1092. 

  1092.     }
    1093. 

  1093. 

  1094.     //7230 needs 2 InitTable and 3 Channel Table
    1095. 

  1095.     if ( pDevice->byRFType == RF_AIROHA7230 ) {
    1096. 

  1096.         wLength1 = CB_AL7230_INIT_SEQ * 3;
    1097. 

  1097.         wLength2 = CB_MAX_CHANNEL * 3;
    1098. 

  1098.         pbyAddr1 = &(abyAL7230InitTableAMode[0][0]);
    1099. 

  1099.         pbyAddr2 = &(abyAL7230ChannelTable2[0][0]);
    1100. 

  1100.         memcpy(abyArray, pbyAddr1, wLength1);
    1101. 

  1101.         //Init Table 2
    1102. 

  1102.         CONTROLnsRequestOut(pDevice,
    1103. 

  1103.                     MESSAGE_TYPE_WRITE,
    1104. 

  1104.                     0,
    1105. 

  1105.                     MESSAGE_REQUEST_RF_INIT2,
    1106. 

  1106.                     wLength1,
    1107. 

  1107.                     abyArray);
    1108. 

  1108. 

  1109.         //Channle Table 0
    1110. 

  1110.         wValue = 0;
    1111. 

  1111.         while ( wLength2 > 0 ) {
    1112. 

  1112. 

  1113.             if ( wLength2 >= 64 ) {
    1114. 

  1114.                 wLength = 64;
    1115. 

  1115.             } else {
    1116. 

  1116.                 wLength = wLength2;
    1117. 

  1117.             }
    1118. 

  1118.             memcpy(abyArray, pbyAddr2, wLength);
    1119. 

  1119.             CONTROLnsRequestOut(pDevice,
    1120. 

  1120.                             MESSAGE_TYPE_WRITE,
    1121. 

  1121.                             wValue,
    1122. 

  1122.                             MESSAGE_REQUEST_RF_CH2,
    1123. 

  1123.                             wLength,
    1124. 

  1124.                             abyArray);
    1125. 

  1125. 

  1126.             wLength2 -= wLength;
    1127. 

  1127.             wValue += wLength;
    1128. 

  1128.             pbyAddr2 += wLength;
    1129. 

  1129.         }
    1130. 

  1130.     }
    1131. 

  1131. 

  1132. }
    1133. 

  1133. 

  1134. // RobertYu:20060412, TWIF1.11 adjust LO Current for 11b mode
    1135. 

  1135. BOOL s_bVT3226D0_11bLoCurrentAdjust(
    1136. 

  1136.       PSDevice    pDevice,
    1137. 

  1137.       BYTE        byChannel,
    1138. 

  1138.       BOOL        b11bMode)
    1139. 

  1139. {
    1140. 

  1140.     BOOL    bResult;
    1141. 

  1141. 

  1142.     bResult = TRUE;
    1143. 

  1143.     if( b11bMode )
    1144. 

  1144.         bResult &= IFRFbWriteEmbeded(pDevice, dwVT3226D0LoCurrentTable[byChannel-1]);
    1145. 

  1145.     else
    1146. 

  1146.         bResult &= IFRFbWriteEmbeded(pDevice, 0x016BC600+(BY_VT3226_REG_LEN<<3)+IFREGCTL_REGW); //RobertYu:20060412
    1147. 

  1147. 

  1148.     return bResult;
    1149. 

  1149. }
    1150.