/drivers/staging/tidspbridge/include/dspbridge/chnlpriv.h

 1/*
 2 * chnlpriv.h
 3 *
 4 * DSP-BIOS Bridge driver support functions for TI OMAP processors.
 5 *
 6 * Private channel header shared between DSPSYS, DSPAPI and
 7 * Bridge driver modules.
 8 *
 9 * Copyright (C) 2005-2006 Texas Instruments, Inc.
10 *
11 * This package is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
17 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
18 */
19
20#ifndef CHNLPRIV_
21#define CHNLPRIV_
22
23#include <dspbridge/chnldefs.h>
24#include <dspbridge/devdefs.h>
25#include <dspbridge/sync.h>
26
27/* Channel manager limits: */
28#define CHNL_MAXCHANNELS    32	/* Max channels available per transport */
29
30/*
31 *  Trans port channel Id definitions:(must match dsp-side).
32 *
33 *  For CHNL_MAXCHANNELS = 16:
34 *
35 *  ChnlIds:
36 *      0-15  (PCPY) - transport 0)
37 *      16-31 (DDMA) - transport 1)
38 *      32-47 (ZCPY) - transport 2)
39 */
40#define CHNL_PCPY       0	/* Proc-copy transport 0 */
41
42/* Higher level channel states: */
43#define CHNL_STATEREADY		0	/* Channel ready for I/O. */
44#define CHNL_STATECANCEL	1	/* I/O was cancelled. */
45#define CHNL_STATEEOS		2	/* End Of Stream reached. */
46
47/* Macros for checking mode: */
48#define CHNL_IS_INPUT(mode)      (mode & CHNL_MODEFROMDSP)
49#define CHNL_IS_OUTPUT(mode)     (!CHNL_IS_INPUT(mode))
50
51/* Types of channel class libraries: */
52#define CHNL_TYPESM         1	/* Shared memory driver. */
53
54/* Channel info. */
55struct chnl_info {
56	struct chnl_mgr *chnl_mgr;	/* Owning channel manager. */
57	u32 cnhl_id;		/* Channel ID. */
58	void *event_obj;	/* Channel I/O completion event. */
59	/*Abstraction of I/O completion event. */
60	struct sync_object *sync_event;
61	s8 mode;		/* Channel mode. */
62	u8 state;		/* Current channel state. */
63	u32 bytes_tx;		/* Total bytes transferred. */
64	u32 cio_cs;		/* Number of IOCs in queue. */
65	u32 cio_reqs;		/* Number of IO Requests in queue. */
66	u32 process;		/* Process owning this channel. */
67};
68
69/* Channel manager info: */
70struct chnl_mgrinfo {
71	u8 type;		/* Type of channel class library. */
72	/* Channel handle, given the channel id. */
73	struct chnl_object *chnl_obj;
74	u8 open_channels;	/* Number of open channels. */
75	u8 max_channels;	/* total # of chnls supported */
76};
77
78/* Channel Manager Attrs: */
79struct chnl_mgrattrs {
80	/* Max number of channels this manager can use. */
81	u8 max_channels;
82	u32 word_size;		/* DSP Word size. */
83};
84
85#endif /* CHNLPRIV_ */