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/drivers/staging/spectra/lld_nand.h

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t
C Header | 131 lines | 99 code | 14 blank | 18 comment | 0 complexity | 69aa22bde997fe3dac92cd1f0b3df360 MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
  1/*
  2 * NAND Flash Controller Device Driver
  3 * Copyright (c) 2009, Intel Corporation and its suppliers.
  4 *
  5 * This program is free software; you can redistribute it and/or modify it
  6 * under the terms and conditions of the GNU General Public License,
  7 * version 2, as published by the Free Software Foundation.
  8 *
  9 * This program is distributed in the hope it will be useful, but WITHOUT
 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 12 * more details.
 13 *
 14 * You should have received a copy of the GNU General Public License along with
 15 * this program; if not, write to the Free Software Foundation, Inc.,
 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 17 *
 18 */
 19
 20#ifndef _LLD_NAND_
 21#define _LLD_NAND_
 22
 23#ifdef ELDORA
 24#include "defs.h"
 25#else
 26#include "flash.h"
 27#include "ffsport.h"
 28#endif
 29
 30#define MODE_00    0x00000000
 31#define MODE_01    0x04000000
 32#define MODE_10    0x08000000
 33#define MODE_11    0x0C000000
 34
 35
 36#define DATA_TRANSFER_MODE              0
 37#define PROTECTION_PER_BLOCK            1
 38#define LOAD_WAIT_COUNT                 2
 39#define PROGRAM_WAIT_COUNT              3
 40#define ERASE_WAIT_COUNT                4
 41#define INT_MONITOR_CYCLE_COUNT         5
 42#define READ_BUSY_PIN_ENABLED           6
 43#define MULTIPLANE_OPERATION_SUPPORT    7
 44#define PRE_FETCH_MODE                  8
 45#define CE_DONT_CARE_SUPPORT            9
 46#define COPYBACK_SUPPORT                10
 47#define CACHE_WRITE_SUPPORT             11
 48#define CACHE_READ_SUPPORT              12
 49#define NUM_PAGES_IN_BLOCK              13
 50#define ECC_ENABLE_SELECT               14
 51#define WRITE_ENABLE_2_READ_ENABLE      15
 52#define ADDRESS_2_DATA                  16
 53#define READ_ENABLE_2_WRITE_ENABLE      17
 54#define TWO_ROW_ADDRESS_CYCLES          18
 55#define MULTIPLANE_ADDRESS_RESTRICT     19
 56#define ACC_CLOCKS                      20
 57#define READ_WRITE_ENABLE_LOW_COUNT     21
 58#define READ_WRITE_ENABLE_HIGH_COUNT    22
 59
 60#define ECC_SECTOR_SIZE     512
 61#define LLD_MAX_FLASH_BANKS     4
 62
 63struct mrst_nand_info {
 64	struct pci_dev *dev;
 65	u32 state;
 66	u32 flash_bank;
 67	u8 *read_data;
 68	u8 *write_data;
 69	u32 block;
 70	u16 page;
 71	u32 use_dma;
 72	void __iomem *ioaddr;  /* Mapped io reg base address */
 73	int ret;
 74	u32 pcmds_num;
 75	struct pending_cmd *pcmds;
 76	int cdma_num;           /* CDMA descriptor number in this chan */
 77	u8 *cdma_desc_buf;	/* CDMA descriptor table */
 78	u8 *memcp_desc_buf;	/* Memory copy descriptor table */
 79	dma_addr_t cdma_desc;	/* Mapped CDMA descriptor table */
 80	dma_addr_t memcp_desc;	/* Mapped memory copy descriptor table */
 81	struct completion complete;
 82};
 83
 84int NAND_Flash_Init(void);
 85int nand_release_spectra(void);
 86u16  NAND_Flash_Reset(void);
 87u16  NAND_Read_Device_ID(void);
 88u16  NAND_Erase_Block(u32 flash_add);
 89u16  NAND_Write_Page_Main(u8 *write_data, u32 block, u16 page,
 90				u16 page_count);
 91u16  NAND_Read_Page_Main(u8 *read_data, u32 block, u16 page,
 92				u16 page_count);
 93u16  NAND_UnlockArrayAll(void);
 94u16  NAND_Write_Page_Main_Spare(u8 *write_data, u32 block,
 95				u16 page, u16 page_count);
 96u16  NAND_Write_Page_Spare(u8 *read_data, u32 block, u16 page,
 97				u16 page_count);
 98u16  NAND_Read_Page_Main_Spare(u8 *read_data, u32 block, u16 page,
 99				u16 page_count);
100u16  NAND_Read_Page_Spare(u8 *read_data, u32 block, u16 page,
101				u16 page_count);
102void NAND_LLD_Enable_Disable_Interrupts(u16 INT_ENABLE);
103u16  NAND_Get_Bad_Block(u32 block);
104u16  NAND_Pipeline_Read_Ahead(u8 *read_data, u32 block, u16 page,
105				u16 page_count);
106u16  NAND_Pipeline_Write_Ahead(u8 *write_data, u32 block,
107				u16 page, u16 page_count);
108u16  NAND_Multiplane_Read(u8 *read_data, u32 block, u16 page,
109				u16 page_count);
110u16  NAND_Multiplane_Write(u8 *write_data, u32 block, u16 page,
111				u16 page_count);
112void NAND_ECC_Ctrl(int enable);
113u16 NAND_Read_Page_Main_Polling(u8 *read_data,
114		u32 block, u16 page, u16 page_count);
115u16 NAND_Pipeline_Read_Ahead_Polling(u8 *read_data,
116			u32 block, u16 page, u16 page_count);
117void Conv_Spare_Data_Log2Phy_Format(u8 *data);
118void Conv_Spare_Data_Phy2Log_Format(u8 *data);
119void Conv_Main_Spare_Data_Log2Phy_Format(u8 *data, u16 page_count);
120void Conv_Main_Spare_Data_Phy2Log_Format(u8 *data, u16 page_count);
121
122extern void __iomem *FlashReg;
123extern void __iomem *FlashMem;
124
125extern int totalUsedBanks;
126extern u32 GLOB_valid_banks[LLD_MAX_FLASH_BANKS];
127
128#endif /*_LLD_NAND_*/
129
130
131