/drivers/staging/spectra/lld_nand.h

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t · C Header · 131 lines · 99 code · 14 blank · 18 comment · 0 complexity · 69aa22bde997fe3dac92cd1f0b3df360 MD5 · raw file

  1. /*
  2. * NAND Flash Controller Device Driver
  3. * Copyright (c) 2009, Intel Corporation and its suppliers.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17. *
  18. */
  19. #ifndef _LLD_NAND_
  20. #define _LLD_NAND_
  21. #ifdef ELDORA
  22. #include "defs.h"
  23. #else
  24. #include "flash.h"
  25. #include "ffsport.h"
  26. #endif
  27. #define MODE_00 0x00000000
  28. #define MODE_01 0x04000000
  29. #define MODE_10 0x08000000
  30. #define MODE_11 0x0C000000
  31. #define DATA_TRANSFER_MODE 0
  32. #define PROTECTION_PER_BLOCK 1
  33. #define LOAD_WAIT_COUNT 2
  34. #define PROGRAM_WAIT_COUNT 3
  35. #define ERASE_WAIT_COUNT 4
  36. #define INT_MONITOR_CYCLE_COUNT 5
  37. #define READ_BUSY_PIN_ENABLED 6
  38. #define MULTIPLANE_OPERATION_SUPPORT 7
  39. #define PRE_FETCH_MODE 8
  40. #define CE_DONT_CARE_SUPPORT 9
  41. #define COPYBACK_SUPPORT 10
  42. #define CACHE_WRITE_SUPPORT 11
  43. #define CACHE_READ_SUPPORT 12
  44. #define NUM_PAGES_IN_BLOCK 13
  45. #define ECC_ENABLE_SELECT 14
  46. #define WRITE_ENABLE_2_READ_ENABLE 15
  47. #define ADDRESS_2_DATA 16
  48. #define READ_ENABLE_2_WRITE_ENABLE 17
  49. #define TWO_ROW_ADDRESS_CYCLES 18
  50. #define MULTIPLANE_ADDRESS_RESTRICT 19
  51. #define ACC_CLOCKS 20
  52. #define READ_WRITE_ENABLE_LOW_COUNT 21
  53. #define READ_WRITE_ENABLE_HIGH_COUNT 22
  54. #define ECC_SECTOR_SIZE 512
  55. #define LLD_MAX_FLASH_BANKS 4
  56. struct mrst_nand_info {
  57. struct pci_dev *dev;
  58. u32 state;
  59. u32 flash_bank;
  60. u8 *read_data;
  61. u8 *write_data;
  62. u32 block;
  63. u16 page;
  64. u32 use_dma;
  65. void __iomem *ioaddr; /* Mapped io reg base address */
  66. int ret;
  67. u32 pcmds_num;
  68. struct pending_cmd *pcmds;
  69. int cdma_num; /* CDMA descriptor number in this chan */
  70. u8 *cdma_desc_buf; /* CDMA descriptor table */
  71. u8 *memcp_desc_buf; /* Memory copy descriptor table */
  72. dma_addr_t cdma_desc; /* Mapped CDMA descriptor table */
  73. dma_addr_t memcp_desc; /* Mapped memory copy descriptor table */
  74. struct completion complete;
  75. };
  76. int NAND_Flash_Init(void);
  77. int nand_release_spectra(void);
  78. u16 NAND_Flash_Reset(void);
  79. u16 NAND_Read_Device_ID(void);
  80. u16 NAND_Erase_Block(u32 flash_add);
  81. u16 NAND_Write_Page_Main(u8 *write_data, u32 block, u16 page,
  82. u16 page_count);
  83. u16 NAND_Read_Page_Main(u8 *read_data, u32 block, u16 page,
  84. u16 page_count);
  85. u16 NAND_UnlockArrayAll(void);
  86. u16 NAND_Write_Page_Main_Spare(u8 *write_data, u32 block,
  87. u16 page, u16 page_count);
  88. u16 NAND_Write_Page_Spare(u8 *read_data, u32 block, u16 page,
  89. u16 page_count);
  90. u16 NAND_Read_Page_Main_Spare(u8 *read_data, u32 block, u16 page,
  91. u16 page_count);
  92. u16 NAND_Read_Page_Spare(u8 *read_data, u32 block, u16 page,
  93. u16 page_count);
  94. void NAND_LLD_Enable_Disable_Interrupts(u16 INT_ENABLE);
  95. u16 NAND_Get_Bad_Block(u32 block);
  96. u16 NAND_Pipeline_Read_Ahead(u8 *read_data, u32 block, u16 page,
  97. u16 page_count);
  98. u16 NAND_Pipeline_Write_Ahead(u8 *write_data, u32 block,
  99. u16 page, u16 page_count);
  100. u16 NAND_Multiplane_Read(u8 *read_data, u32 block, u16 page,
  101. u16 page_count);
  102. u16 NAND_Multiplane_Write(u8 *write_data, u32 block, u16 page,
  103. u16 page_count);
  104. void NAND_ECC_Ctrl(int enable);
  105. u16 NAND_Read_Page_Main_Polling(u8 *read_data,
  106. u32 block, u16 page, u16 page_count);
  107. u16 NAND_Pipeline_Read_Ahead_Polling(u8 *read_data,
  108. u32 block, u16 page, u16 page_count);
  109. void Conv_Spare_Data_Log2Phy_Format(u8 *data);
  110. void Conv_Spare_Data_Phy2Log_Format(u8 *data);
  111. void Conv_Main_Spare_Data_Log2Phy_Format(u8 *data, u16 page_count);
  112. void Conv_Main_Spare_Data_Phy2Log_Format(u8 *data, u16 page_count);
  113. extern void __iomem *FlashReg;
  114. extern void __iomem *FlashMem;
  115. extern int totalUsedBanks;
  116. extern u32 GLOB_valid_banks[LLD_MAX_FLASH_BANKS];
  117. #endif /*_LLD_NAND_*/