/drivers/staging/rtl8192u/r8192U_dm.h

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t · C Header · 254 lines · 169 code · 48 blank · 37 comment · 0 complexity · b5cb8b3c8d590926a585d81d8a60bf69 MD5 · raw file

  1. /*****************************************************************************
  2. * Copyright(c) 2007, RealTEK Technology Inc. All Right Reserved.
  3. *
  4. * Module: Hal819xUsbDM.h (RTL8192 Header H File)
  5. *
  6. *
  7. * Note: For dynamic control definition constant structure.
  8. *
  9. *
  10. * Export:
  11. *
  12. * Abbrev:
  13. *
  14. * History:
  15. * Data Who Remark
  16. * 10/04/2007 MHC Create initial version.
  17. *
  18. *****************************************************************************/
  19. /* Check to see if the file has been included already. */
  20. #ifndef __R8192UDM_H__
  21. #define __R8192UDM_H__
  22. /*--------------------------Define Parameters-------------------------------*/
  23. #define DM_DIG_THRESH_HIGH 40
  24. #define DM_DIG_THRESH_LOW 35
  25. #define DM_DIG_HIGH_PWR_THRESH_HIGH 75
  26. #define DM_DIG_HIGH_PWR_THRESH_LOW 70
  27. #define BW_AUTO_SWITCH_HIGH_LOW 25
  28. #define BW_AUTO_SWITCH_LOW_HIGH 30
  29. #define DM_check_fsync_time_interval 500
  30. #define DM_DIG_BACKOFF 12
  31. #define DM_DIG_MAX 0x36
  32. #define DM_DIG_MIN 0x1c
  33. #define DM_DIG_MIN_Netcore 0x12
  34. #define RxPathSelection_SS_TH_low 30
  35. #define RxPathSelection_diff_TH 18
  36. #define RateAdaptiveTH_High 50
  37. #define RateAdaptiveTH_Low_20M 30
  38. #define RateAdaptiveTH_Low_40M 10
  39. #define VeryLowRSSI 15
  40. #define CTSToSelfTHVal 30
  41. //defined by vivi, for tx power track
  42. #define E_FOR_TX_POWER_TRACK 300
  43. //Dynamic Tx Power Control Threshold
  44. #define TX_POWER_NEAR_FIELD_THRESH_HIGH 68
  45. #define TX_POWER_NEAR_FIELD_THRESH_LOW 62
  46. //added by amy for atheros AP
  47. #define TX_POWER_ATHEROAP_THRESH_HIGH 78
  48. #define TX_POWER_ATHEROAP_THRESH_LOW 72
  49. //defined by vivi, for showing on UI
  50. #define Current_Tx_Rate_Reg 0x1b8
  51. #define Initial_Tx_Rate_Reg 0x1b9
  52. #define Tx_Retry_Count_Reg 0x1ac
  53. #define RegC38_TH 20
  54. /*--------------------------Define Parameters-------------------------------*/
  55. /*------------------------------Define structure----------------------------*/
  56. /* 2007/10/04 MH Define upper and lower threshold of DIG enable or disable. */
  57. typedef struct _dynamic_initial_gain_threshold_
  58. {
  59. u8 dig_enable_flag;
  60. u8 dig_algorithm;
  61. u8 dbg_mode;
  62. u8 dig_algorithm_switch;
  63. long rssi_low_thresh;
  64. long rssi_high_thresh;
  65. long rssi_high_power_lowthresh;
  66. long rssi_high_power_highthresh;
  67. u8 dig_state;
  68. u8 dig_highpwr_state;
  69. u8 cur_connect_state;
  70. u8 pre_connect_state;
  71. u8 curpd_thstate;
  72. u8 prepd_thstate;
  73. u8 curcs_ratio_state;
  74. u8 precs_ratio_state;
  75. u32 pre_ig_value;
  76. u32 cur_ig_value;
  77. u8 backoff_val;
  78. u8 rx_gain_range_max;
  79. u8 rx_gain_range_min;
  80. bool initialgain_lowerbound_state;
  81. long rssi_val;
  82. }dig_t;
  83. typedef enum tag_dynamic_init_gain_state_definition
  84. {
  85. DM_STA_DIG_OFF = 0,
  86. DM_STA_DIG_ON,
  87. DM_STA_DIG_MAX
  88. }dm_dig_sta_e;
  89. /* 2007/10/08 MH Define RATR state. */
  90. typedef enum tag_dynamic_ratr_state_definition
  91. {
  92. DM_RATR_STA_HIGH = 0,
  93. DM_RATR_STA_MIDDLE = 1,
  94. DM_RATR_STA_LOW = 2,
  95. DM_RATR_STA_MAX
  96. }dm_ratr_sta_e;
  97. /* 2007/10/11 MH Define DIG operation type. */
  98. typedef enum tag_dynamic_init_gain_operation_type_definition
  99. {
  100. DIG_TYPE_THRESH_HIGH = 0,
  101. DIG_TYPE_THRESH_LOW = 1,
  102. DIG_TYPE_THRESH_HIGHPWR_HIGH = 2,
  103. DIG_TYPE_THRESH_HIGHPWR_LOW = 3,
  104. DIG_TYPE_DBG_MODE = 4,
  105. DIG_TYPE_RSSI = 5,
  106. DIG_TYPE_ALGORITHM = 6,
  107. DIG_TYPE_BACKOFF = 7,
  108. DIG_TYPE_PWDB_FACTOR = 8,
  109. DIG_TYPE_RX_GAIN_MIN = 9,
  110. DIG_TYPE_RX_GAIN_MAX = 10,
  111. DIG_TYPE_ENABLE = 20,
  112. DIG_TYPE_DISABLE = 30,
  113. DIG_OP_TYPE_MAX
  114. }dm_dig_op_e;
  115. typedef enum tag_dig_algorithm_definition
  116. {
  117. DIG_ALGO_BY_FALSE_ALARM = 0,
  118. DIG_ALGO_BY_RSSI = 1,
  119. DIG_ALGO_MAX
  120. }dm_dig_alg_e;
  121. typedef enum tag_dig_dbgmode_definition
  122. {
  123. DIG_DBG_OFF = 0,
  124. DIG_DBG_ON = 1,
  125. DIG_DBG_MAX
  126. }dm_dig_dbg_e;
  127. typedef enum tag_dig_connect_definition
  128. {
  129. DIG_DISCONNECT = 0,
  130. DIG_CONNECT = 1,
  131. DIG_CONNECT_MAX
  132. }dm_dig_connect_e;
  133. typedef enum tag_dig_packetdetection_threshold_definition
  134. {
  135. DIG_PD_AT_LOW_POWER = 0,
  136. DIG_PD_AT_NORMAL_POWER = 1,
  137. DIG_PD_AT_HIGH_POWER = 2,
  138. DIG_PD_MAX
  139. }dm_dig_pd_th_e;
  140. typedef enum tag_dig_cck_cs_ratio_state_definition
  141. {
  142. DIG_CS_RATIO_LOWER = 0,
  143. DIG_CS_RATIO_HIGHER = 1,
  144. DIG_CS_MAX
  145. }dm_dig_cs_ratio_e;
  146. typedef struct _Dynamic_Rx_Path_Selection_
  147. {
  148. u8 Enable;
  149. u8 DbgMode;
  150. u8 cck_method;
  151. u8 cck_Rx_path;
  152. u8 SS_TH_low;
  153. u8 diff_TH;
  154. u8 disabledRF;
  155. u8 reserved;
  156. u8 rf_rssi[4];
  157. u8 rf_enable_rssi_th[4];
  158. long cck_pwdb_sta[4];
  159. }DRxPathSel;
  160. typedef enum tag_CCK_Rx_Path_Method_Definition
  161. {
  162. CCK_Rx_Version_1 = 0,
  163. CCK_Rx_Version_2= 1,
  164. CCK_Rx_Version_MAX
  165. }DM_CCK_Rx_Path_Method;
  166. typedef enum tag_DM_DbgMode_Definition
  167. {
  168. DM_DBG_OFF = 0,
  169. DM_DBG_ON = 1,
  170. DM_DBG_MAX
  171. }DM_DBG_E;
  172. typedef struct tag_Tx_Config_Cmd_Format
  173. {
  174. u32 Op; /* Command packet type. */
  175. u32 Length; /* Command packet length. */
  176. u32 Value;
  177. }DCMD_TXCMD_T, *PDCMD_TXCMD_T;
  178. /*------------------------------Define structure----------------------------*/
  179. /*------------------------Export global variable----------------------------*/
  180. extern dig_t dm_digtable;
  181. extern u8 dm_shadow[16][256];
  182. extern DRxPathSel DM_RxPathSelTable;
  183. /*------------------------Export global variable----------------------------*/
  184. /*------------------------Export Marco Definition---------------------------*/
  185. /*------------------------Export Marco Definition---------------------------*/
  186. /*--------------------------Exported Function prototype---------------------*/
  187. extern void init_hal_dm(struct net_device *dev);
  188. extern void deinit_hal_dm(struct net_device *dev);
  189. extern void hal_dm_watchdog(struct net_device *dev);
  190. extern void init_rate_adaptive(struct net_device *dev);
  191. extern void dm_txpower_trackingcallback(struct work_struct *work);
  192. extern void dm_restore_dynamic_mechanism_state(struct net_device *dev);
  193. extern void dm_backup_dynamic_mechanism_state(struct net_device *dev);
  194. extern void dm_change_dynamic_initgain_thresh(struct net_device *dev,
  195. u32 dm_type, u32 dm_value);
  196. extern void dm_force_tx_fw_info(struct net_device *dev,u32 force_type, u32 force_value);
  197. extern void dm_init_edca_turbo(struct net_device *dev);
  198. extern void dm_rf_operation_test_callback(unsigned long data);
  199. extern void dm_rf_pathcheck_workitemcallback(struct work_struct *work);
  200. extern void dm_fsync_timer_callback(unsigned long data);
  201. extern void dm_cck_txpower_adjust(struct net_device *dev,bool binch14);
  202. extern void dm_shadow_init(struct net_device *dev);
  203. extern void dm_initialize_txpower_tracking(struct net_device *dev);
  204. /*--------------------------Exported Function prototype---------------------*/
  205. #endif /*__R8192UDM_H__ */
  206. /* End of r8192U_dm.h */