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/drivers/staging/octeon/cvmx-helper-sgmii.c

https://bitbucket.org/cyanogenmod/android_kernel_asus_tf300t
C | 550 lines | 299 code | 50 blank | 201 comment | 31 complexity | 4ff5a0bb3aab9a092ec68cf06e4bbb0c MD5 | raw file
Possible License(s): LGPL-2.0, AGPL-1.0, GPL-2.0
  1/***********************license start***************
  2 * Author: Cavium Networks
  3 *
  4 * Contact: support@caviumnetworks.com
  5 * This file is part of the OCTEON SDK
  6 *
  7 * Copyright (c) 2003-2008 Cavium Networks
  8 *
  9 * This file is free software; you can redistribute it and/or modify
 10 * it under the terms of the GNU General Public License, Version 2, as
 11 * published by the Free Software Foundation.
 12 *
 13 * This file is distributed in the hope that it will be useful, but
 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
 16 * NONINFRINGEMENT.  See the GNU General Public License for more
 17 * details.
 18 *
 19 * You should have received a copy of the GNU General Public License
 20 * along with this file; if not, write to the Free Software
 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 22 * or visit http://www.gnu.org/licenses/.
 23 *
 24 * This file may also be available under a different license from Cavium.
 25 * Contact Cavium Networks for more information
 26 ***********************license end**************************************/
 27
 28/*
 29 * Functions for SGMII initialization, configuration,
 30 * and monitoring.
 31 */
 32
 33#include <asm/octeon/octeon.h>
 34
 35#include "cvmx-config.h"
 36
 37#include "cvmx-mdio.h"
 38#include "cvmx-helper.h"
 39#include "cvmx-helper-board.h"
 40
 41#include "cvmx-gmxx-defs.h"
 42#include "cvmx-pcsx-defs.h"
 43
 44void __cvmx_interrupt_gmxx_enable(int interface);
 45void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
 46void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
 47
 48/**
 49 * Perform initialization required only once for an SGMII port.
 50 *
 51 * @interface: Interface to init
 52 * @index:     Index of prot on the interface
 53 *
 54 * Returns Zero on success, negative on failure
 55 */
 56static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index)
 57{
 58	const uint64_t clock_mhz = cvmx_sysinfo_get()->cpu_clock_hz / 1000000;
 59	union cvmx_pcsx_miscx_ctl_reg pcs_misc_ctl_reg;
 60	union cvmx_pcsx_linkx_timer_count_reg pcsx_linkx_timer_count_reg;
 61	union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg;
 62
 63	/* Disable GMX */
 64	gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
 65	gmxx_prtx_cfg.s.en = 0;
 66	cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
 67
 68	/*
 69	 * Write PCS*_LINK*_TIMER_COUNT_REG[COUNT] with the
 70	 * appropriate value. 1000BASE-X specifies a 10ms
 71	 * interval. SGMII specifies a 1.6ms interval.
 72	 */
 73	pcs_misc_ctl_reg.u64 =
 74	    cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
 75	pcsx_linkx_timer_count_reg.u64 =
 76	    cvmx_read_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface));
 77	if (pcs_misc_ctl_reg.s.mode) {
 78		/* 1000BASE-X */
 79		pcsx_linkx_timer_count_reg.s.count =
 80		    (10000ull * clock_mhz) >> 10;
 81	} else {
 82		/* SGMII */
 83		pcsx_linkx_timer_count_reg.s.count =
 84		    (1600ull * clock_mhz) >> 10;
 85	}
 86	cvmx_write_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface),
 87		       pcsx_linkx_timer_count_reg.u64);
 88
 89	/*
 90	 * Write the advertisement register to be used as the
 91	 * tx_Config_Reg<D15:D0> of the autonegotiation.  In
 92	 * 1000BASE-X mode, tx_Config_Reg<D15:D0> is PCS*_AN*_ADV_REG.
 93	 * In SGMII PHY mode, tx_Config_Reg<D15:D0> is
 94	 * PCS*_SGM*_AN_ADV_REG.  In SGMII MAC mode,
 95	 * tx_Config_Reg<D15:D0> is the fixed value 0x4001, so this
 96	 * step can be skipped.
 97	 */
 98	if (pcs_misc_ctl_reg.s.mode) {
 99		/* 1000BASE-X */
100		union cvmx_pcsx_anx_adv_reg pcsx_anx_adv_reg;
101		pcsx_anx_adv_reg.u64 =
102		    cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface));
103		pcsx_anx_adv_reg.s.rem_flt = 0;
104		pcsx_anx_adv_reg.s.pause = 3;
105		pcsx_anx_adv_reg.s.hfd = 1;
106		pcsx_anx_adv_reg.s.fd = 1;
107		cvmx_write_csr(CVMX_PCSX_ANX_ADV_REG(index, interface),
108			       pcsx_anx_adv_reg.u64);
109	} else {
110		union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg;
111		pcsx_miscx_ctl_reg.u64 =
112		    cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
113		if (pcsx_miscx_ctl_reg.s.mac_phy) {
114			/* PHY Mode */
115			union cvmx_pcsx_sgmx_an_adv_reg pcsx_sgmx_an_adv_reg;
116			pcsx_sgmx_an_adv_reg.u64 =
117			    cvmx_read_csr(CVMX_PCSX_SGMX_AN_ADV_REG
118					  (index, interface));
119			pcsx_sgmx_an_adv_reg.s.link = 1;
120			pcsx_sgmx_an_adv_reg.s.dup = 1;
121			pcsx_sgmx_an_adv_reg.s.speed = 2;
122			cvmx_write_csr(CVMX_PCSX_SGMX_AN_ADV_REG
123				       (index, interface),
124				       pcsx_sgmx_an_adv_reg.u64);
125		} else {
126			/* MAC Mode - Nothing to do */
127		}
128	}
129	return 0;
130}
131
132/**
133 * Initialize the SERTES link for the first time or after a loss
134 * of link.
135 *
136 * @interface: Interface to init
137 * @index:     Index of prot on the interface
138 *
139 * Returns Zero on success, negative on failure
140 */
141static int __cvmx_helper_sgmii_hardware_init_link(int interface, int index)
142{
143	union cvmx_pcsx_mrx_control_reg control_reg;
144
145	/*
146	 * Take PCS through a reset sequence.
147	 * PCS*_MR*_CONTROL_REG[PWR_DN] should be cleared to zero.
148	 * Write PCS*_MR*_CONTROL_REG[RESET]=1 (while not changing the
149	 * value of the other PCS*_MR*_CONTROL_REG bits).  Read
150	 * PCS*_MR*_CONTROL_REG[RESET] until it changes value to
151	 * zero.
152	 */
153	control_reg.u64 =
154	    cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
155	if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) {
156		control_reg.s.reset = 1;
157		cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
158			       control_reg.u64);
159		if (CVMX_WAIT_FOR_FIELD64
160		    (CVMX_PCSX_MRX_CONTROL_REG(index, interface),
161		     union cvmx_pcsx_mrx_control_reg, reset, ==, 0, 10000)) {
162			cvmx_dprintf("SGMII%d: Timeout waiting for port %d "
163				     "to finish reset\n",
164			     interface, index);
165			return -1;
166		}
167	}
168
169	/*
170	 * Write PCS*_MR*_CONTROL_REG[RST_AN]=1 to ensure a fresh
171	 * sgmii negotiation starts.
172	 */
173	control_reg.s.rst_an = 1;
174	control_reg.s.an_en = 1;
175	control_reg.s.pwr_dn = 0;
176	cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
177		       control_reg.u64);
178
179	/*
180	 * Wait for PCS*_MR*_STATUS_REG[AN_CPT] to be set, indicating
181	 * that sgmii autonegotiation is complete. In MAC mode this
182	 * isn't an ethernet link, but a link between Octeon and the
183	 * PHY.
184	 */
185	if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) &&
186	    CVMX_WAIT_FOR_FIELD64(CVMX_PCSX_MRX_STATUS_REG(index, interface),
187				  union cvmx_pcsx_mrx_status_reg, an_cpt, ==, 1,
188				  10000)) {
189		/* cvmx_dprintf("SGMII%d: Port %d link timeout\n", interface, index); */
190		return -1;
191	}
192	return 0;
193}
194
195/**
196 * Configure an SGMII link to the specified speed after the SERTES
197 * link is up.
198 *
199 * @interface: Interface to init
200 * @index:     Index of prot on the interface
201 * @link_info: Link state to configure
202 *
203 * Returns Zero on success, negative on failure
204 */
205static int __cvmx_helper_sgmii_hardware_init_link_speed(int interface,
206							int index,
207							cvmx_helper_link_info_t
208							link_info)
209{
210	int is_enabled;
211	union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg;
212	union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg;
213
214	/* Disable GMX before we make any changes. Remember the enable state */
215	gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
216	is_enabled = gmxx_prtx_cfg.s.en;
217	gmxx_prtx_cfg.s.en = 0;
218	cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
219
220	/* Wait for GMX to be idle */
221	if (CVMX_WAIT_FOR_FIELD64
222	    (CVMX_GMXX_PRTX_CFG(index, interface), union cvmx_gmxx_prtx_cfg,
223	     rx_idle, ==, 1, 10000)
224	    || CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface),
225				     union cvmx_gmxx_prtx_cfg, tx_idle, ==, 1,
226				     10000)) {
227		cvmx_dprintf
228		    ("SGMII%d: Timeout waiting for port %d to be idle\n",
229		     interface, index);
230		return -1;
231	}
232
233	/* Read GMX CFG again to make sure the disable completed */
234	gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
235
236	/*
237	 * Get the misc control for PCS. We will need to set the
238	 * duplication amount.
239	 */
240	pcsx_miscx_ctl_reg.u64 =
241	    cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
242
243	/*
244	 * Use GMXENO to force the link down if the status we get says
245	 * it should be down.
246	 */
247	pcsx_miscx_ctl_reg.s.gmxeno = !link_info.s.link_up;
248
249	/* Only change the duplex setting if the link is up */
250	if (link_info.s.link_up)
251		gmxx_prtx_cfg.s.duplex = link_info.s.full_duplex;
252
253	/* Do speed based setting for GMX */
254	switch (link_info.s.speed) {
255	case 10:
256		gmxx_prtx_cfg.s.speed = 0;
257		gmxx_prtx_cfg.s.speed_msb = 1;
258		gmxx_prtx_cfg.s.slottime = 0;
259		/* Setting from GMX-603 */
260		pcsx_miscx_ctl_reg.s.samp_pt = 25;
261		cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64);
262		cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
263		break;
264	case 100:
265		gmxx_prtx_cfg.s.speed = 0;
266		gmxx_prtx_cfg.s.speed_msb = 0;
267		gmxx_prtx_cfg.s.slottime = 0;
268		pcsx_miscx_ctl_reg.s.samp_pt = 0x5;
269		cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64);
270		cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
271		break;
272	case 1000:
273		gmxx_prtx_cfg.s.speed = 1;
274		gmxx_prtx_cfg.s.speed_msb = 0;
275		gmxx_prtx_cfg.s.slottime = 1;
276		pcsx_miscx_ctl_reg.s.samp_pt = 1;
277		cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 512);
278		cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 8192);
279		break;
280	default:
281		break;
282	}
283
284	/* Write the new misc control for PCS */
285	cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface),
286		       pcsx_miscx_ctl_reg.u64);
287
288	/* Write the new GMX settings with the port still disabled */
289	cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
290
291	/* Read GMX CFG again to make sure the config completed */
292	gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
293
294	/* Restore the enabled / disabled state */
295	gmxx_prtx_cfg.s.en = is_enabled;
296	cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
297
298	return 0;
299}
300
301/**
302 * Bring up the SGMII interface to be ready for packet I/O but
303 * leave I/O disabled using the GMX override. This function
304 * follows the bringup documented in 10.6.3 of the manual.
305 *
306 * @interface: Interface to bringup
307 * @num_ports: Number of ports on the interface
308 *
309 * Returns Zero on success, negative on failure
310 */
311static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports)
312{
313	int index;
314
315	__cvmx_helper_setup_gmx(interface, num_ports);
316
317	for (index = 0; index < num_ports; index++) {
318		int ipd_port = cvmx_helper_get_ipd_port(interface, index);
319		__cvmx_helper_sgmii_hardware_init_one_time(interface, index);
320		__cvmx_helper_sgmii_link_set(ipd_port,
321					     __cvmx_helper_sgmii_link_get
322					     (ipd_port));
323
324	}
325
326	return 0;
327}
328
329/**
330 * Probe a SGMII interface and determine the number of ports
331 * connected to it. The SGMII interface should still be down after
332 * this call.
333 *
334 * @interface: Interface to probe
335 *
336 * Returns Number of ports on the interface. Zero to disable.
337 */
338int __cvmx_helper_sgmii_probe(int interface)
339{
340	union cvmx_gmxx_inf_mode mode;
341
342	/*
343	 * Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the
344	 * interface needs to be enabled before IPD otherwise per port
345	 * backpressure may not work properly
346	 */
347	mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
348	mode.s.en = 1;
349	cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
350	return 4;
351}
352
353/**
354 * Bringup and enable a SGMII interface. After this call packet
355 * I/O should be fully functional. This is called with IPD
356 * enabled but PKO disabled.
357 *
358 * @interface: Interface to bring up
359 *
360 * Returns Zero on success, negative on failure
361 */
362int __cvmx_helper_sgmii_enable(int interface)
363{
364	int num_ports = cvmx_helper_ports_on_interface(interface);
365	int index;
366
367	__cvmx_helper_sgmii_hardware_init(interface, num_ports);
368
369	for (index = 0; index < num_ports; index++) {
370		union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg;
371		gmxx_prtx_cfg.u64 =
372		    cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
373		gmxx_prtx_cfg.s.en = 1;
374		cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),
375			       gmxx_prtx_cfg.u64);
376		__cvmx_interrupt_pcsx_intx_en_reg_enable(index, interface);
377	}
378	__cvmx_interrupt_pcsxx_int_en_reg_enable(interface);
379	__cvmx_interrupt_gmxx_enable(interface);
380	return 0;
381}
382
383/**
384 * Return the link state of an IPD/PKO port as returned by
385 * auto negotiation. The result of this function may not match
386 * Octeon's link config if auto negotiation has changed since
387 * the last call to cvmx_helper_link_set().
388 *
389 * @ipd_port: IPD/PKO port to query
390 *
391 * Returns Link state
392 */
393cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port)
394{
395	cvmx_helper_link_info_t result;
396	union cvmx_pcsx_miscx_ctl_reg pcs_misc_ctl_reg;
397	int interface = cvmx_helper_get_interface_num(ipd_port);
398	int index = cvmx_helper_get_interface_index_num(ipd_port);
399	union cvmx_pcsx_mrx_control_reg pcsx_mrx_control_reg;
400
401	result.u64 = 0;
402
403	if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) {
404		/* The simulator gives you a simulated 1Gbps full duplex link */
405		result.s.link_up = 1;
406		result.s.full_duplex = 1;
407		result.s.speed = 1000;
408		return result;
409	}
410
411	pcsx_mrx_control_reg.u64 =
412	    cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
413	if (pcsx_mrx_control_reg.s.loopbck1) {
414		/* Force 1Gbps full duplex link for internal loopback */
415		result.s.link_up = 1;
416		result.s.full_duplex = 1;
417		result.s.speed = 1000;
418		return result;
419	}
420
421	pcs_misc_ctl_reg.u64 =
422	    cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
423	if (pcs_misc_ctl_reg.s.mode) {
424		/* 1000BASE-X */
425		/* FIXME */
426	} else {
427		union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg;
428		pcsx_miscx_ctl_reg.u64 =
429		    cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
430		if (pcsx_miscx_ctl_reg.s.mac_phy) {
431			/* PHY Mode */
432			union cvmx_pcsx_mrx_status_reg pcsx_mrx_status_reg;
433			union cvmx_pcsx_anx_results_reg pcsx_anx_results_reg;
434
435			/*
436			 * Don't bother continuing if the SERTES low
437			 * level link is down
438			 */
439			pcsx_mrx_status_reg.u64 =
440			    cvmx_read_csr(CVMX_PCSX_MRX_STATUS_REG
441					  (index, interface));
442			if (pcsx_mrx_status_reg.s.lnk_st == 0) {
443				if (__cvmx_helper_sgmii_hardware_init_link
444				    (interface, index) != 0)
445					return result;
446			}
447
448			/* Read the autoneg results */
449			pcsx_anx_results_reg.u64 =
450			    cvmx_read_csr(CVMX_PCSX_ANX_RESULTS_REG
451					  (index, interface));
452			if (pcsx_anx_results_reg.s.an_cpt) {
453				/*
454				 * Auto negotiation is complete. Set
455				 * status accordingly.
456				 */
457				result.s.full_duplex =
458				    pcsx_anx_results_reg.s.dup;
459				result.s.link_up =
460				    pcsx_anx_results_reg.s.link_ok;
461				switch (pcsx_anx_results_reg.s.spd) {
462				case 0:
463					result.s.speed = 10;
464					break;
465				case 1:
466					result.s.speed = 100;
467					break;
468				case 2:
469					result.s.speed = 1000;
470					break;
471				default:
472					result.s.speed = 0;
473					result.s.link_up = 0;
474					break;
475				}
476			} else {
477				/*
478				 * Auto negotiation isn't
479				 * complete. Return link down.
480				 */
481				result.s.speed = 0;
482				result.s.link_up = 0;
483			}
484		} else {	/* MAC Mode */
485
486			result = __cvmx_helper_board_link_get(ipd_port);
487		}
488	}
489	return result;
490}
491
492/**
493 * Configure an IPD/PKO port for the specified link state. This
494 * function does not influence auto negotiation at the PHY level.
495 * The passed link state must always match the link state returned
496 * by cvmx_helper_link_get(). It is normally best to use
497 * cvmx_helper_link_autoconf() instead.
498 *
499 * @ipd_port:  IPD/PKO port to configure
500 * @link_info: The new link state
501 *
502 * Returns Zero on success, negative on failure
503 */
504int __cvmx_helper_sgmii_link_set(int ipd_port,
505				 cvmx_helper_link_info_t link_info)
506{
507	int interface = cvmx_helper_get_interface_num(ipd_port);
508	int index = cvmx_helper_get_interface_index_num(ipd_port);
509	__cvmx_helper_sgmii_hardware_init_link(interface, index);
510	return __cvmx_helper_sgmii_hardware_init_link_speed(interface, index,
511							    link_info);
512}
513
514/**
515 * Configure a port for internal and/or external loopback. Internal
516 * loopback causes packets sent by the port to be received by
517 * Octeon. External loopback causes packets received from the wire to
518 * sent out again.
519 *
520 * @ipd_port: IPD/PKO port to loopback.
521 * @enable_internal:
522 *                 Non zero if you want internal loopback
523 * @enable_external:
524 *                 Non zero if you want external loopback
525 *
526 * Returns Zero on success, negative on failure.
527 */
528int __cvmx_helper_sgmii_configure_loopback(int ipd_port, int enable_internal,
529					   int enable_external)
530{
531	int interface = cvmx_helper_get_interface_num(ipd_port);
532	int index = cvmx_helper_get_interface_index_num(ipd_port);
533	union cvmx_pcsx_mrx_control_reg pcsx_mrx_control_reg;
534	union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg;
535
536	pcsx_mrx_control_reg.u64 =
537	    cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
538	pcsx_mrx_control_reg.s.loopbck1 = enable_internal;
539	cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
540		       pcsx_mrx_control_reg.u64);
541
542	pcsx_miscx_ctl_reg.u64 =
543	    cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
544	pcsx_miscx_ctl_reg.s.loopbck2 = enable_external;
545	cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface),
546		       pcsx_miscx_ctl_reg.u64);
547
548	__cvmx_helper_sgmii_hardware_init_link(interface, index);
549	return 0;
550}